JPH04172697A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the area occupied by a semiconductor storage device and, at the same time, to make the device more highly integrated by constituting a memory cell of a memory cell for transferring information and memory cells for storage and connecting the bit line connected to one of the memory cells for storage with the bit line connected to the other memory cell for storage through a capacitor. CONSTITUTION:A memory cell 1 is divided into a memory cell 1a for transferring information and memory cells 1b for storage and one of the memory cells 1b for storage is connected to the other memory cell 1b for storage through a capacitor C. Accordingly, the cell 1a for transfer is used as a bit line BL and a transfer gate and bit-line collector can be omitted and the memory cell 1 can be connected to the bit line BL irrespective of the number, since stored information is sent to a sense amplifier from the memory cells 1b for storage through the memory cell 1a for storage through the memory cell 1a for transfer. Therefore, the area occupied by this semiconductor storage device can be suppressed to a small value and, at the same time, the device can be more highly integrated.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor memory device, and aims to provide a semiconductor memory device (SRAM) that has a small occupied area and is highly integrated. transistors,
and a load resistor connected to each of the transistors,
and a memory cell consisting of an individual capacitor interposed between the load resistor and the pinpoint line corresponding to each output point of the transistor, and two bit lines connected to the memory cell via the capacitor. a semiconductor memory device, wherein one of the positive side and negative side power supply lines for supplying current to the memory cell also serves as a word line, the memory cell being an information transfer memory cell and a memory cell. The bit line connected to the storage memory cell is connected to the bit line connected to another memory cell via a capacitor.

[Industrial application field]

The present invention relates to a semiconductor memory device, and specifically relates to a SRA
M (static random access
The present invention relates to a semiconductor memory device which is suitable for use in small memory devices and which reduces the occupied area.

In recent years, for example, SR has been used as a high-speed read/write memory.
Many semiconductor memory devices such as AM have been developed.

These semiconductor memory devices are becoming more and more highly integrated and dense, but SRAM uses a large number of transistors, making it difficult to achieve the goals of high integration and density. It becomes.

Therefore, countermeasures such as reducing the number of transistors and arranging the constituent elements are required.

[Conventional technology]

As a conventional semiconductor memory device of this type, for example,
, as shown in Figure 6.

FIG. 5.6 is a schematic circuit diagram showing a conventional semiconductor memory device, and FIG. 5 shows a high resistance load type SRA, M.
FIG. 6 shows a CMO3 type SRAM.

In FIG. 5, the memory cell l of the SRAM is roughly divided into data holding transistors Ql, Q2, transfer gate transistors Q3, . Q4, and load resistors R1 and R2.

Note that BL is a focus line, the tag is a word line, van is a positive current level, and VSS is a negative current level.

This SRAM is a so-called four-transistor two-resistance type, and as shown in the figure, two transistors Ql
, Q2 is for data retention, and the remaining two transistors Q3
．． Q4 is used for transfer gate.

The memory cell 1 of the SRAM shown in FIG. 6 is a CMOS (complemens memory cell) consisting of an N-channel transistor and a P-channel transistor, in which load resistors R1 and R2 in FIG. 5 are each replaced with P-channel transistors.
Tary metal oxide semiconductor
The so-called 2-in-harter is used.
The CMOS inverter is a two-transistor type, and the inno λ
Since the cell is formed of 0 MO3, the cell size is larger (although this results in lower power consumption and stable operation) compared to the conventional example shown in FIG.

Note that since these SRAMs have relative bit lines, one of the bit lines can be omitted and one of the transfer gate transistors can be saved.

[Problem to be solved by the invention]

However, in such SRAM, in general, the number of elements per memory cell is 6 in any system, in order to store and retain information without requiring a refresh operation, and other memories, such as DRA M (dyna
mic random access memory)
Compared to the above, the number of transistors per memory cell is large, so there is a problem that the area occupied in a plan view becomes large.

Ignoring the problem of reliability, it is possible to configure a memory cell with two resistors and 3F transistors, or a memory cell with two CMOS inverters and one transistor, but this has not been put to practical use.

Therefore, transfer gate transistor Q3゜Q4
It is also conceivable to use a capacitor instead to reduce the number of transistors and reduce the area occupied in plan view. In other words, the capacitor does not need to be formed on the surface of the semiconductor substrate and can be placed on top of other elements.
This is because the occupied area seen in a plane becomes unnecessary.

However, in this case, the number of memory cells that can be connected to the bit line is reduced from several to one due to the parasitic capacitance caused by the bit line BL.
A new problem arises that the number of items is limited to 0 or more,
Not practical.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device (SRAM) that has a small occupied area and is highly integrated.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory device according to the present invention includes two transistors whose gates are cross-connected, a load resistor connected to each of the transistors, and a focus line B corresponding to each output point of the load resistor and the transistor.
A positive polarizer that supplies current to the memory cell 1 includes a memory cell 1 consisting of an individual capacitor interposed between the LOs, and two bit lines BL connected to the memory cell 1 via the capacitor C. A semiconductor memory device in which either one of the side or negative side power supply line also serves as a word line hole,
The memory cell 1 consists of an information transfer memory cell 1a and a storage memory cell 1b.
The bit line BL connected to the bit line BL is connected via a capacitor C to a pinto line BL connected to another memory cell.

Also, two sets of CMOS whose gates are cross-connected
A memory cell 1 consisting of an inverter and individual capacitors interposed between an inverter and a bit line corresponding to each output point of the CMOS inverter, and two bit lines connected to the memory cell 1 via the capacitors. BL, and one of the positive and negative power supply lines for supplying current to the memory cell 1 also serves as a word line, wherein the memory cell 1 is an information transfer memory. The bit line BL connected to the memory cell 1b is configured to be connected via a capacitor C to a bit line BL connected to another memory cell. are doing.

[Function] In this embodiment, the memory cell is an information transfer memory cell,
The storage memory cells are connected to other memory cells via capacitors.

That is, since memory information is sent from the storage cell to the sense amplifier through the transfer cell, the transfer cell replaces the bit line, the transfer gate and bit line contact are omitted, and any number of memory cells can be connected to the bit line. connected to.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

2 to 4 are diagrams showing one embodiment of the semiconductor memory device according to the present invention. In FIG. 2, the same numbers as those given to the conventional example shown in FIGS. 5-6 indicate the same parts. show.

FIGS. 2(a) and 2(b) show the memory cell 1 shown in FIG.
2(a) is a circuit diagram of the conventional transfer gate transistor Q3. shown in FIG. 5.
By using capacitors CI and C2 in place of Q4, as shown in Fig. 2 (
In the case shown in 1)), the number of transistors per memory cell is reduced by using capacitors C1 and C2 in place of the transfer gate transistors f13 and Q4 of the conventional example shown in FIG.

That is, the capacitor CLC2 is a semiconductor substrate, for example,
There is no need to form it on the surface of a silicon wafer or the like, and it can be installed on top of other elements, so the area it occupies in plan view can be reduced.

In addition, in Fig. 2 (a) and (b), A, B
indicate connection points (nodes) within the memory cell 1, respectively.

Data holding transistor Ql in this embodiment.

Ω4, channel length, and channel width are both 1 μm, and other transistors Q5. Q6 is composed of a MOSFET with a channel length of 1.2 μm and a channel width of 1 μm.

The load resistors R1 and R2 are made of polysilicon resistors that are not doped with impurities or doped with a small amount of impurities, and have a resistance of 100
The resistance value is set to MΩ.

This polysilicon resistor exhibits a very high resistance, so it can supply the minimum load current to maintain the “H” output of the inverter section, and since polysilicon has a high non-resistance, the resistor The occupied area can be reduced.

The capacitors C1 and C2 are located, for example, between the gate electrodes of the data holding transistors Q1 and Q2 and the bit line BL, and have a capacitance of about 5 to 1 ofF.

Since the capacitors C1 and C2 can be formed on the data holding transistors Q2, the area occupied by the capacitor CLC2 itself becomes unnecessary when viewed from above, and the integration of the SRAM can be improved.

Note that the capacitors C1 and C2 may be formed in a layer different from the data holding transistors Ql and Q2.

Next, the effect will be explained.

FIGS. 3 and 4 are timing charts for explaining the operation of this embodiment. FIG. 3 shows the operation at the time of reading, and FIG. 4 shows the operation at the time of writing. Note that the horizontal axis is the time axis.

First, the operation at the time of reading will be explained based on FIG.

When not selected, the power supply voltage of memory cell 1, that is, the level of the word line hole is 1/2 (in this case, 2.5V)
, the level at connection point A is "H" and the level at connection point B is "L".

At the time of selection, the power supply voltage of memory cell 1, that is,
■The level of the word line hole. . (5V in this case), the voltage at the connection point A can be changed by VDD/2 without changing the voltage at the connection point B. This voltage fluctuation is transferred to the information transfer memory cell 1a arranged next to the storage memory cell 1b by the capacitor C1°C2, and is stored as transfer information.

Information transfer between the information transfer memory cells 1a+1a' is performed in the same manner as the information transfer between the storage memory cell 1b and the information transfer memory cell 1a, and is ultimately transferred to a sense amplifier (not shown). Ru.

Next, the operation at the time of writing will be explained based on FIG.

First, the power supply voltages of the information transfer memory cell 1a and the storage memory cell 1b, that is, the level of the word line hole, are set in 5. (in this case, OV), and based on the information to be written, set the level at connection point A to "°°H" and the level at connection point B to "L" (or set the level at connection point A to "L", and set the level at connection point A to "L", The level at point B is “Hpa)
shall be.

In this state, the power supply voltage of the information transfer memory cell la' to which information is to be transferred is raised, and the write information of the information transfer memory cell 1a is transferred to the information transfer memory cell la'.

Then, almost at the same time that information is transferred to the information transfer memory cell ta+, the storage memory cell 1 at the destination address
By raising the power supply voltage of b, information is written into this storage memory cell 1b.

In this embodiment, one information transfer memory cell is provided for every two storage memory cells, but an information transfer memory cell may be provided for each of a large number of storage memory cells.

As described above, according to this embodiment, the memory cells are divided into information transfer memory cells and storage memory cells, and the storage memory cells are connected to other memory cells via capacitors. Storage information can be sent from the storage memory cell to the sense amplifier through the information transfer cell, and the information transfer memory cell can be used in place of a bit line.

Therefore, the transfer gate and the bit line contact can be omitted, and an unlimited number of memory cells can be connected to the bit line.

In addition, the number of transistors is reduced by two compared to the conventional example,
Since there is no need to use bit line contacts, device reliability can be increased and cell area can be reduced.

Note that the above embodiment is explained by taking as an example a case in which a capacitor is provided between a storage memory cell and another memory cell, but in this embodiment, a capacitor is provided on the bit line side of the storage memory cell. Since a capacitor is provided in advance, this capacitor may be omitted.

Further, in the above embodiment, the power supply wiring connected to the load resistor is used as the word line, but the present invention is not limited to this, and the power supply wiring connected to the data holding transistor may be used as the word line.

(Effects of the Invention) In the present invention, memory cells are divided into information transfer memory cells and storage memory cells, and the storage memory cells are connected to other memory cells via capacitors, thereby making it possible to create information transfer memory cells. Storage information can be sent from the storage cell to the sense amplifier through the cell, and the information transfer memory cell can be used in place of a bit line.

Therefore, transfer gates and bit line contacts can be omitted, and an unlimited number of memory cells can be connected to bit lines.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIGS. 2 to 4 show an embodiment of the semiconductor memory device of the present invention, FIGS. 2(a) and 2(b) are circuit diagrams showing the memory cells thereof, and FIG. FIG. 4 is a timing chart for explaining the read operation, FIG. 4 is a timing chart for explaining the write operation, FIGS. 5 and 6 show a conventional semiconductor memory device, and FIG. 6 is a circuit diagram showing a high resistance load type SRAM, and FIG. 6 is a circuit diagram showing a CMO three-way SRAM. 1...Memory cell, 1a+1a'...Memory cell for information transfer, 1b
...Memory cell for storage, +2LQ2...Transistor for data retention, Q
3. Q4... Transfer gate transistor, Q5. Q6...P channel transistor, R1
, R2... Load resistance, CI, C2... Capacitor, BL... Pinto line, Ridge... Word line, VOO...... Positive side power supply level, VSS...Negative side power supply level. C: Capacitor Principle diagram of the present invention Figure 1 (a) (b) Circuit diagram showing a memory cell of one embodiment Timing chart for explaining the read operation of one embodiment Fig. 3 Timing chart for explaining the write operation of the present embodiment Fig. 4 Circuit diagram showing a high resistance load type SRAM Fig. 5

Claims (2)

[Claims] (1) Two transistors whose gates are cross-connected, a load resistor connected to each transistor, and an individual bit line interposed between the load resistor and the bit line corresponding to each output point of the transistor. A memory cell consisting of a capacitor, and two bit lines connected to the memory cell via the capacitor, and either a positive side or a negative side power supply line that supplies current to the memory cell. is a semiconductor memory device in which the memory cell also serves as a word line, the memory cell is composed of an information transfer memory cell and a storage memory cell, and the bit line connected to the storage memory cell is connected to another memory cell. A semiconductor memory device characterized in that it is connected to a connected bit line via a capacitor. (2) Two sets of CMOS whose gates are each cross-connected
A memory cell consisting of an inverter and an individual capacitor interposed between an inverter and a bit line corresponding to each output point of the CMOS inverter, and two bit lines connected to the memory cell via the capacitor. A semiconductor memory device, wherein one of a positive power supply line and a negative power supply line for supplying current to the memory cell also serves as a word line, wherein the memory cell is a memory cell for information transfer and a memory cell for storage. 1. A semiconductor memory device comprising a memory cell, wherein the bit line connected to the storage memory cell is connected to a bit line connected to another memory cell via a capacitor.