JPH0269846A - Error detection and correction device - Google Patents

Abstract

PURPOSE:To improve the reliability of data by means of simple circuit constitution by adding and outputting an inversion bit at the time of writing data into a memory circuit, inputting normal data and inversion data at the time of reading data from the memory circuit and diagnosing the correction of an error detection correction logic. CONSTITUTION:A bit which is intentionally inverted is added and written into the memory circuit 1, and a word including the inverted bit and a word including the normal bit are time-divisionally read. The right or wrong of the error detection and correction logic in the error detection and correction circuit 2 is diagnosed by detecting and correcting errors in the same error detection and correction circuit 2, and comparing respective results. Thus, logical abnormality can speedily be detected even if it occurs in the error detection and correction circuit, and the occurrence of problems which is to output data that have erroneously been decoded (corrected) and which where the error abnormality of data being left as it is reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is an error detection and correction method that detects bit errors and corrects Ω-bit errors by adding an M-bit redundant word to N-bit word data. Regarding the equipment,
In particular, the present invention relates to an error detection and correction device with an error detection and correction logic diagnostic function that further improves data reliability by determining whether error detection and correction logic is correct and detecting malfunctions of the error detection and correction logic.

[Prior Art] In systems that operate under environmental conditions where errors are likely to occur or systems that require high reliability, error detection and correction devices are used to improve data reliability.

FIG. 5 is a block diagram of a conventional error detection and correction device.

In the figure, l is a memory circuit that stores an N-bit data word and an M-bit redundancy word (N and M are natural numbers). Further, numeral 2 is an error detection and correction circuit that detects errors in 2-bit data and corrects Q-bit errors. This error detection and correction circuit'l
@2 adds an M-bit redundancy word to an N-bit data word to detect errors up to 1 (bit) and further correct errors to correct data up to Q bits. Therefore, the memory circuit l and the error detection and correction circuit 2, environments where the memory circuit 1 is prone to bit-flipping soft errors caused by radiation, or environments where high reliability is required such as for space development or air traffic control. It serves to maintain an N-bit data word at the correct value in such systems.

Further, at this time, the error detection function of the Q bit and the error correction function of the Q bit are performed by the logic of the encoding circuit 3 and the decoding circuit 4.

Next, the operation of this error detection and correction circuit 2 will be explained.

First, N data words DW= (DB8. . . . , DB . . .
, DB, -1) (where l is a natural number such that l≦N-1) is latched by the encoding circuit 3. Then, the encoding circuit 3 uses an M-bit redundancy word CW=
(CB8...., CB..., CB□,)
After creating the data word DW, the data word DW is output to the data word bus 6 without any processing, and the created redundant word F' CW is output to the redundant word bus 7. Furthermore, the memory circuit 1 stores this (N+M) bit data, that is, an N-bit data word DW and an M-bit redundancy word CW.

On the other hand, when data is output from the memory circuit l,
The decoding circuit 4 latches the N-bit data word DW output from the data word bus 6 and also latches the M-bit redundancy word CW output from the redundancy word bus 7. Then, the encoding circuit 3 decodes the M-bit redundant word CW using the reverse logic. On this occasion,
(N+M) bits of data are correctly detected errors up to the total number of error bits l(bit, and the number of error bits is '(
k' is a natural number such that '≦. ) is output to the error detection signal line 8 as an error detection signal. Further, errors are correctly corrected up to a certain bit Q according to a predetermined logic, and the corrected data is output to the human output data bus 3.

Conventional error detection and correction devices perform the processing described above.

[Problems to be Solved] The conventional error detection and correction device described above has the following problems.

■When a failure occurs in the encoding circuit that creates redundant bits in the error detection and correction circuit or the decoding circuit that detects and corrects errors and the encoding or decoding logic is incorrect, the output data may be incorrectly corrected. The reliability of the system is significantly lowered due to errors being detected or false errors being detected.

■It is difficult to determine whether the failure is in the memory circuit or the error detection circuit just by monitoring the error detection signal.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an error detection and correction device capable of diagnosing the correctness of error detection and correction logic using a simple circuit configuration.

[Means for Solving Problems] In order to achieve the above object, the error detection and correction device of the present invention includes an (N+M+1) bit memory circuit, an error detection and correction circuit that performs k-bit error detection and Q-bit error correction, and the above-mentioned. On the data bus between the memory circuit and the error detection and correction circuit, when writing data to the memory circuit, an inverted bit, which is one bit of the input data, is added and output, and when reading data to the memory circuit, the above bit is added and output. A bidirectional buffer that selects and outputs normal data that does not include an inverted bit and inverted data that replaces the normal data with the inverted bit, and a bidirectional buffer that selects and outputs normal data that does not include the inverted bit and inverted data that replaces the normal data with the inverted bit, and 1. The normal data and the inverted data as described in 1. The configuration includes a diagnostic circuit that inputs the input signal and diagnoses whether the error detection and correction logic is correct or incorrect.

With this configuration, when data is written to the memory, a bit that has been inverted by one bit is also written, and when reading, error detection and correction processing for normal data and error detection and correction processing for one-bit inverted data are performed in a time-sharing manner. A diagnostic circuit compares each value to determine whether the error detection and correction logic is correct.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of an error detection and correction device according to an embodiment of the present invention, FIG. 2 is a diagram showing data processing in the error detection and correction device of FIG. 1, and FIG. 3 is a diagram of the error detection and correction device of FIG. FIG. 3 is a block diagram of a diagnostic circuit in the error detection and correction device.

Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

In FIG. 1, 1 is a memory circuit for storing (N+M+1) bit words, and 2 is an error detection and correction circuit having a 2-bit error detection function and a Q-bit error correction function. In this error detection and correction circuit 2, an encoding circuit 3, which is an internal circuit, latches an N-bit data word DW input from an input data bus 5, and converts each bit of the data word DW based on a certain predetermined logic. Correspondingly, an M-bit redundancy word CW for error detection and correction is created.

After creating the redundant word CW, the input data word DW is output as is to the data word bus 6, and the created redundant word CW is output to the redundant word bus 7.

On the other hand, when the error detection and correction circuit 2 receives data from the memory circuit l, the decoding circuit 7
and the (+'J+M) bit data of the redundant word bus 7 are latched and decoded using the reverse logic of encoding. That is,
(errors within bits are detected, errors within Q bits are corrected and output to the human output data bus 3. Also, if a 'bit error is detected, rk'
Information indicating that there is an error in the number of bits is output to the error detection signal line 8.

Next, 9 is a bidirectional buffer, and data word bus 6
Connected to any bit 1 above.

When the memory circuit 1 is in the write mode, the same signal is output to the DB signal line of the data word bus 6 for the input data pin DB, and an inverted signal DB is output.
is output to the diagnostic bit line 10.

Furthermore, when the memory circuit l is in the read mode, the DB
It has a function of connecting only to either the signal line or the diagnostic bit line IO.

This bidirectional buffer 9 performs the following processing when the memory circuit 1 is in the read mode. That is, D.B.
When connected to the signal line, the decoding circuit 7 outputs the data word DW=(DB,,-,DB,.

..., DBN-1) is latched and connected to the diagnostic bit line 10, the decoding circuit 7 sets DW=(DBe
.

..., DB, ..., DBN-4).

In this way, the bidirectional buffer 9 is connected to the error detection and correction circuit 2.
This circuit creates a -bit error in order to diagnose the correctness of the error detection and correction logic of the circuit, and has the function of switching between a data word with an intentional one-bit error and normal data. It also has a function of time-divisionally sending normal data and 1-bit error data (inverted data) to the error detection and correction circuit 2.

Further, 11 is a control signal line, and the bidirectional buffer 9 is connected to the bit signal line DB in the read mode of the memory circuit l.
A control signal is transmitted to control which of the diagnostic bit line 10 and the diagnostic bit line IO is connected.

A diagnostic circuit 12 determines whether the logic of error detection and correction in the error detection and correction circuit 2 is correct or incorrect, and outputs the result of the diagnosis to the diagnostic signal line 13.

Now, FIG. 2 shows data processing in the memory circuit 1 and the error detection and correction circuit 2 when no bit error occurs.

Here, the input data 21 is an N-bit data word DW input from the human output data bus 5 and latched by the encoding circuit 3. The memory write data 22 is then written to the memory circuit l (a data word of N+M+ 1> bits and a data word of N bits D
W and the N-bit redundant word F' created by the encoding circuit 3
It consists of CW and DB which is inverted from DB by the bidirectional buffer 9. Further, the memory read data word 23 is a data word read when the bidirectional buffer 9 is connected to the bit signal line DB.

The error detection and correction output data word 24 is the data word after the memory read data 23 is checked by the decoding circuit 4.

On the other hand, the diagnostic data read word 25 is a data word when the bidirectional buffer 9 is connected to the diagnostic bit line 10. The redundant word CW in this diagnostic data read word 25 is the input data word DW=(DB
8. ..., DB,, ...DBN-1) Since it was created for 21, the diagnostic data read word DW= (DB8゜..., DB,, ...
. . , DB, . ) 25 data words will have a - bit error.

Therefore, when the diagnostic data read word 25 is input to the decoding circuit 4, a bit error in DB is detected,
A one-bit error detection signal is sent to the error detection signal line 8. Then, DB is error-corrected to DB,
After error detection and correction, the data word 16 is output to the human output data bus 5.

Now, FIG. 3 shows the configuration of the diagnostic circuit 12.

In the figure, 31 is an N-bit latch circuit (latch A) that latches the error detection and correction output data word;
is a latch circuit (latch B) that latches the data 26 after error detection and correction. Further, 33 is a latch control circuit that uses the control signal line 11 to create latch timings for the latch 31 and latch 32, and the latch timings for the latch 31 and latch 32 are output as a latch control signal 34 and a latch control signal 35, respectively. Ru.

On the other hand, when data is latched in both the latch 31 and the latch 32, N-bit data is input to the determination circuit 38 via the latch A output data line 36 and the latch B output data line 37, respectively. Further, the number of error detection bits of the data in the latch 31 and the detection pitch I k B of the latch 32 are also input via the error detection signal line 8 . Then, the determination circuit 38 determines whether the error detection and correction logic in the error detection and correction circuit 2 is correct or incorrect based on the logic shown in the table of FIG.

In other words, since the number of error correction bits of the error detection and correction circuit 3 is Q, errors should be completely corrected when the number is (Q-1) or less. Therefore, when the values of the latch 31 and the latch 32 are not the same, it is determined that an error has occurred in the error correction function, and "correction function error" information is output to the diagnostic signal line 13.

Furthermore, since the number of detectable bits is k, an error detection signal should be sent from the error detection signal line 8 when (k-1) or less errors occur.

Therefore, when there is no detection signal, there is an "error detection function abnormality".
It is output to the diagnostic signal line 13 as a signal.

In this way, in this embodiment, intentionally inverted bits are added and written into the memory circuit, and a word containing the inverted bits and a word containing normal bits are read out in a time-sharing manner using the same error detection and correction circuit. By performing error detection and correction and comparing the respective results, it is possible to effectively diagnose whether the error detection and correction logic of the error detection and correction circuit is correct.

Therefore, even if a logic abnormality occurs in the error detection and correction circuit, it can be detected quickly, and problems such as outputting erroneously decoded (corrected) data or leaving data error abnormalities unattended are reduced.

It should be noted that the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the above embodiment, the bits to be inverted for diagnosis are referred to as data bits DB, but it is also possible to arrange the bidirectional buffer 9 on the redundant word bus 6 and invert CB to CB. (not shown), the diagnostic circuit may be the same, and the same diagnostic function can be obtained.

[Effects of the Invention] As explained above, the present invention improves data reliability with a simple circuit configuration, and prevents system failures, stoppages,
This has the advantage that it is possible to provide an error detection and correction device that can effectively prevent the adverse effects of malfunctions.

In addition, since the inversion bit, which is error information for diagnosis, is stored in the memory circuit, the same diagnosis can be executed many times, increasing the reliability of the diagnosis result, It is also very effective in isolating failures in detection and correction circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an error detection and correction device according to an embodiment of the present invention, FIG. 2 is a diagram showing data processing in the error detection and correction device of FIG. 1, and FIG. 3 is a block diagram of an error detection and correction device of FIG. A block diagram of the diagnostic circuit in the device, Figure 4 is the first
A table showing the logic of the error detection and correction device shown in FIG. 5 is a block diagram of a conventional error detection and correction device. l: Memory circuit 2: Error detection and correction circuit 9: Bidirectional buffer 13: Diagnostic circuit

Claims (1)

[Claims] An (N+M+1) bit memory circuit, an error detection and correction circuit that performs k-bit error detection and l-bit error correction, and an input on a data bus between the memory circuit and the error detection and correction circuit when writing data to the memory circuit. An inverted bit, which is one bit of data inverted, is added and output, and when data is read into the memory circuit, normal data that does not include the inverted bit and inverted data that replaces the normal data with the inverted bit are selected. and a diagnostic circuit that inputs the normal data and the inverted data when reading data from the memory circuit and diagnoses whether the error detection and correction logic is correct. correction device.