JPH0268994A - Alignment deviation measuring device in manufacturing of multilayer printed circuit board and measuring method - Google Patents

Abstract

PURPOSE: To obtain a method for non-destructively rapidly measuring alignment deviations of layers with a low cost by attaching a plurality of vernier scales to materials of the layers, then positioning them on a translucent main reference unit attached with the scales, and reading the superposed scales. CONSTITUTION: After a plurality of vernier scales 13 are attached to a substance layer 1 used for a multilayer printed circuit board, and the layer 1 is positioned on a translucent main reference unit 10 attached with the scales 13. The superposed scales 13 are read with respect to the unit 10, and hence an alignment deviation of the layer 1 is measured. For example, one set of positioning pins 12 are provided, the layer 1 of a copper-clad glass epoxy board provided at four corners with the scales 13 is aligned on the unit 10 disposed at corners of an upper surface of a glass plate 11 with perpendicularly crossed sets of the scales 13. The unit 10 is illuminated from its lower surface, and the superposed scales 13 are read.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method and apparatus for measuring alignment deviation characteristics using a vernier method, particularly in the manufacture of multilayer printed circuit boards.

[Prior art and its problems]

Large scale integrated circuits (LSI) and very large scale integrated circuits (V
Printed circuit board (PCB) technology has changed significantly with the introduction of LSI.

The interconnections between elements in LSIs and VSLrs are enormous and complex, and printed wiring now occupies a larger portion of the PCB area than the elements.

Thus, multilayer PCBs began to be used, which make connections within the circuit board rather than on the surface, significantly reducing the PCB surface area required for the connections. Internal layers also serve as power or ground planes, and provide heat sinking mechanisms and electrical shielding properties.

One of the major issues with multi-Jli PCBs is accurately maintaining glabellar alignment during manufacturing. There are several factors contributing to misalignment, including temperature and humidity changes, positioning issues, bonding mechanism shrinkage, uneven lamination pressure, high moisture content in the glass epoxy substrate, and heat in various layer materials. Includes differences in expansion and heat contraction properties.

For actual manufacturing, photo tools are usually used.
) is created. Laser plotting systems are most commonly used to create phototools. Laser plotting systems transfer circuit artwork to silver halide or diazo film.

After the film is exposed to a laser, it is developed and checked for dimensional accuracy.

In a simplified multilayer PCB manufacturing process, a pre-sized copper-clad glass epoxy substrate is placed using positioning pinholes. Locating pins are placed on the base and sized to hold the various film and layer materials in place during the manufacturing process. The copper-clad PCB is then cleaned and photoresist is applied. The next step is the transfer of the artwork image. This is accomplished by positioning a phototool (silver halide or diazo film) on the copper surface using paste and locating pins.

The photoresist and phototool are then exposed to a light source of the appropriate wavelength to polymerize the areas of the copper surface not covered by the phototool. Next exposed blank
and remove the unexposed photoresist. The exposed copper is then etched and the polymerized photoresist is removed. Prior to lamination, the etched PCB must be inspected to ensure that the printed circuit is free of defects. The etched boards are then cleaned, dried and prepared for lamination. Several layers for a multilayer PCB can be fabricated using the process described above. The layers are then aligned relative to the locating pins of the lamination jig. Heat and pressure are applied to the lamination jig to flow the epoxy within the substrate and bond the layers together. After lamination, interlayer connection holes are made. The connection holes and printed circuit are then photosensitized using an electroless copper bath. Using the same process as above, we now create a multilayer PCB
etching the unetched external surface of the The PCB is then electroplated with copper and tin-lead. The photoresist is then stripped and the exposed copper is etched away. Next, open the unplated through holes and adjust the outline of the board to give it its final shape.

Alignment of each layer of the PCB is a problem.

L I EBMAN is U.S. Patent No. 3,591,28
4 describes an apparatus for assisting in the layout and design of multilayer printed circuit boards. The device uses a three pin positioning system and a translucent grid layer. LI EBMAN's equipment positions a polyester sheet over the grid layer and designs circuits on the polyester sheet. Although this equipment can align several layers of large features, it does not have a means to measure alignment deviations, and the tolerances required by today's technology are within a few ten thousandths of an inch. Cannot be used to produce artwork.

US Pat. No. 4,647 for measuring mask misalignment in IC manufacturing by HENDERON et al.
The 850 can measure alignment deviations on the order of 1 micron. During IC manufacturing, multiple sets of conductors are incorporated into the IC. Each set is provided with a different incremental distance between its two conductors. The individual conductors of each set are incorporated into different adjacent layers. After forming two adjacent layers, the alignment deviation can be determined by making electrical connections to the conductors. If the conductors of each pair are in contact with each other, current will flow through the "switch".

In this way, a few incremental sets can be digitally analyzed to determine the overall alignment deviation. The problem with applying this process to multilayer printed circuit board manufacturing is that adjacent layers of the printed circuit board are usually Neither material can be electrically conductive, so one side of the "switch" is necessarily non-conductive.A further disadvantage of this measurement technique is that it requires complex and expensive processes and measurements. , which is unsuitable for printed circuit board manufacturing.

Traditionally, destructive analytical techniques have been used to obtain the dimensional stability and spatial relationships of all layers. In this analysis technique, multilayer P
A small section of CB is analyzed under the microscope. This technique necessarily requires destruction of the multilayer printed circuit board, requires expensive analytical equipment, and is also time consuming.

OBJECTS OF THE INVENTION The present invention provides a nondestructive method for quickly and inexpensively measuring alignment deviations in each layer, and improves the apparatus and method for measuring alignment deviations typically associated with the manufacture of multilayer printed circuit boards. It is to provide.

[Summary of the invention]

These objectives are achieved by applying multiple sets of orthogonal vernier scales to each layer of material during the manufacturing process. After processing each layer, each layer is measured against a translucent or transparent primary reference body to detect alignment deviations. The translucent primary reference is typically a flat translucent sheet, such as glass, an etched or plated laminate, a solder mask, or a phototool. This primary reference body has one or more vernier scales on its surface, for example a set of orthogonal vernier scales at each corner. The primary datum is further fitted along its edges with a set of locating bins or holes extending vertically upward from the top surface. As each layer is positioned on the main datum, the vernier scale on each layer material is superimposed on the vernier scale on the main datum. The alignment deviation is then measured by reading the superimposed vernier scale.

〔Example〕

FIG. 1 is a flowchart of the three main steps of the vernier method for measuring deviation in multilayer PCBs according to the present invention. The first step 14 is to attach vernier scales to the individual layer materials. These layers may be phototools, etched or plated laminates, solder masks, and copper-clad glass epoxy substrates. This layer is then processed. The next step 15 in the vernier measurement method is to align the layer or layers of interest onto the translucent primary reference. The final step 16 is to measure the alignment deviation by reading the overlapping vernier scales using a small magnifying glass. In practice, we found that by illuminating the main reference body from below, the overlapping vernier scales became much easier to read.

A preferred apparatus for vernier analysis of multilayer printed circuit boards, ie, a translucent primary reference indicated at 10, is shown in FIG. The translucent main reference body 10, also referred to as master 10, in this embodiment is constructed of a glass plate 11 and has a 1 m alignment pin 12 projecting upward from its upper surface. A set 13 of orthogonal vernier scales is attached to the upper surface of the glass plate 11 (etched in this case), conveniently located at each corner.

In use, material Nl, such as a photo tool, copper-clad glass epoxy board or solder mask, is placed onto master 10 by inserting alignment pins 2 into alignment holes 2, or by any other suitable known alignment method. Can be matched. There are identical vernier scales 13 at the four corners of the material layer 1.

After processing the material layer 1, the material layer 1 can be aligned again on the master 10 and any alignment deviations can be measured by reading the overlapping vernier scales 13. Depending on the translucent properties of the material layer 1, the translucent sheet of glass 11 can be illuminated from the back and the overlapping vernier scales 13 can be easily read. FIG. 3 shows an enlarged view of overlapping linear vernier scales 13, each with a series of graduations clearly indicating equal increments. The incremental pitch can be modified to match the resolution of the printed circuit artwork. The vernier scale 13 is shown slightly shifted, and the matching portion of the scale is indicated by an arrow.

〔Effect of the invention〕

As explained above, in the present invention, alignment characteristics can be measured simply by attaching a vernier scale to the material layer to be processed. More practically, combined with visual interpolation between scale lines, field technicians can accurately measure deviations of a few ten thousandths of an inch using only a 10x handheld magnifier. be.

Although preferred embodiments of the present invention have been shown and described, the present invention is not limited to these embodiments, and can of course be realized in various forms within the scope of the following claims.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of the measuring method according to the present invention. FIG. 2 is a perspective view showing a translucent main reference body and one material layer used in the apparatus and method of the present invention. FIG. 3 is an enlarged view showing the overlapping state of the vernier scales used in the present invention. 10: Translucent main reference body, 12: Positioning pin, 13: Vernier scale, 1: Material layer, 2: Hole F/G 2 FIG, J

Claims (2)

[Claims] (1) attaching a plurality of vernier scales to a material layer used in a multilayer printed circuit board; positioning the material layer on a translucent main reference body to which the vernier scale is attached; the translucent main reference member; A method of measuring alignment deviations in multilayer printed circuit board manufacturing, comprising: measuring alignment deviations of said material layers by reading overlapping vernier scales. (2) a flat translucent plate provided with a plurality of vernier scales; and means provided on the translucent plate for positioning a material layer for a multilayer printed circuit board disposed on the translucent plate; Alignment deviation measurement equipment in multilayer printed circuit board manufacturing, including.