JPH0268649A - Interruption control method - Google Patents

Abstract

PURPOSE:To occupy a system bus impartially by each slave processor by making an interruption signal enter each slave processor module at every constant time with an interval. CONSTITUTION:A timer 11 outputs the interruption signal at every constant time, and it is sent to a main processor module 20 and slave processor modules 30, 40, and 50 via a signal line 12. A main processor 21 writes the data of the moving command in each axis of a numerical controller, etc., on a shared RAM 22 by the interruption signal. Each of the slave processors 31, 41, and 51 reads the data of the shared RAM. Here, a time to occupy the system bus 13 by the slave processor is decided to some extent, and the time is found in advance, and the interruption signal arrives keeping the interval of that time. In such a way, each slave processor can acquire a right in using the bus impartially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method in a multi-processor system, and more particularly to an interrupt control method that allows each slave processor to equally monopolize a system bus.

[Conventional technology]

2. Description of the Related Art Numerical control devices, robot control devices, and the like use multi-processor systems that use a plurality of processors to control a large number of axes at high speed.

In particular, in numerical control devices or robot control devices, the main processor writes common data for each axis to be controlled, such as axis movement pulses, into a shared memory, and the slave processors that control each axis simultaneously share the data to read it. Access memory. In such a case, a bus arbitration circuit or the like is provided so that each slave processor can equally use the system bus.

[Problem to be solved by the invention]

However, if each slave processor tries to access the shared memory at the same time, it will eventually compete for the right to use the system bus, and some of the slave processors will experience increased latency and
The overall processing speed decreases. For example, if the number of slave processors is m, the time it takes to read one word of shared memory is τa, and n words of data are read, then the time it takes for the slave processor with the worst conditions to acquire the right to use the bus is ( It can be expressed as 1/2)m(m+1)·n-ra.

The present invention has been made in view of these points, and it is an object of the present invention to provide an interrupt control method that allows each slave processor to equally monopolize a system bus.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an interrupt control method in a multi-processor system, in which an interrupt signal is periodically generated, and each slave processor transmits the interrupt signal to the system bus. An interrupt control method is provided, characterized in that an interrupt signal is caused to arrive at each of the slave processors at exclusive time intervals.

[Effect]

The amount of time that a slave processor has exclusive use of the system bus is regulated to a certain extent, and by determining this time in advance and having interrupt signals arrive at intervals equal to that amount of time, each slave processor has equal rights to use the bus. can be obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a block diagram of a multi-processor system for implementing the interrupt control method of the present invention. Here, a numerical control device will be explained as an example of a multi-processor system. In the figure, 10 is a timer module, which has a timer 11 inside. 12 is an interrupt signal line, and 13 is a system bus composed of multipaths.

A main processor module 20 includes a main processor 21, a shared RAM 22, and the like. Other internal elements are omitted.

30, 40 and 50 are slave processor modules, and since each module has the same configuration, only the slave processor module 30 will be described. 3
1 is a slave processor, 32 is a delay circuit, and is connected to the interrupt signal line 12. Other RAM, ROM, etc. are omitted.

Next, an interrupt control method will be explained. The timer 11 outputs an interrupt signal TI at regular intervals, which is transmitted to the main processor module 20 and slave processor module 30, 40 through the interrupt signal line 12.
and sent to 50.

The main processor 21 uses this interrupt signal TI to share data such as movement commands for each axis of the numerical control device RA.
Write to M22. Each slave processor 31, 41 and 51 reads data from this shared RAM as follows.

First, it is assumed that the delay time of the delay circuit 32 of the slave processor module 30 is approximately O. Therefore, when the main processor 21 writes data to the shared RAM 22, the data is immediately read. Next, the delay time of the delay circuit 42 is assumed to be n° τ a +α. Here, τa is R shared by each slave processor.
The time to read one word of AM22 data, where n is the number of words and α is a margin, is about 30% of n·τa. Therefore, after the slave processor 31 reads the necessary data, the interrupt signal is sent to the slave processor 4.
Reach 1. Similarly, the delay time of the delay circuit 52 of the slave processor module 50 is assumed to be 2n·τa+β. Here, β is approximately the same value as the above-mentioned margin α, and a little margin is provided. As a result, the interrupt signal reaches the slave processor 51 from the delay circuit 52 when reading of data from the slave processor 41 is completed.

FIG. 2 shows a time chart of the usage state of the system bus of each slave processor described above, that is, the state of reading the shared RAM. In the figure, TI is timer 1
This is an interrupt signal from 1. As shown in the figure, each slave processor can read data from the shared RAM 22 by monopolizing the bus for the necessary time and time without conflict. As a result, wasted time such as processing for system bus arbitration and waiting time for requests to use the system bus is eliminated, and each slave processor can equally use the system bus.

In the above description, the time required for the main processor 21 to write data to the shared RAM 22 is assumed to be 0, but in reality, it is necessary to take this time into account. Specifically, the delay circuit 32 needs to have a delay time corresponding to that amount of time. Moreover, although the number of slave processor modules has been described as three, this number is just an example and can be applied to any slave processor module.

[Effects of the Invention] As explained above, in the present invention, the interrupt signal arrives at each slave processor module at regular intervals, so that each slave processor can avoid contention on the system bus. The system bus can be used equally, eliminating the need for processing such as system bus arbitration, and reducing system bus waiting time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multi-processor system for implementing the interrupt control method of the present invention, and FIG. 2 is a time chart showing the usage status of the system bus of each slave processor. 0−・−・−−−−−1−−−−Slave processor・
Modulet --- 1 --- Slave processor 2 --- Delay circuit 0 ---
−・−・・−Slave processor module 1−−−
−−−−・−−−−1−−・Slave processor 2−1−−−・−・−−−−1 Delay circuit patent applicant FANUC Co., Ltd. agent Patent attorney Takeshi Hattori 1−−−−− −−・・・−−−−1 timer 2−−−−−
−−−・・−・Interrupt signal line 3・−・−1−−−・−・−System bus 0−・・−−−−−−−−
・・−Main processor module 1−−−−−−−
−−−−−−−−Main processor 2・−−Shared memory

Claims (4)

[Claims] (1) In an interrupt control method in a multi-processor system, an interrupt signal is generated periodically, and the interrupt signal is sent to each slave processor at intervals of a time period during which each slave processor monopolizes the system bus. 1. An interrupt control method characterized in that: (2) The interrupt control method according to claim 1, wherein the multi-processor system is a numerical control device or a robot control device. (3) The interrupt control method according to claim 1, wherein the interrupt signal is shifted by a delay circuit within each slave processor unit. (4) The interrupt control method according to claim 1, wherein the time of the delay circuit is the time during which each of the slave processors monopolizes the system bus plus a certain tolerance value.