JPH0267591A - Drive circuit and thin-film el display device - Google Patents

Abstract

PURPOSE:To reduce the number of high-voltage resistant elements and the chip dimensions at the time of integration by providing a common switching element between terminals of plural circuits and an external power source connected with the terminals and causing an NPN transistor for driving a thyristor to drive a capacitive load also in addition to the thyristor. CONSTITUTION:At the time of charging picture elements with a high voltage, an NPN transistor 11 is turned on while a common switching element 16 is turned on. Then a thyristor 8 is turned on and the picture elements are charged. When the picture elements are discharged, on the other hand, the transistor 11 is turned on while the element 16 is turned off. Then the electric current discharged from the picture elements flows to the transistor 11 through an output terminal 3, diode 9, the cathode gate of the thyristor 8, and anode gate of the thyristor 8. Since the switching element 16 is turned off while the electric current flows, no high voltage is applied across the anode of the thyristor 8 and collector of the transistor 11. Therefore, the number of high-voltage resisting elements and the chip dimensions at the time of integration can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit and a display device using the circuit, and in particular to a pulsating device suitable for charging and discharging a capacitive load to a high voltage. The present invention relates to a circuit and a thin film EL display device using the drive circuit for driving data lines or scanning lines.

[Prior Art] Generally, driving a capacitive load such as an EL panel or a piezoelectric element requires a high voltage drive of several hundred square meters, and the drive circuit thereof is required to have a high withstand voltage. In addition, the drive circuits for matrix loads such as EL panels are required to integrate a large number of channels, but because they must be driven at high voltages,
Reducing the power consumption is an important issue when integrating devices.

As a prior art related to this type of drive circuit that aims to reduce power consumption and improve current drive capability, for example, Japanese Patent Laid-Open No. 60
A technique described in JP-A-208119 and the like is known. This type of conventional technology uses a thyristor as a switch.

FIG. 7 is a circuit diagram showing an example of a drive circuit according to the prior art. In FIG. 7, 6 is a logic circuit, 7 is a buffer circuit, 8 is a thyristor, 9 is a diode, 10.1
1 is an NPN transistor.

13 is a capacitive load, and 71.72 is a PMO5 transistor.

In general, a capacitive load drive circuit includes a source-side switch for charging the load and a sink-side switch for discharging the previously charged load. In the prior art shown in FIG. 7, a thyristor 8 is used as a source side switch, and an NPN transistor 1 is used as a sink side switch.
0 is set.

In FIG. 7, the anode of the thyristor 8 is connected to the high voltage application terminal 1, and its cathode is connected to the capacitive load 13.
The anode gate is connected to the collector of the NPN transistor 11, and the cathode gate is connected to the collector of the NPN transistor 10. Further, the anode of the diode 9 is connected to the cathode of the thyristor 8, and the cathode of the diode 9 is connected to the cathode gate of the thyristor 8. The emitter of the NPN transistor 11 is connected to the other high voltage application terminal 2 via the resistor 12, and its base is connected to the drain of the PMOS transistor 71 in the buffer circuit 7. Also, NPN
The emitter of the transistor 10 is connected to the other high voltage application terminal 2, and the base thereof is connected to the buffer circuit 7.
It is connected to the drain of the PMOS transistor 72 inside. The source of each PMOS transistor 71.72 is
It is connected to the low voltage power supply terminal 4. Further, a logic circuit 6 that controls the operation of the buffer circuit 7 according to a control input signal from the input terminal 5 is connected to the buffer circuit 7 . The capacitive load 13 is.

One end thereof is connected to the output terminal 3, and the other end is connected to the terminal 14.

The operation of driving an EL panel using the drive circuit configured as described above will be described below.

Generally, in an EL panel, a scanning side electrode to which a high voltage is sequentially and selectively applied, and a data side electrode to which a relatively low voltage is applied in synchronization with one emission/non-emission data, cross each other. An EL layer is formed between both electrodes. The portion sandwiched between the scanning side electrode and the data side electrode functions as one pixel, and is equivalently a capacitive load. The emission starting voltage is, for example,
As described in Japanese Patent No. 0-97394, etc., a high voltage of about 200V is required.

The capacitive load 13 in the circuit shown in FIG. 7 corresponds to one pixel in the EL panel, and the output terminal 3 corresponds to one scanning electrode. Actually, there are multiple pixels corresponding to the number of data-side electrodes for one scanning electrode, so multiple capacitive loads 13 are connected to the output terminal 3.
In the figure.

Only one capacitive load is shown for simplicity.

In the following description, the capacitive load 13 may be referred to as a pixel 13.

The terminal 14 to which the other end of the pixel 13 is connected corresponds to one data-side electrode if the output terminal 3 is one scanning electrode. In reality, as in the case of the scanning electrode described above, there are multiple pixels corresponding to the number of scanning electrodes for one data side electrode, but one scanning electrode as shown in FIG. The operation of the other scanning electrodes is similar, so the explanation thereof will be omitted.

Since EL panels have a polarization effect, they are generally driven by alternating current. In other words, even if a pixel that is charged with a certain electrode and emits light is subsequently discharged, polarization occurs in the direction that cancels the voltage polarity previously applied inside the EL, and the pixel is charged with the same polarity again. In this case, the luminance of the emitted light will decrease. The polarity of the voltage applied to the pixel to charge the pixel and cause it to emit light must be reversed each time it is driven.

The details of the method for driving this type of EL panel are described in, for example, Japanese Patent Laid-Open No. 123883/1983.

When the pixel 13, that is, the capacitive load 13 is driven by the drive circuit shown in FIG. is a positive low voltage (■) depending on whether the pixel 13 emits light or not. Or Ov is applied. The positive high voltage vsp is sufficiently higher than the light emission starting voltage Vt of the EL, and the positive low voltage Vsp is
o is a voltage sufficiently lower than the emission starting voltage v1, and lV
, IpV o I < l V□1.

In this state, when the pixel 13 connected to the output terminal 3 serving as the scanning side electrode terminal is caused to emit light, the data side electrode terminal 14 is biased to Ov, the PMOS transistor 71 in the buffer circuit 7 is turned on, and the NPN transistor 11 is turned on. The thyristor 8 is turned on by drawing a gate current from the anode gate of the thyristor 8. At this time, the PMOS transistor 72 in the buffer circuit 7
And the NPN transistor 1°, which is the sink side switch, is controlled to be in the off state.

Regarding the on-driving operation of the thyristor 8, a one-shot circuit is provided in the logic circuit 6 and the PMOS transistor 71 and the NPN transistor 1 are
By operating thyristor 1 in a pulse manner, thyristor 8
It is possible to effectively reduce the gate operating current of the drive circuit, thereby reducing the power consumption of the drive circuit.

When the thyristor 8 is turned on, a positive high voltage is applied to the output terminal 3 which is the scanning side electrode, and the terminal 14 which is the data side
Since the voltage is biased to 0■, the voltage applied to both ends of the pixel 13 becomes a voltage (2) larger than the EL light emission start voltage (2), so one pixel 13 emits light. Also, pixel 1
3 does not emit light, the data side electrode terminal 14 is biased to a positive low voltage vD. In this state, when a positive high voltage ■1 is applied to the output terminal 3, which is the scanning side electrode terminal, 1
The voltage across the pixel 13 is lvH□-VDI, which is smaller than the EL light emission start voltage v1, so the pixel 13 does not emit light. In this way, when a certain scan electrode is selected, the drive circuit shown in FIG.
It can be controlled by the voltage applied to the data side electrode.

The drive circuit outputs a positive high voltage VIIP to the output terminal 3 serving as the scanning side electrode terminal to charge one pixel 13 and control it to emit or not emit light, and then discharges it in preparation for the next drive. Therefore, the discharge of pixel 13 is
This is done by turning on the PMOS transistor 72 in the buffer circuit 7 and the NPN transistor 10, which is a sink side switch, and drawing current from the pixel 13 toward the terminal 2 biased to Ov.

The above operation completes the selection of one scan electrode terminal and the driving of the pixels on the scan electrode, and then.

The scan electrode adjacent to the scan electrode terminal selected so far is selected, and the above-described operation is repeated.

After such an operation is performed for all the scanning electrodes, the same scanning electrode is selected again, and the pixel is driven to emit light or not emit light. In this case, as mentioned above, EL
has a polarization effect, so in order to cause the pixel to emit light at the same level, it is necessary to apply a voltage whose polarity is inverted from the voltage polarity previously applied to the pixel. Therefore, in the drive circuit shown in FIG. 7, the terminal 2 is biased to the negative high voltage VIIN, the terminal 1 is biased to Ov, and the PMOS transistor 72 and the NPN transistor 10, which is the sink side switch, are turned on. Then, the thyristor 8, which is the source side switch, is turned off, and a negative high voltage V□ is applied to the output terminal 3, which is the scanning side electrode terminal. In this case, the negative high voltage V□ is 1vlltl<lv, I,
In addition, it is assumed that the following conditions are satisfied: I vHN l + I Vo 1>IV, l.

In the above-described state, the data side electrode terminal 14 is connected to the positive low voltage V.
If it is biased to D, the voltage across each pixel 13 will be 1v□I + lV o I,
Since the light emission starting voltage is equal to or higher than 71, the pixel 13 emits light. Furthermore, when the data side electrode terminal 14 is biased to ov, the voltage across the pixel 13 is IVNN
I, and the emission starting voltage is V.

, the pixel 13 does not emit light.

As described above, the drive circuit shown in FIG. 7 outputs a negative high voltage V
3 is charged and controlled to emit or not emit light, it will be discharged in the same way as last time, but this time, the NPN transistor 10, which is the switch on the sink side, is turned off.
This is done by turning on the thyristor 8, which is a source-side switch, and flowing a current toward the pixel 13, contrary to the previous time.

The above operation completes the selection of one scan electrode terminal and driving the pixels on the scan electrode in the opposite direction, and then the scan electrode adjacent to the scan electrode terminal that has been selected until now is selected. The above operation is then repeated. When such operations are completed for all scanning electrodes, the state returns to the previous initial state, and all the operations described above are repeated.

In the drive circuit shown in FIG. 7, the voltage applied to the low voltage power supply terminal 4 is a voltage necessary for the operation of the logic circuit 6 and the buffer circuit 7, and is always applied with reference to the potential of the terminal 2. Ru.

[Problems to be Solved by the Invention] The circuit according to the above-mentioned prior art has the thyristor 8 and the NP
The N transistors 10 and 11 must be constructed of high-voltage elements, and when this circuit is integrated into multiple channels, the three high-voltage elements are required for each channel. Generally, high-voltage elements require large element dimensions to ensure voltage resistance, and in circuit integration, the dimensions are larger than that of a chip.

It is desirable to reduce the number of high voltage elements as much as possible.

In the prior art shown in FIG. 7, although the NPN transistor 11 is used only to turn on the thyristor 8 and is not directly involved in driving the load, the NPN transistor 11
The N transistor 11 must be a high voltage element,
Therefore, there is a problem in that the chip area becomes large when integrated.

An object of the present invention is to provide a drive circuit that can solve the problems of the prior art, reduce the number of high voltage elements, and reduce the chip size during integration. An object of the present invention is to provide a display device using a drive circuit.

[Means for Solving the Problems] According to the present invention, the object is to provide, in the conventional circuit shown in FIG. 7, between the terminals 1 of the plurality of circuits and the external power supply connected thereto. A common switching element is provided,
This is achieved by having the NPN transistor 11 for driving the thyristor not only turn on the thyristor but also drive the capacitive load.

[Operation] When charging a capacitive load, which is a pixel, to a positive high voltage, with the common switching element turned on,
By turning on the NPN transistor, the thyristor can be turned on and the pixel can be charged.

Next, when discharging this pixel, the NPN transistor is turned on while the commonly provided switching element is turned off. At this time, the discharge current from the pixel is
Output terminal - diode - thyristor cathode 1 -
- the anode gate of the thyristor - flows in the path of the NPN transistor.

During this operation, since the switching element is off, no high positive voltage is applied to the anode of the thyristor and the collector of the NP-N transistor.

Furthermore, when charging a pixel to a negative high voltage, a current of charging can be passed through the above-described path during discharging while the switching element is turned off. Further, the negatively charged pixel can be discharged using the above-described charging path with the switching element turned on.

The drive circuit described above can turn on the thyristor and drive the pixel using a single NPN transistor, so it is possible to use a single NPN transistor to turn on the thyristor and drive the pixel.
- Can be constructed using only two transistors,
When this circuit is integrated, the above-mentioned switching elements can be used in common, so the chip area can be reduced.

[Example] Hereinafter, an example of a drive circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention. In FIG. 1, 16 is a switching element;
Other symbols are the same as in FIG. 7.

A first embodiment of the present invention shown in FIG. 1 includes a thyristor 8 whose anode is connected to a terminal 1 and whose cathode is connected to an output terminal 3; a switching element 16 connected between terminal 1 and power supply terminal 15; a corefter connected to the anode gate of thyristor 8; and an emitter connected to terminal 2 via resistor 12. and the base is the PMOS in the buffer circuit 7
The NPN transistor 11 is connected to the drain of the transistor 71.

In the above-described configuration, a logic circuit 6 for controlling the buffer circuit 7 is further provided as in the case of the prior art. The source of the PMOS transistor 71 in the buffer circuit 7 is connected to the low voltage power supply terminal 4, and the capacitive load 13 is connected between the output terminal 3 and the terminal 14.

When driving an EL panel using the driving circuit of the embodiment shown in FIG. corresponds to one pixel in the EL panel. The capacitive load 13 will also be referred to as one pixel 13 hereinafter.

The operation of driving an EL panel using the drive circuit shown in FIG. 1 will be described below.

First, one pixel 13 is charged to a positive high voltage Vnp, and the pixel 13
The operation when emitting light will be explained.

In this case, the terminal 14, that is, the data side electrode, is biased to Ov, the positive high voltage power supply VMP is connected to the power supply terminal 15, and the switching element 16 is turned on. In this state, when the PMOS transistor 71 in the buffer circuit 7 is turned on via the logic circuit 6 by the control signal applied to the input terminal 5, the NPN transistor 11
is turned on, thereby drawing out the gate drive current of the thyristor 8, and the thyristor 8 is turned on.

When the thyristor 8 is turned on, the pixel 13 is charged to the positive high voltage VHP connected to the power supply terminal 15 via the switching element 16, the thyristor 8, and the output terminal 3, and the pixel 13 emits light. When the NPN transistor 11 turns on the thyristor 8, the NPN transistor 11 is turned on only for a period sufficient to turn on the thyristor 8. This can be done by so-called pulse driving, and the power consumption due to the gate drive current of the thyristor 8 can be reduced.

Next, the discharge of the pixel 13 charged to a positive high voltage as described above will be explained.

In the conventional technique explained with reference to FIG. 7, an NPN transistor 10 is provided as a sink side switch.

This caused the pixel 13 to discharge, but in the first embodiment of the present invention shown in FIG.
The pixel 13 can be discharged using the N transistor 11. That is, in the embodiment shown in FIG.
When discharging the pixel 13, the switching element 16 is turned off, and the voltage applied to the terminal 15 is changed to the terminal 1.
Alternatively, the voltage is not applied to the collector of the N-PN transistor 11. In this state, NPN transistor 1
1 is turned on, the discharge current from the pixel 13 can flow through the path of the pixel 13 - output terminal 3 - diode 9 - cathode gate of thyristor 8 - anode gate of thyristor 8) - NPN transistor 11. . In the conventional circuit shown in FIG. 7, the terminal 1 and the collector of the NPN transistor 11 are biased to the high voltage 1.

It is not possible to discharge the pixel by the NPN transistor 11 as in the previous embodiment. In addition, in the operation of the embodiment described above, when the switching element 16 is turned off, the terminal 1
The voltage may be switched in the switching element 16 so that a certain voltage, for example, 0.times. is applied. In this case, in principle, the pixel 13 will be discharged to the voltage applied to the terminal 1.

Next, the operation when charging one pixel 13 to a negative high voltage V□ and causing it to emit light will be described.

In this case, by applying a negative high voltage VH8 to the terminal 2, turning off the switching element 16, and turning on the NPN transistor 11, a charging current flows through the same path as in the case of discharging one pixel 13. can be charged to a negative high voltage VHN.

In this negative charging operation, it is necessary to keep the terminal 1 in an open state by the switching element 16.

When discharging the pixel 13 charged to the negative high voltage VHN as described above, the switching element 16 is turned on, the power supply terminal 15 is biased to 0■, and the NPN transistor 11 is turned on, so that the thyristor 8 is turned on, and it becomes possible to flow a current of discharge toward the pixel 13 from the power supply terminal 15 side.

When integrating the drive circuit shown in FIG.
and NPN transistor 11. When the switching element 16 is made into a monolithic IC, it can be formed within the IC chip.

However, in a matrix panel such as an EL panel, the number of scanning lines is approximately 200 to 400, and it is not possible to integrate all the drive circuits for all scanning lines into one IC.
Since a plurality of ICs are required and the scanning lines are selected line-sequentially, it is reasonable to provide one switching element per matrix panel.

In one drive of the EL panel, for example, the voltage applied to the terminal 1 in the conventional technique shown in FIG. 7 needs to be switched depending on the drive mode of the pixel 13.

That is, when negative high voltage vHN is applied to terminal 2,
If the high positive voltage HP is kept applied to the terminal 1, the collector-emitter voltage of the NPN transistor 11 will be l V++ Nl + l Vupl toner'J.

If IvHsl and 1VHpl are approximately the same voltage, the NPN transistor 11 would need to have twice the withstand voltage.
It is necessary to switch the voltage applied to the terminal 1 according to the drive mode No. 3.

In the first embodiment of the present invention shown in FIG. 1, the external switching element for switching the power supply voltage of the terminal 1 as described above can be used as the switching element 16.
When integrating the circuit shown in FIG. 1, it is possible to use two high-voltage elements per channel, the thyristor 8 and the NPN transistor 11.

According to the first embodiment of the present invention described above, by providing the switching element 16, the NPN transistor 11
Accordingly, the thyristor 8 can be turned on, and one pixel 13 can be discharged and charged with a negative high voltage. Therefore, in the first embodiment of the present invention, when the circuit of the embodiment is integrated into a large number of channels, the switching element 16 is used in common, and the high withstand voltage elements for each channel are two, the thyristor 8 and the NPN transistor 11. Therefore, it is possible to improve the utilization efficiency of the high voltage element and reduce the chip size thereof.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention. In FIG. 2, 17 is a low voltage switching element, and other symbols are the same as in FIG. 1.

The second embodiment of the present invention is an NPN transistor 1
A resistor 12 connected between the emitter of 1 and terminal 2
A low voltage switching element 17 is provided in parallel with the
An NMOS transistor is used as the switching element 17, and a PNP transistor is used as the switching element 16.
This is an example using a transistor.

In the second embodiment of the present invention shown in FIG. 2, the sink current of the NPN transistor 11 can be switched and controlled by the low voltage switching element 17 according to the operation mode.

That is, in this embodiment, when the NPN transistor 11 operates to turn on the thyristor 8, the gate drive current to the thyristor 8 may be relatively small, so the low voltage switching element 17 described above is turned off and the resistor 1 is turned on.
2, the current of the NPN transistor 11, i.e.,
The gate drive current of the thyristor 8 is limited to suppress its power consumption, which is advantageous for integration. On the other hand, in this embodiment, N
When the pixel 13 is discharged or charged to a negative high voltage to emit light using the PN transistor 11, a relatively large current is required, so by turning on the low voltage switching element 17, the resistor 12 is switched to an apparently low impedance. Increase the current of NPN transistor 11.

According to the second embodiment of the present invention, it is possible to achieve the same effects as the above-described first embodiment of the present invention, and further reduce power consumption and improve load driving ability. .

FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention. In FIG. 3, 18.19 is an NPN transistor, 73.74 is a PMO3)-transistor, and other symbols are the same as in FIG. 1.

This third embodiment of the present invention is also an embodiment in which the current of the NPN transistor 11 is switched according to the operation mode, like the second embodiment described above.

In the third embodiment of the present invention shown in FIG. 3, the NPN transistor 11 is constructed by connecting NPNh transistors 18. It is connected to PMOS transistors 73 and 74 for current supply.

In this embodiment, when turning on the thyristor 8, PM
Only the OS transistor 74 is turned on and only the NPN transistor 19 is turned on to draw out the gate current of the thyristor 8, while the pixel 13 is connected to the NPN transistor 1.
1, the PMOS transistor 73 is turned on and the NPN transistor 18. '19 is operated as a Darlington-connected NPN transistor to ensure current drive capability.

This third embodiment of the present invention can produce the same effects as the aforementioned second embodiment of the present invention.

FIG. 4 is a circuit diagram showing the configuration of a fourth embodiment of the present invention. In FIG. 4, 20 is a low voltage switching element, and other symbols are the same as in FIG. 1.

The fourth embodiment of the present invention shown in FIG. 4 is similar to the second embodiment described above. Similarly to the third embodiment, the current of the NPN transistor 11 is switched according to the operation mode, and the NPN transistor 11 has a multi-emitter structure, and one emitter is connected to the terminal 2 via the resistor 12. and the other emitter is connected to the terminal 2 via the low voltage switching element 20.

In the fourth embodiment configured as described above, when the thyristor 8 is turned on, the low voltage switching element 20 is kept in the off state, the current of the NPN transistor 11 is limited by the resistor 12, and the pixel 13 is driven as an NPN transistor. 1
When driven by 1.

By turning on the low voltage switching element 20, N
A large current is caused to flow through the emitter of the PN transistor 11 to which the low voltage switching element 20 is connected, and the NP
This is intended to increase the drive current of the N transistor 11.

This embodiment is based on the second embodiment of the present invention described above. The same effect as the third embodiment is achieved.

FIG. 5 is a circuit diagram showing the configuration of a fifth embodiment of the present invention. In FIG. 5, 21 is a PNP transistor, and other symbols are the same as in FIG. 1.

A fifth embodiment of the present invention shown in FIG.
NP transistor is replaced with RI21, and P
The emitter of the NP transistor 21 is connected to the terminal 1, its base is connected to the collector of the NPN transistor 11, and the collector is connected to the output terminal 3. In the case of the embodiment using the thyristor 8, the low voltage diode 9 was required to secure a current path from the pixel 13 to the NPN transistor 11, but when using the PNP transistor 21 as in this embodiment, Since the collector-base junction of this PNP transistor 21 is in the forward direction, the low voltage diode 9 is unnecessary.

Also in the fifth embodiment of the present invention described above, the high breakdown voltage element upon integration is composed of two PNP transistors for each channel.
1 and NPN transistor 11, the same effect as the first embodiment of the present invention can be obtained.

FIG. 6 is a circuit diagram showing the configuration of a sixth embodiment of the present invention. In Figure 6, 22 is a low voltage diode, 23.2
4 is a switching element, and the other symbols are the same as in FIG. 1.

A sixth embodiment of the present invention shown in FIG.
Connect the anode to the node gate.

A low voltage diode 22 whose cathode is connected to the anode of the thyristor 8 is added, and the switching element 16 is
Commonly connect one end to terminal 1, and the other end to terminal 15.25
It is constructed by switching elements connected to each other.

In the first embodiment of the present invention described in FIG. Since a galvanic discharge current will flow, N
Care must be taken regarding the safe operating area (hereinafter referred to as ASO) of the PN transistor 11. Generally, N P N
In order to enlarge the ASO of the I-transistor 11, it is necessary to increase the element area, but this is disadvantageous for integration.

On the other hand, when driving the pixel 13, it is desirable that the current driving capability of the driving circuit is large.

A sixth embodiment of the present invention, shown in FIG.
3 can be performed via the switching element 16. That is, in FIG. 6, when the terminal 15 is now biased to a positive high voltage v, 4P and the switching element 23 and the thyristor 8 are turned on to charge the pixel 13 and then discharged, the switching element 23 is turned off. , by turning on the switching element 24 and biasing the terminal 25 to Ov, the pixel 13 - the diode 9 - the cathode gate of the thyristor 8 - the thyristor 8
A discharge current can be caused to flow through the path of the anode gate, the diode 22, the switching element 24, and the terminal 25.

Note that during this discharging operation, the NPN transistor 11 is
Control it in the off state.

Switching element 23 that constitutes switching element 16
．． As mentioned above, when integrating the drive circuit, 24 can be provided as a common element throughout the EL panel, and an external power transistor or the like can be used.
Securing internal SO work is relatively easy.

According to the sixth embodiment of the present invention described above, it is possible to achieve the same effects as the first embodiment of the present invention, and
It is also possible to protect the NP transistor 21 against ASO.

In the plurality of embodiments of the present invention described above, the case where the pixel 13 is charged to the negative high voltage vHN by the NPN transistor 11 is disclosed in Japanese Patent Application No. 62-321 already proposed.
As described in No. 560, when the EL panel is driven, the positive high voltage 1vI (compared to t'l, the negative high voltage IV□1
The value of is smaller, ゛Also.

Since one pixel 13 holds the voltage when the pixel 13 emits light, there is no problem with the ASO of the NPN transistor 11.

When the drive circuit according to the plurality of embodiments of the present invention described above is used to drive a thin film EL display device, it is used to drive the scanning side electrode, but the present invention can also be used to drive the data side electrode. It's ringing.

[Effects of the Invention] As explained above, according to the present invention, in a capacitive load drive circuit, the sink-side high-voltage switching element can both turn on the source-side high-voltage switching element and activate the load. This makes it possible to improve the utilization efficiency of high-voltage switching elements and reduce the number of high-voltage elements, making it possible to provide a drive circuit that can reduce chip size during integration. An efficient display device using a drive circuit can be provided.

[Brief explanation of the drawing]

1, 2, 3, 4, 5 and 6 are the first embodiment of the present invention. Second. Third. FIG. 7 is a circuit diagram showing the configuration of the fourth, fifth, and sixth embodiments, and FIG. 7 is a circuit diagram showing the configuration of the prior art. 6...Logic circuit, 7...Buffer circuit, 8...Thyristor, 9,22...
Diode, 10゜11.18.19...NP
N transistor, 13... Capacitive load, 16,1
7.20...Switching element, 21...
・・PNP transistor, 71~Figure 2 Figure 2 Figure 5 Figure 3 Figure 4 Figure 7

Claims (1)

[Claims] 1. In a drive circuit including a source-side switch that supplies current to a load and a sink-side switch that draws current from the load, the source-side switch is turned on by the sink-side switch. Features a drive circuit. 2. The drive circuit according to claim 1, wherein the source side switch is a thyristor. 3. The drive circuit according to claim 1, wherein the source side switch is a transistor. 4. Claim 1, 2 or 3, wherein the sink side switch is a transistor.
Drive circuit described in section. 5. The drive circuit according to claim 1, wherein the sink-side switch includes current switching means. 6. The drive circuit according to claim 5, wherein the current switching means is a switching element connected in parallel to a resistor connected in series with the sink side switch. 7. The drive circuit according to claim 6, wherein the switching element is a MOS transistor. 8. The drive circuit according to claim 1, 2 or 3, wherein the sink-side switch is a Darlington-connected transistor having individual current supply means. 9. The sink side switch is a transistor having a first emitter connected to a resistor and a second emitter connected to a switching element. The drive circuit according to item 3. 10. The drive circuit according to claim 9, wherein the switching element is a MOS transistor. 11. The drive circuit according to claim 1, wherein the sink side switch is driven by a MOS transistor. 12. In a drive circuit including a source-side switch that supplies current to a load and a sink-side switch that draws current from the load, a switching circuit is provided between a first main terminal of the source-side switch and a first power supply terminal. the sink side switch is connected between the first gate terminal and the second power supply terminal of the switching element constituting the source side switch, and the second main terminal of the source side switch is output. A drive circuit characterized by being connected to a terminal. 13. The switching element constituting the source side switch is a thyristor including a diode with an anode connected to the second main terminal and a cathode connected to the second gate terminal. Drive circuit described in section. 14. The switching element constituting the source side switch includes a first diode having a cathode connected to its first main terminal and an anode connected to its first gate terminal;
13. The disturbance circuit according to claim 12, wherein the disturbance circuit is a thyristor having an anode connected to the main terminal thereof and a second diode having a cathode connected to the second gate terminal. 15. A drive circuit comprising a source-side switch that supplies current to a load and a sink-side switch that draws current from the load, wherein a load discharge current flows through the source-side switch. 16. In a thin film EL display device comprising a scanning side electrode and a data side electrode arranged to intersect with each other and an EL layer provided between the two electrodes, the method according to the above-mentioned claim is used for driving the scanning side electrode. A thin film EL characterized by using the drive circuit according to one of the ranges 1 to 15.
Display device. 17. In a thin film EL display device comprising scanning side electrodes and data side electrodes arranged to intersect with each other, and an EL layer provided between the two electrodes, for driving the data side electrodes, Thin film E characterized by using the drive circuit described in one of the ranges 1 to 15.
L display device.