JP3080371B2 - Switch circuit and display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit for conducting or blocking an input signal by a semiconductor device, and is particularly suitable for controlling a high-voltage input signal by a low-voltage signal. The present invention relates to a switching circuit and a driving method thereof.

[Conventional technology]

Conventionally, analog switch circuits that conduct or cut off input signals with semiconductor elements are described in "How to use FETs (1.
983) Pages 110 to 114 (published by CQ Publishing Co., Ltd.)
Are discussed in Here, a small signal input is given to the source of the MOS transistor, an output signal is taken from the drain, and the body (substrate) is set so that the pn junction is not forward-biased to the source or drain under any conditions. In addition, a method of controlling conduction and interruption of a signal by a gate voltage is described.

[Problems to be solved by the invention]

The above prior art does not take into consideration the conduction or interruption of the high voltage signal, and does not take into account the active use of the parasitic diode between the drain and the body.

A first object of the present invention is to provide a simple switch circuit that positively utilizes a parasitic diode existing between a drain and a body of a MOS transistor.

A second object of the present invention is to provide a high-voltage signal switch circuit for controlling conduction and interruption of a high-voltage signal by a low-voltage signal.

A third object of the present invention is to provide a capacitive load driving device for driving a capacitive load with low power consumption.

[Means for solving the problem]

The first object is achieved by connecting a source and a body of a MOS transistor, using this as a signal input terminal, a drain as a signal output terminal, and a gate as a signal control terminal.

The second object is to provide a gate of the MOS transistor.
A protection diode is connected between the sources, and when a signal pulse is input to the source, the voltage transition at the beginning of the pulse causes a reverse bias voltage between the gate and the source at both ends of the diode to generate a bias voltage. This is achieved by providing means for connecting the first active element to the gate to turn on the MOS transistor and forcibly turn off the MOS transistor.

The third object is to provide a pulse generator as disclosed in
Using the power recovery circuit described in No. 2997, the pulse from this pulse generator was used as the input to the switch circuit,
This is achieved by connecting a capacitive load to the output terminal.

[Action]

A switch circuit in which the source and the body of a MOS transistor are connected, this is used as a signal input terminal, the drain is used as an output terminal, and the gate is used as a signal control terminal is used when an n-channel MOS transistor is used as a switch element. When the potential is high, the output also becomes high. When a p-channel MOS transistor is used as a switch element, the output also becomes low when the input is low, making it impossible to control opening and closing by the gate. However, in the former case, when used as a switch for a negative pulse for suppressing a pulse in a negative direction with respect to an input pulse, no malfunction occurs. In the latter case, when used as a positive pulse switch for suppressing a pulse in the positive direction with respect to an input pulse, no malfunction occurs.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
M ₁ is an n-channel MOS transistor having a source and a body connected, and applies an input signal voltage V _IN to the source side and extracts an output signal voltage V _OUT from the drain side. M ₂ is n channel
In MOS transistors, it is used as a current inhalation device when setting the force off M _1. D ₁ is a diode used as a gate protection M _1, by using this, the voltage amplitude of V _IN and V _OUT can be set higher than the gate breakdown voltage of M _1. D ₁ is preferably the breakdown voltage is the Zener diode of about 5 to 30 V. R ₁ is
The resistance used to reduce the current value of M _2, when the power consumption by the current flowing through the M ₂ is not a problem is unnecessary.

FIG. 2 is a time chart showing a method of driving the circuit of FIG. The cathode and the drain between the drain of M ₁ and body, the parasitic diode of the body as the anode is present, given an input signal voltage V _IN of the amplitude V _DH, V
_IN is in a high voltage state, the output signal voltage V _OUT does not depend on the state of the control signal voltage V _C is also a high voltage state. When V _IN falls, if V _C is in a low voltage state (M ₂ is off), the voltage of V _X is about to be maintained, M ₁ is on, and V _OUT
Also falls. However, when V _IN falls and V _C is in a high voltage state (M ₂ is on), M ₁ is forcibly turned off, so that V _OUT holds almost the high voltage state. Call V _C
It is possible to control whether V _IN and V _OUT are made conductive or cut off according to the value of V _IN, and it functions as a switch circuit that suppresses a negative-going pulse for an input pulse entering V _IN .

FIG. 3 is also a time chart showing a method of driving the circuit of FIG. In this driving method, V _{C is set} to a high voltage state in synchronization with the fall of V _IN only during the period when it is not _desired to fall V _OUT . Thus, controlled by a signal voltage V _C decreases the reactive current which current flows in M _2, can reduce the power consumption of the circuit.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, when the first to add capacity C ₁ between the V _X portion and the high power supply voltage V _H of the circuit of embodiment M ₂ falls is V _IN in the off state, M ₁ is turned on To make it easier. In the present embodiment has at a capacitance C ₁ between the V _X portion and the high power supply voltage, be placed between such V _X portion and the ground or V _C unit the same effect is obtained.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In the present embodiment, the diode D ₁ of the circuit of the first embodiment is used.
We are adding a diode D ₂ in the reverse direction in series with the. Therefore, it is possible to V _C even when a driving method shown in Figure 2 is eliminated reactive current flowing through connexion to M ₂ when the high voltage state.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. In this embodiment, the diode D ₁ of the circuit of the first embodiment is used.
And by the resistance R ₂ in place of. For example, when using polysicon resistance as R _2, as compared to the diode, it is possible to reduce the parasitic capacitance in a small area. However, the value of the resistor R ₂ is too large, useless as a gate protection M _1, is too small, M ₁ when the fall of the V _IN
Therefore, care must be taken in setting the resistance value, since it will not be possible to turn on the resistor.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention. When the falls V _IN in the first embodiment and the like, although about 10% of the voltage drop of the voltage amplitude of the even V _IN an attempt to keep the V _OUT to the high voltage state has been made in V _OUT, in this embodiment, In order to prevent this voltage drop and maintain a high voltage state, two p-channel MOS transistors M ₃ and M ₄ are connected in a current mirror, and the current of the transistor M ₃ is controlled by an n-channel MOS transistor M ₅ . The driving method of this circuit can be the same as that shown in FIGS. 2 and 3 by connecting V _C1 and V _{C2 and} setting the control signal voltage V _C.

FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention. In this embodiment, as means for setting the supply to the on-state current to the gate of M _1, and p channel MOS transistor M _6, M ₇ connected current mirror, n channel for driving
MOS transistors are used M _8. In the present embodiment, V _OUT can be raised while M ₁ is on, so that the parasitic diode between the drain and the body of M ₁ can be driven without forward bias. Due to the accumulation of minority carriers
The switching-speed decrease of M ₁ can be prevented. Furthermore, since the V _IN by setting a higher high power supply voltage V _H from the highest voltage V _DH of V _IN can be set to the ON state of M ₁ even at a high potential state V
A small signal from _IN can be sent to V _OUT over a wide voltage range. Note that the p-channel MOS transistors M ₉ and n
Channel MOS transistor M ₁₀ is an inverter configuration and summer, and connect the V _C1 and V _C3, if the control signal voltage V _C, it is possible to use the same driving method as the second figure and Figure 3.

_VL is a signal system power supply voltage.

FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention. The present embodiment is configured to have the circuit functions shown in FIGS. 7 and 8. The high power supply voltages V _H1 and V _H2 may be set to the same potential.However, by setting V _H2 to about 5 to 20 V higher than V _H1 , M ₁ may be turned on when V _IN is at a high potential. It is possible. When V _C1 , V _C2, and V _C3 are connected and this is used as the V _C terminal, the driving method shown in FIGS. 2 and 3 can be used.

FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention. In this embodiment, the input signal voltage V _IH and the output signal voltage V _OUT
This is also a switch circuit effective when used at a level lower than the gate breakdown voltage.

FIG. 11 is a truth table of the circuit of FIG. When the control signal voltages V _CON and V _IN are both in the low voltage state, V _OUT retains the previous state of V _OUT .

FIG. 12 is a circuit diagram showing a ninth embodiment of the present invention. This embodiment is also a switch circuit effective when V _IN and V _OUT are used at a level lower than the gate withstand voltage.

FIG. 13 is a truth table of the circuit of FIG. V _CON and V
_IH if are both low voltage state, because the p-channel MOS transistor M ₃ is turned on, V _OUT becomes a high voltage state.

FIG. 14 is a circuit diagram showing a tenth embodiment of the present invention. In the present embodiment, replacing the n-channel MOS transistors M ₁ used in FIG. 1 as switch elements in the npn transistor Q _1, a diode D _Q1, n-channel MOS transistor M ₂
Which is a switch circuit was replaced with npn transistor Q _2. Thus the circuit described in Embodiment far, the MOS transistor M _1, a circuit having a same function cowpea to be replaced by a bipolar transistor connected in parallel to the diode is feasible.

FIG. 15 is a circuit diagram showing an eleventh embodiment of the present invention. The embodiments described so far have shown a switch circuit that is effective in suppressing a pulse in the negative direction with respect to the reference voltage. It is possible to realize a switch circuit that is effective in suppressing a pulse. In the present embodiment realizes a switching circuit for the positive pulse by replacing the n-channel MOS transistors used in the embodiment of Figure 1 respectively to M ₁₁ and M ₁₂ of the p channel MOS transistor.

FIG. 16 is a circuit block diagram showing a twelfth embodiment of the present invention. In this embodiment, it is configured to determine whether or not to send each pulse output from the pulse generator to two or more loads by opening and closing the switch circuit SW according to the present invention. The switching of the switch is performed based on control signal voltages V _C ( ₁ ), V _C ( ₂ ),... V _C ( _N ) sent from the drive circuit. The drive circuit has a function of transferring the data input from the data input terminal in the shift register by a clock signal, performing serial-parallel conversion, synchronizing by a latch signal, and simultaneously transmitting the control signal voltage to each switch circuit. I have.

In FIG. 16, when the load is capacitive, the pulse generation circuit can be realized by a power recovery circuit (Japanese Patent Laid-Open No. 61-132997). In this case, the power transmitted from the pulse generator to the load is returned from the load to the pulse generator again, so that a capacitive load driving device with low power consumption can be realized.

FIG. 17 is a circuit block diagram showing a thirteenth embodiment of the present invention. This embodiment describes a method of driving a matrix display device using the switch circuit of the present invention as an example in Japanese Patent Application No.
This shows an example in which the invention is applied to driving of a display device described in Japanese Patent No. 113686.

As shown in FIG. 17, the discharge cell is composed of three electrodes: an anode, a cathode, and an auxiliary anode. The discharge between the anode and the cathode is a display discharge, while the discharge between the auxiliary anode and the cathode is The auxiliary discharge is not observed from the outside. Cathode resistance R _K
Is provided to prevent simultaneous display discharge and auxiliary discharge. Assuming the anode voltage V _A , the cathode voltage V _K , and the auxiliary anode voltage V _SA , the following procedure is required to perform display discharge. That is, (1) Auxiliary discharge is started with _{VSA set} to high potential and _{VK set} to low potential.

(2) _{VSA is set} to a low potential, _{VK is set} to a low potential, and _{VA is set} to a high potential, auxiliary discharge is stopped, and display discharge is started.

If, in step (2), if you leave V _SA is at a high potential, V
_{Even when K} has a low potential and _VA has a high potential, the display discharge does not start because the auxiliary discharge does not stop.

Utilizing the characteristics of the above discharge cells, for running signals,
By using the positive pulse V _A and the negative pulse V _K and using the negative pulse V _SA for the image signal, a display discharge can be performed on any discharge cell on the display matrix. In the case of this embodiment, the power consumption of the anode drive circuit and the auxiliary anode drive circuit can be reduced by using the pulse generator as the power recovery circuit, as compared with the related art. As a switch circuit for the anode drive circuit, a drive circuit (A) having a built-in switch circuit for a positive pulse as shown in FIG. 15 is used. As a switch circuit for the auxiliary anode drive circuit, a switch circuit shown in FIG. Using a drive circuit (B) incorporating a switch circuit for negative pulses as described above,
A display device capable of driving with low power consumption can be realized by using a conventional push-pull type driving circuit (C) for driving the cathode. Note that the driving method described in the present embodiment is a general plasma display, EL (electroluminescence).
The present invention is applicable to a capacitive load driving device such as a display, a fluorescent display, and a piezoelectric element.

〔The invention's effect〕

According to the present invention, a switch circuit capable of handling a high-voltage signal with a simple configuration can be provided. In particular, when a capacitive load is driven, it can be used together with a power recovery circuit to reduce power consumption compared to a normal driving method using a complementary circuit. There is an effect that power can be reduced.

[Brief description of the drawings]

FIG. 1 is a switch circuit diagram of a first embodiment of the present invention, and FIG.
FIGS. 3 and 4 are time charts showing a driving method of the switch circuit of the present invention, FIGS. 4 to 10 are switch circuit diagrams of another embodiment of the present invention, and FIG. 11 is a switch circuit of FIG. FIG. 12 is a switch circuit diagram of still another embodiment of the present invention, FIG. 13 is a truth table of the switch circuit of FIG. 12,
14 and 15 are switch circuit diagrams of still another embodiment of the present invention, FIG. 16 is a block diagram of a switch circuit of still another embodiment of the present invention, and FIG. 17 is an embodiment of the present invention. It is a block diagram of a display apparatus. M ₁ , M ₂ , M ₅ , M ₈ , M ₁₀ ... N-channel MOS transistors, M ₃ , M
_{4, M 6, M 7,} M 9, M 11, M 12 ...... p -channel MOS transistor, Q
_1, Q ₂ ...... npn _{transistors, D 1, D 2, D} 11, D Q1 ...... _{diodes, R 1, R 2, R} 11 ...... resistors, C ₁ ...... Kiyapashita, V _IN ...... input signal voltage, V _OUT …… Output signal voltage, V _C , V _C1 , V _C2 , V _C3 , V
_CON …… Control signal voltage, V _H , V _H1 , V _H2 …… High power supply voltage, V _DD
…… Power supply voltage, V _L …… Signal power supply voltage.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeo Mikoshiba 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Inside the Central Research Laboratory (72) Inventor Masayo Edo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-157197 (JP, A) JP-A-49-18428 (JP, A) JP-A-52-6412 (JP, A) JP-A-61-132997 (JP, A) JP-A-62-186530 (JP, U) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H03K 17/687 H01L 29/78

Claims (3)

(57) [Claims] 1. A display device for displaying an image by driving a display unit with a driving unit, wherein the driving unit has a switch circuit unit for passing or blocking a pulse signal from a pulse generation unit, and the switch circuit unit. A first MOSFET that drives a display unit using a source as an input unit of the pulse signal and a drain as an output terminal
A diode connected between the gate and the source of the first MOSFET, and a second MOSFET connected to an output terminal to the gate of the first MOSFET and controlling the first MOSFET; When the first MOSFET is turned on, an on operation is performed with a reverse bias voltage generated in the diode due to a voltage transition at the beginning of a pulse of the pulse signal. When the first MOSFET is turned off, The above second MOSFET
Is turned on in synchronization with the voltage transition period at the beginning of the pulse of the pulse signal, and is turned off by following the source potential of the first MOSFET and transitioning the gate voltage of the first MOSFET. A display device characterized by being performed. 2. The display device according to claim 1, wherein the display section is constituted by a panel having a capacitive electrode, and the pulse generating section of the driving means is constituted by a power recovery circuit. 3. A first MOSFET for driving a display section using a source as an input section of a pulse signal and a drain as an output terminal;
A diode connected between the gate and the source of the first MOSFET, and a second MOSFET having an output terminal connected to the gate of the first MOSFET and controlling the first MOSFET;
When the first MOSFET is turned on, an on operation is performed with a reverse bias voltage generated in the diode due to a voltage transition at the beginning of a pulse of the pulse signal, and the first MOSFET is turned on.
When the MOSFET is turned off, the second MOSFET is turned on in synchronization with the voltage transition period at the beginning of the pulse of the pulse signal, and is followed by the source potential of the first MOSFET. A switch circuit configured to perform an off operation by changing a gate voltage.