JP3537061B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a power MOSFET as a source follower in an output stage.
In particular, the present invention relates to a semiconductor device suitable for a high-side switch that drives an inductive load at high speed.

[0002]

2. Description of the Related Art A circuit disclosed in U.S. Pat. No. 4,928,053 is known as a circuit for a high-side switch of this kind. FIG. 1 shows a configuration of a main part of this conventional high-side switch circuit (source follower circuit).
1 is shown. In FIG. 11, reference numeral 70 denotes a power MO.
The power MOSFET 70 has a drain connected to the power supply terminal V _DD and a source connected to the output terminal OU.
It is connected to the inductive load 71 via T. Power M
A power MOS is connected between the gate and the source of the OSFET 70.
N-channel MOSFET 7 for cutting off FET 70
The drain and source of the N-channel MOSFET 72 are connected to each other, and the gate of the N-channel MOSFET 72 is connected to the circuit ground. The drain and gate of the P-channel MOSFET 75 are connected to the gate of the power MOSFET 70 and the circuit ground, respectively. A power MO is connected between the power supply terminal V _DD and the gate of the power MOSFET 70.
A series circuit of a clamp diode 74 for determining the minimum value of the voltage at the output terminal OUT when the SFET 70 is cut off and a diode 73 for blocking current by a reverse voltage is connected.

[0003] The high-side switch circuit thus configured operates as follows. P-channel MOSFET
When the source potential V _S of the source 75 is changed from a low potential to a high potential, the P-channel MOSFET 75 is turned on and the power M
The gate of the OSFET 70 is driven and the power MOSFET is
T70 is turned on, the power MOSFET from the power supply terminal V _DD
A current is supplied to the inductive load 71 via the drain / source 70.

[0004] On the other hand, to the potential V _S of the source of the P-channel MOSFET75 from a high potential to a low potential, the P-channel M
By making the parasitic diode (shown by a broken line) built in the OSFET 75 forward bias, the power MOSFET
The charge is extracted from the gate of T70 and the power MOSF
The ET 70 is turned off. When the power MOSFET 70 is cut off, a back electromotive voltage is generated in the inductive load 71, the source (output terminal OUT) of the power MOSFET 70 drops below the ground potential, and after the source of the power MOSFET 70 becomes a negative voltage, the N channel MOSFET7
By turning on 2, the power MOSFET 70 is kept shut off. Thereafter, when a negative output voltage value determined by the clamp diode 74 (hereinafter, referred to as a negative output maintaining voltage) is reached, the power MOSFET 70 is turned on and the output voltage stops decreasing. Thus, the energy stored in the inductive load 71 continues to be released until the load current is cut off. Here, in order to cut off the current supplied to the inductive load 71 at high speed, it is necessary to lower the output voltage below the ground voltage as much as possible.

[0005]

However, according to the above-described conventional circuit configuration, the lower limit of the output voltage is limited by the withstand voltage between the gate and the source of the N-channel MOSFET 72 (generally, about 20 V). Furthermore, when a battery is used as a power supply, there is a power supply voltage fluctuation (about 5 V) depending on the charge level of the battery. Therefore, it is necessary to allow for this margin in the conventional circuit configuration, and the negative output maintaining voltage is limited to about -15 V. Met. For this reason, there has been a problem that it is difficult to increase the breaking speed of the inductive load.

In the conventional circuit configuration, the P channel M
Since the gate of the OSFET 75 is connected to the ground and the drain is connected to the gate of the power MOSFET, a voltage (battery voltage +8 V) applied between the gate of the power MOSFET and the ground is applied to the P-channel MOSF.
It must be lower than the gate-source breakdown voltage of ET75. For this reason, there is a problem that the battery cannot be used when a battery having a high voltage such as 24 V is used.

Furthermore, in the conventional high-side switch circuit, no countermeasure has been taken against the case where an overcurrent flows in the control circuit for driving the power MOSFET when the battery is erroneously reversely connected.

An object of the present invention is to provide a semiconductor device for a high-side switch that can cut off an inductive load at high speed. Another object of the present invention is to provide a semiconductor device for a high-side switch that can use a battery having a high voltage of 24 V or more. Still another object of the present invention is to provide a semiconductor device for a high-side switch that does not break even when a battery is reversely connected by mistake.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention has a drain connected to a power supply terminal 31 and a source connected to an output terminal 33, as shown in FIG. Power MOSFET 1,
A first MOSFET, MOSFET2, which is arranged between the gate of the power MOSFET1 and the control circuit ground, that is, the ground line 34, to turn off the power MOSFET1 based on the voltage of the input terminal 32, a gate of the power MOSFET1, and the output terminal 33; And a power MO based on the voltage of the input terminal 32.
The second MOSFET that turns off SFET1, namely MO
SFET3 and a power MOSFET connected to the gate of the power MOSFET 1 and based on the voltage of the input terminal 32.
Gate charging circuit for turning on ET1, ie, boosting circuit 19
And at least the following.

In the semiconductor device, the power MO
A diode for blocking current flowing between the gate of the SFET and the control circuit ground through a parasitic diode existing between the drain and source of the first MOSFET, that is, a diode 8 as shown in FIG. It is preferable to arrange the connection.

A third MOSFET for turning on the second MOSFET, that is, a MOS transistor as shown in FIG.
FET 4 and a resistor 1 connected between the gate and source of the MOSFET 3 for turning off the MOSFET 3
7 is preferably provided.

A third MOSFET for turning on the second MOSFET, and a fourth MOSFET connected between the gate and the source of the second MOSFET for turning off the second MOSFET, As shown in FIG. 4, a MOSFET 23 may be provided instead of the resistor 17.

Further, a constant voltage power supply for obtaining a predetermined constant voltage from the power supply voltage, for example, a voltage regulator 2 as shown in FIG.
0, the voltage regulator 20 and the MOSFET
Between the MOSFET 4 and the MOSF
A series circuit with the diode 9 that blocks a current flowing through a parasitic diode existing between the drain and the source of the ET 4 can be provided.

Further, a clamping diode, for example, as shown in FIG. 1 or 4, a clamping diode 13 and / or 14 is further provided between the gate of the power MOSFET and a power supply terminal and / or a constant voltage power supply. It is preferable to provide them.

Further, a first diode and a fifth M connected between the gate of the power MOSFET and a power supply terminal.
A series circuit of an OSFET, for example, a series circuit of a diode 12 and a MOSFET 6 is provided as shown in FIG.
A resistor 18 is provided between the gate and the source of the FET 6, and the MOSFET is connected to the gate of the power MOSFET 1.
A second clamping diode, that is, a diode 13 is provided between the power supply terminal 31 and the power supply terminal 31 via the gate of T6, and a constant voltage power supply, that is, a voltage regulator 20 that obtains a predetermined constant voltage from the power supply voltage applied to the power supply terminal 31 From the gate of the power MOSFET 1 to the MOS
The voltage regulator 20 via the gate of the FET 6
May be provided with a third clamping diode, that is, a diode 14.

In this case, instead of the resistor provided between the gate and the source of the fifth MOSFET, that is, the resistor 18, the sixth MOSFET having the drain and the gate diode-connected is used.
OSFET, a MOSFET as shown in FIG.
28 may be provided between the gate and the source of the MOSFET 6.

A seventh MOSFET having a gate connected to an output terminal between the gate of the power MOSFET and the first MOSFET, that is, a MOSFET 5 may be further provided as shown in FIG.

Furthermore, the drain is connected to the ground terminal,
It is preferable to connect an eighth MOSFET in which a source and a body are connected to the control circuit ground and a gate is connected to the power supply terminal or a portion having a voltage of the same polarity as the power supply terminal, that is, a MOSFET 7 in FIG. It is.

Further, in the semiconductor device according to the present invention, a control circuit for controlling a vertical power MOSFET 1 and a gate of the power MOSFET 1 on the same semiconductor substrate of the first conductivity type, for example, as shown in FIG. Wherein the power MOSFE
The region of T1 includes, in order from the substrate 101 side, a first conductivity type, that is, an N-type first semiconductor layer, and a first conductivity type second semiconductor layer, that is, an N-type epitaxial layer 105a having a lower concentration than the first semiconductor layer. And a third semiconductor layer of a first conductivity type having a higher concentration than the second semiconductor layer reaching from the surface to the first semiconductor layer, that is, a high-concentration N-type semiconductor region 107a at a peripheral portion of the power MOSFET region, The control circuit region includes, in order from the substrate side 101, a fourth semiconductor layer of the second conductivity type, that is, P-type epitaxial layers 103 a and 103.
b and the second semiconductor layers 105b to 105d of the first conductivity type
In order to form the plurality of island regions 105b to 105d by separating the second semiconductor layer into islands,
In a semiconductor device having a fifth semiconductor layer of the second conductivity type having a higher concentration than the P-type epitaxial layer reaching the P-type epitaxial layer from the surface, that is, the high-concentration P-type diffusion layers 108a and 108b, at least one of the island regions is formed. In order to separate from the other island regions, the sixth semiconductor layer of the first conductivity type having a higher concentration than the N-type epitaxial layer reaching the semiconductor substrate 101 from the surface, that is, in the case of FIG.
High concentration N-type semiconductor region 107a and high concentration N-type buried layer 1
It is characterized in that a semiconductor layer composed of 02a and 104a is provided.

In this case, a seventh semiconductor layer of the first conductivity type having a higher concentration than the second semiconductor layer, that is, a high concentration N-type buried layer as shown in FIG. 104b to 104d may be provided.

Further, the first semiconductor layer is a layer of an impurity of a first conductivity type provided on the semiconductor substrate before the formation of the fourth semiconductor layer, that is, as shown in FIG.
It is preferable to use a mold buried layer 102a and a high-concentration N-type buried layer 104a.

Further, the sixth semiconductor layer is formed of the raised layer, that is, the high-concentration N-type buried layer 1 as shown in FIG.
02a, a high-concentration N-type buried layer 104a, and a high-concentration N-type semiconductor region 107a.

A sixth semiconductor layer in the control circuit area;
That is, as shown in FIG.
a, 104a and the P-type epitaxial layer 103a and the high-concentration P-type diffusion layer 108a in at least one island region separated by the high-concentration N-type region 107a.
The P-type epitaxial layer 10 of another at least one island region electrically connected to the source potential of the power MOSFET 1 formed in the ET region and separated by the sixth semiconductor layer
It is preferable that 3b and the high-concentration P-type diffusion layer 108b be electrically connected to the ground of the control circuit.

Further, at least one other island-like region separated by the sixth semiconductor layer, wherein the fourth semiconductor layer and the fifth semiconductor layer are connected to the ground of a control circuit, The drain is electrically connected to the ground terminal to which the external power supply is connected, that is, the ground terminal 30 in FIG. 8, and the source and the body are the ground of the control circuit, that is, the ground line 34 in FIG. Speaking of the island region of FIG. 10, the P-type epitaxial layer 103b and the high-concentration P-type diffusion layer 108b that are connected to the ground of the control circuit are electrically connected to each other, and the gate is a power supply terminal to which an external power supply is connected. In FIG. 8, the power supply terminal 3
It is preferable to provide a MOSFET 7 connected to the power supply terminal 1 or a portion having a voltage of the same polarity as the power supply terminal.

[0025]

According to the semiconductor device of the present invention, the first MOSFET disposed between the gate of the power MOSFET driving the inductive load and the control circuit ground has a gate voltage of the power MOSFET higher than that of the ground terminal. Performs a power MOSFET shut-off operation at a high voltage, and the power M
A second terminal disposed between the gate of the OSFET and the output terminal;
The power MOSFET is turned off after the power MOSFET is turned off by the first MOSFET and the gate voltage of the power MOSFET becomes close to the power supply voltage.
Even when the ET is shut off and the output terminal is at a negative voltage lower than the voltage of the ground terminal, the power MOSFET is shut off, and the gate charging circuit that turns on the power MOSFET boosts the input voltage to the power supply voltage or higher. Power MO
Drive the gate of the SFET.

A diode provided between the gate of the power MOSFET and the control circuit ground to block a current flowing through a parasitic diode existing between the drain and the source of the first MOSFET. The gate voltage of the gate line becomes equal to or lower than the ground voltage, that is, a negative voltage. Here, the power MOSF
The first MOSF limits the upper limit of the gate voltage of ET.
Although the withstand voltage between the drain and the source of the ET is used, when a vertical MOSFET having a high withstand voltage is used, a withstand voltage of 60 V or more can be easily obtained, so that a battery of 24 V or more can be used.

The second MOSFET is turned on by turning on the third MOSFET, the second MOSFET is turned off by turning off the third MOSFET, and the second MOSFET is turned on.
The second M is connected by a resistor connected between the gate and the source of T.
The gate charge when the OSFET is turned off is discharged. As a result, the gate voltage of the second MOSFET is lowered below the ground voltage, so that the absolute value of the negative output sustaining voltage can be a large value that is not limited by the gate-source breakdown voltage of the second MOSFET. Therefore, the breaking speed of the inductive load can be increased. Here, the second MOS
In place of the above resistor when the FET is cut off, a fourth MO
An SFET may be used connected between the gate and the source of the second MOSFET.

Further, the constant voltage power supply obtains a predetermined constant voltage from the power supply voltage, and a diode provided between the constant voltage power supply and the gate of the second MOSFET is a third MOSFET.
Current flowing through a parasitic diode existing between the drain and the source of the transistor.

Further, the clamping diode provided between the gate of the power MOSFET and the power supply terminal determines the negative output sustaining voltage, and when the battery voltage increases beyond the standard, a high voltage is applied between the drain and the source of the power MOSFET. Prevents voltage from being applied.

The clamping diode provided between the gate of the power MOSFET and the constant voltage power supply determines the negative output sustaining voltage. However, by connecting to the constant voltage power supply, the voltage of the battery connected to the power supply terminal is reduced. It is possible to prevent a change in the cutoff speed of the inductive load due to the change.

Further, a first diode and a fifth M connected between a gate of the power MOSFET and a power supply terminal are provided.
The first diode in the series circuit of OSFETs allows the gate potential to be higher than the power supply voltage by the gate charging or boosting circuit, and the fifth MOSFET
Supplies a current for maintaining a negative output sustaining voltage. When the output terminal voltage is higher than the negative output sustain voltage, the resistance provided between the gate and the source of the fifth MOSFET becomes the fifth MO.
It operates to turn off the SFET. The second clamping diode determines the negative output sustaining voltage as well as the clamping diode provided between the gate of the power MOSFET and the power supply terminal. To prevent a high voltage from being applied between the drain and the source of the semiconductor device. The third clamping diode determines the negative output sustain voltage in the same manner as the clamping diode provided between the gate of the power MOSFET and the constant voltage power supply. To prevent a change in the inductive load cutoff speed caused by a voltage change of a battery connected to the battery. Further, since the fifth MOSFET supplies the gate current of the power MOSFET for maintaining the negative output sustain voltage, the element size of the second and third clamping diodes can be reduced.

Further, the gate of the fifth MOSFET
The sixth of the diode connection provided in place of the resistance between the sources
Since the MOSFET forms a current mirror with the fifth MOSFET, the element size of the second and third clamping diodes can be reduced.

Further, since a seventh MOSFET is provided between the gate of the power MOSFET and the first MOSFET, the first MOSFET is a seventh MOSFET.
Since the shut-off operation of the power MOSFET is terminated quickly by the threshold voltage of the FET, the turn-off becomes soft and low-noise switching can be performed.

Further, the drain is connected to the ground terminal,
An eighth MOSFET in which a source and a body are connected to the control circuit ground and a gate is connected to the power supply terminal or a portion having a voltage having the same polarity as the power supply terminal, a battery normally operates between the power supply terminal and the ground terminal. When it is connected, it turns on and connects the control circuit ground and the ground terminal, and when the battery is connected in reverse, it turns off and disconnects the control circuit ground and the ground terminal,
A current flowing through a parasitic diode existing between the control circuit ground and the power supply terminal is blocked.

Further, in the semiconductor device according to the present invention, the power MOSFET region includes, in order from the substrate 101 side, a first conductive type first semiconductor layer and a first conductive type first semiconductor layer having a lower concentration than the first semiconductor layer. With two semiconductor layers, the power MO
The drain terminal of the SFET can be taken out from the substrate side, and the high-concentration first conductivity type third semiconductor layer reaching from the surface to the first semiconductor layer at the periphery of the power MOSFET region is controlled on the same semiconductor substrate. It functions as a stopper for a leak current between the second conductivity type semiconductor layer in the circuit region, the body of the power MOSFET, and the fourth semiconductor layer.
The plurality of island-shaped regions of the first conductive type first semiconductor layer surrounded by the second conductive type fourth semiconductor layer and the fifth semiconductor layer in the control circuit region serve as control circuit element forming portions, respectively. The sixth semiconductor layer of the first conductivity type, which reaches from the semiconductor substrate to the semiconductor substrate, allows each of the island regions to be further electrically isolated.

The high-concentration first-conductivity-type seventh semiconductor layer provided on the surface of the required portion of the fourth semiconductor layer functions as a low-resistance buried layer of the control circuit element, so that the element characteristics are improved.

In addition, the first semiconductor layer is composed of a layer of an impurity of the first conductivity type provided on the semiconductor substrate before the formation of the fourth semiconductor layer, and the seventh semiconductor layer. The fourth semiconductor layer formed in the region can be easily penetrated by the layer of the first conductivity type, and conduction between the second semiconductor layer and the substrate can be obtained.

Further, the fourth and fifth semiconductor layers of at least one island region separated by the sixth semiconductor layer of the control circuit region are electrically connected to the source potential of the power MOSFET formed in the power MOSFET region. By connecting the fourth and fifth semiconductor layers of at least one other island region separated by the sixth semiconductor layer to the ground of the control circuit, the former island region becomes negative. It is possible to change to a potential, and it can be suitably used as a pull-down element whose potential changes together with the source of the power MOSFET. The absolute value of the negative output sustaining voltage can be increased and the inductive load can be cut off at high speed.

Further, at least one island region separated by the sixth semiconductor layer in the control circuit region, wherein the fourth semiconductor layer and the fifth semiconductor layer are electrically connected to the ground of the control circuit. By providing a MOSFET in which the drain is connected to the ground terminal, the source and the body are connected to the ground of the control circuit, and the gate is connected to the power supply terminal, the MOSFET is turned off when the battery is reversely connected. , A battery reverse connection protection operation that is turned on when the connection is normally made can be performed.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. <Embodiment 1> FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. FIG. 2 is a circuit diagram of the drive circuit shown in FIG. It is an input / output waveform diagram. In FIG. 1, reference numeral 50 denotes a semiconductor device of the present invention. One terminal of a battery 41 is connected to a power terminal 31 of the semiconductor device 50, and the other terminal of the battery 41 is connected to a ground terminal 30. And the output terminal 3 via an inductive load 40 such as a solenoid or a motor.
3 is connected.

The internal circuit of the semiconductor device 50 of this embodiment is a power MOS used as a high side switch.
It comprises an FET 1 and a control circuit for controlling the gate of the power MOSFET 1. That is, the semiconductor device 5
0 is an N-channel power MOSFET 1 having a drain connected to the power supply terminal 31 and a source connected to the output terminal 33, and an N-channel power MOSFET 1 having a drain and a source connected between the gate and the source of the power MOSFET 1. MOSFET3 and drain are power MOS
N is connected to the gate of the FET 1 via the diode 8 and the source is connected to the ground terminal 30 via the ground line (first ground line) 34 of the control circuit.
A channel MOSFET 2, an inverter 21 whose output is connected to the gate of the MOSFET 2, a P-channel MOSFET 4 whose source and drain are connected to the power supply terminal 31 and the gate of the MOSFET 3, respectively, and a power MOSFET.
A booster circuit 19 connected to the gate of ET1, a series circuit of diodes 12 and 13 whose anodes are connected between the power supply terminal 31 and the gate of the power MOSFET 1,
A series circuit of diodes 26 and 27 whose cathodes are connected between a second ground line 36 connected to the output terminal 33 and the gate of the power MOSFET 1;
A resistor 17 connected between the gate and the source of the ET3, an input signal processing circuit 35 having an input connected to the input terminal 32 and an output connected to the input of the booster circuit, the gate of the MOSFET 4, and the input of the inverter 21; Consists of Although not shown, the input signal processing circuit 35 includes a level shift circuit, an overheat protection circuit, an overcurrent protection circuit, and the like.

As described above, the semiconductor device 50 has the power MO
It is composed of a high-side switch in which the SFET 1 is grounded as a source follower, and a control circuit composed of MOSFETs 2, 3, 4 and a booster circuit 19 for controlling the switch, and has input / output characteristics as shown in FIG. FIG. 2 shows an input voltage waveform at the input terminal 32 and an output voltage waveform at the output terminal 33 of the semiconductor device 50 in which the inductive load 40 and the battery 41 having the voltage _VDD are connected as shown in FIG. It is an output characteristic diagram. That is, as shown in FIG. 2, when a voltage of, for example, 5 V is applied to the input terminal 32, the voltage input to the booster circuit 19 via the input signal processing circuit 35 is higher than the power supply voltage V _{DD of the} battery 41 by the booster circuit 19. And is applied to the gate of the power MOSFET 1 to turn on the power MOSFET 1. To drive with a sufficiently high gate voltage equal to or higher than the power supply voltage V _DD , a power MOS
FET1 has a low on-resistance of about 100 mΩ or less,
The output terminal 33 has substantially the same voltage as the power supply voltage V _DD . As a specific circuit configuration example of the booster circuit 19, for example, proceedings of PCIM'88, 32nd to 4th
The charge pump circuit described in page 0 (PCIM'88 PROCEEDINGS, pp. 32-40) can be suitably used. In FIG. 1, a diode 12 is a power MOSFET.
It is provided so that the gate of T1 can be boosted to the voltage V _DD of the power supply terminal 31 or more.
Is a gate protection diode of the power MOSFET1.

[0043] In order to turn off the power MOSFET1 the input voltage V _IN of the input terminal 32 as shown in FIG. 2 0
Then, the operation of the booster circuit 19 is stopped. At this time, since a high potential (for example, 5 V) is applied to the gate of the MOSFET 2 via the input signal processing circuit 35 and the inverter 21, the MOSFET 2 is turned on. Further, the gate of the MOSFET 4 is set to a low potential (for example, 0 V) via the input signal processing circuit 35, so that the MOSFET 4 is turned on and drives the MOSFET 3, so that the MOSFET 3 is also turned on.

Here, the reason why the MOSFET 2 and the MOSFET 3 are used for lowering the output terminal 33 is as follows. When the voltage V _OUT of the output terminal 33 is
Regarding ET2, within the range of equation (1), MOSFET
In the range of Equation (2), the power MOSFE
This is because T1 cannot be cut off.

[0045]

V _OUT <V _{on (2)} + V _{f (8)} −V _{th (1)} (1) V _OUT > V _DD −V _{on (4)} −V _{th (3)} (2) , V _DD is the voltage of the power supply terminal 31, and V _{th (1)} and V _{th (3)} are the power MOSFET1 and MOSFET3, respectively.
Threshold voltage, V _{f (8)} is the forward voltage of diode 8, V
_{on (2)} and V _{on (4)} are the ON voltages of MOSFET2 and MOSFET4.

This will be described in more detail as follows. Power MOSFET1 even if MOSFET2 is turned on
Can be reduced only to a voltage ( _{Von (2)} + _{Vf (8)} ) which is almost equal to the potential of the ground terminal 30, and the voltage _VOUT of the output terminal 33 is reduced to the voltage of this ground terminal by the back electromotive force. Voltage close to ground (V _{on (2)} +
V _{f (8)} ) when the potential drops below V _{th (1).}
Since OSFET1 is turned on, it cannot be cut off by MOSFET2.

Since the source potential of the MOSFET 3 is the voltage of the output terminal 33 when the power MOSFET 1 is in the ON state, that is, almost the power supply voltage V _DD ,
Even if the SFET 4 is turned on, the gate potential of the MOSFET 3 is V _DD −V _{on (4),} which is lower than the source potential of the MOSFET 3, and the MOSFET 3 cannot be turned on. MOSFET
In order for 3 to turn on, the source potential must be lower than the gate potential by _{Vth (3)} or more. Therefore, MOSF
ET3 is the power MO when the voltage V _OUT of the output terminal 33 is higher than the voltage (V _DD −V _{on (4)} −V _{th (3)} ) close to the power supply voltage.
SFET1 cannot be cut off.

That is, the MOSFET 2 is a power MOS
FET1 is turned off from the on state, and the output terminal voltage V _OUT
Is reduced to a voltage close to the above-mentioned ground terminal voltage, and the power MOSFET 1 can be continuously cut off.
The operation starts after the output terminal voltage V _OUT becomes close to the power supply voltage after the OSFET 1 is turned off, and continues to turn off the power MOSFET 1 even when the output terminal voltage V _OUT becomes a negative voltage lower than the ground terminal level. Can be executed. The diode 8 blocks a current flowing from the ground terminal 30 through a parasitic diode existing between the source and the drain of the MOSFET 2 when the gate potential of the power MOSFET 1 becomes a negative voltage, and
This is for enabling the gate voltage of SFET1 to become a negative voltage in accordance with the output terminal voltage.
The diode 8 may be connected to the source side of T2.

Next, the negative output sustain voltage will be described.
Since the load of the semiconductor device 50 of the present embodiment is the inductive load 40, when the power MOSFET 1 is cut off, back electromotive force is generated at both ends of the inductive load 40. Therefore, the output current I _OUT flowing through the inductive load 40 continues to flow, and as shown in FIG. 2, the voltage V _OUT at the output terminal 33 decreases until the clamp diode 13 breaks down and the power MOSFET 1 turns on. Assuming that the output voltage at this time is the negative output sustaining voltage _VSUS , the breakdown voltage of the diode 13 is BV ₍₁₃₎ , and the forward voltage of the diode 12 is _{Vf (12)} , the following expression is obtained.

[0050]

V _SUS = V _DD -BV ₍₁₃₎ -V _{f (12)} -V _{th (1)} (3) Thereafter, the output current I _OUT flowing through the inductive load 40 decreases, and this current becomes When the current stops flowing, the output terminal voltage V _OUT becomes zero volt. Here, assuming that the inductance component of the inductive load 40 is L _L and the resistance component is R _L , the inductive load 4
Since the cut-off time t _off of the output current I _OUT flowing to 0 is expressed by Expression (4), the cut-off time t _off can be reduced as the negative output sustaining voltage _VSUS increases.

[0051]

T _off = (L _L / R _L ) · ln (1−I _OUT · R _L / V _SUS ) (4) In the conventional circuit shown in FIG. 11, the MOSFET of this embodiment is used.
Since the gate of the N-channel MOSFET72 corresponding to 3 was connected to the ground corresponding to the first ground line 34 of this embodiment, MOSF negative output sustaining voltage V _SUS
It could not be made larger than the gate-source breakdown voltage of ET72. For this reason, the shortening of the cutoff time t _off has been limited. On the other hand, in this embodiment, the MOSFE
Since the gate of T3 is connected to the output terminal 33 via the resistor 17, the value of the negative output sustaining voltage _VSUS can be increased by an amount that allows the gate voltage of the MOSFET 3 to be lower than the voltage of the first ground line 34. . For this reason,
It is possible to increase the cutoff speed. For example, in the case of the present embodiment, the voltage V _{DD of the} battery 41 = 12 V, the diode 13
₍₃₎ = 44V, forward voltage _{Vf (12) of} diode 12 = 0.6V, and threshold voltage _{Vth (1) of} power MOSFET ₁ = 2V, negative output is maintained from equation (3). voltage V _SUS can to a large value of about -35 V. For this reason,
In the case of performing the pulse width modulation drive, it is possible to solve the problem that the control range of the pulse width is limited due to the restriction of the minimum value of the pulse width.

In the conventional circuit, a power MOSFET
P-channel MO for control between gate 70 and ground
Since the source and gate of SFET 75 were connected,
The gate voltage of the power MOSFET 70 is the control MOSF
It was limited by the gate breakdown voltage of ET75 (usually about 20 V). For this reason, it has not been possible to use a battery having a power supply voltage V _DD of 24 V or more and drive the gate of the power MOSFET 70 at a high voltage of 24 V or more in order to reduce the ON resistance of the power MOSFET 70. On the other hand, the semiconductor device 5 of the present embodiment
0, the gate voltage of the power MOSFET 1 is MOSFE
Since it is not limited by the gate breakdown voltage of T2 and T3, MOS
As the FETs 2 and 3, high-breakdown-voltage MOSFETs having a drain-source breakdown voltage of about 70 V can be used. Therefore, a high voltage of 24 V or more can be used for the battery 41, and
The gate voltage of the power MOSFET 1 can be applied by a voltage boosted by about 8 V from the voltage of the power supply terminal 31 by the boosting circuit 19, so that there is an advantage that the on-resistance of the power MOSFET 1 can be reduced.

Incidentally, in the circuit example of FIG.
Although 13 is a series circuit in which the anodes are connected to each other, the order may be interchanged to form a series circuit in which the cathodes are connected. Further, the clamping diode 13 may be configured by connecting a plurality of diodes in series so as to obtain a desired withstand voltage.

FIG. 9 shows a semiconductor device 50 of this embodiment.
Power MOSFET 1 and MOSFET
2 shows a cross-sectional structure of main elements such as 2, 3, and 4. In FIG. 9, the semiconductor layer regions having the same reference numerals and different alphabets indicate regions which are formed in the same manufacturing process step but are electrically isolated.
Semiconductor layers having the same reference numerals but without alphabets only indicate that they are formed in the same manufacturing process step.

The semiconductor device 50 of the present embodiment has a resistivity of 0.02 Ω · cm to 0.
A P-type epitaxial layer 10 having a resistivity of about 3 Ω · cm is formed on a high-concentration N-type semiconductor substrate 101 of about 002 Ω · cm.
3a and 103b are formed to a thickness of about 20 μm, and N-type epitaxial layers 105a to 105
Before forming the P-type epitaxial layer, phosphorus of about 5 × 10 ¹⁴ cm ^{−2 is applied} to a predetermined region of the semiconductor substrate 101 to form the P-type epitaxial layer into regions of 103 a and 103 b. The high-concentration N-type buried layer 102a formed by selective ion implantation using a photoresist mask or the like, and antimony selectively diffused and formed in a predetermined region of the P-type epitaxial layer after forming the P-type epitaxial layer were used as impurities. The high-concentration N-type buried layer 104a having a layer resistance of about 20Ω / □ is further connected by thermal diffusion. Alternatively, the high-concentration N-type buried layer 104a may be connected to the high-concentration N-type buried layer 102a at the same time as the formation by thermal diffusion. Further, the N-type epitaxial layer is
Layer resistance of 3Ω to separate into the regions of 05a to 105d.
/ □ high concentration P-type diffusion layers 108a and 108b are formed from the semiconductor surface to the P-type epitaxial layers 103a and 103b.
To the power MO.
A plurality of island regions for the control circuit separated from the SFET 1 can be formed.

In FIG. 9, the high-concentration N-type semiconductor region 10
1, 102a, 104a, 107a, P
-Type epitaxial layer 103b and high-concentration P-type diffusion layer 108
The p-type semiconductor region constituted by the p-type epitaxial layer 10b is a region of the first ground line 34 shown in FIG.
The P-type semiconductor region composed of the high-concentration P-type diffusion layer 108a and the high-concentration P-type diffusion layer 108a is a region of the second ground line 36 connected to the output terminal 33 shown in FIG. High concentration N-type buried layer 10
2a, 104a and N-type epitaxial layer region 105
a is a drain, the polycrystalline silicon layer 110 is a gate electrode,
The N-type diffusion layer 113 is formed as a source and the P-type diffusion layer 111 is formed as a channel diffusion layer (body).
The source aluminum electrode 114a of the OSFET 1 is also connected to the high-concentration P-type diffusion layer 108a serving as a second ground region. The MOSFETs 2 and 3 each have an N-type diffusion layer 113 as a source, a P-type diffusion layer 111 as a channel diffusion layer, and N-type epitaxial layers 105c and 105b.
Vertical N-channel MOSFET with high drain voltage
MOSFET2 is a P-type epitaxial layer 103
The element is separated by a first ground region consisting of a high-concentration P-type diffusion layer 108b and the MOSFET 3, and the MOSFET 3 is separated by a second ground region consisting of a P-type epitaxial layer 103a and a high-concentration P-type diffusion layer 108a. MOSFET
Reference numeral 4 denotes a lateral high-breakdown-voltage P-channel MOSFET having the P-type diffusion layer 112 as a source and a drain and the low-concentration P-type diffusion layer 115 as an offset drain region for increasing a breakdown voltage.
Although not shown in the main circuit of FIG. 1, the SFET 10 can be used as needed on the same chip, and a lateral N-channel MOSFET using the N-type diffusion layer 113 as a source and a drain.
For CMOS circuits. Reference numeral 106 is an insulating film such as an oxide film.

By having such a cross-sectional structure,
In the semiconductor device 50 of the present embodiment, the P-type semiconductor layer region 10 in the second ground region separating the MOSFET 3
Since the potentials of the sources 3a and 108a fluctuate together with the potential of the source of the power MOSFET 1 (the output terminal 33 of FIG. 1), the P-type semiconductor layer constituting the first ground region (the control circuit ground line 34 of FIG. 1). Regions 103b and 108
power MOS even if the potential of the output terminal 33 is lower than
MOSFET 3 can be kept on so that FET 1 is turned off.

The second ground area (the second ground line 36 connected to the output terminal 33 in FIG. 1) and the power M
The withstand voltage with respect to the conductor substrate 101 (connected to the power supply terminal 31 in FIG. 1), which is the drain of the OSFET 1, can be designed to have a high withstand voltage of 80 V or more because the high-concentration diffusion layers are not in contact with each other. Between the region and the second ground region, a high-concentration N-type region 10 maintained at a higher potential (the voltage of the power supply terminal 31 in FIG. 1) than these ground regions.
1, 102a, 104a, and 107a exist, so P
The second ground region including the mold layer regions 103a and 108a can be set to a potential lower than the semiconductor substrate 101 by 80V or more. Therefore, even if the second ground region has a higher or lower potential than the first ground region including the P-type layer regions 103b and 108b, the parasitic transistor existing between the two ground regions does not operate. Absent.

Since the MOSFET 4 has the low-concentration P-type offset region 115 on the drain side, the drain-source breakdown voltage can be easily set to 40 V or more. For example, to a -35V negative output sustaining voltage V _SUS as estimated in Figure 1, the power supply terminal voltage 12
In the case of V, it can be realized by setting the breakdown voltage of the MOSFET 4 to a breakdown voltage of 47 V or more. MOSFE
As T2 and MOSFET3, as shown in FIG. 9, a vertical MOSFET that can easily achieve a high withstand voltage can be used, and thus a drain-source withstand voltage of 70 V or more can be easily obtained. Therefore, when a 12 V or 24 V battery normally used for a vehicle is used as the battery 41, the gate voltage of the power MOSFET 1 is set to the MOSFETs 2 and 3.
Can be boosted without being limited by the withstand voltage between the drain and the source.

It should be noted that the numerical values of the conditions of the above-described manufacturing process are merely examples, and the present invention is not limited to these values. Needless to say, they can be appropriately changed according to the required breakdown voltage.

<Embodiment 2> FIG. 3 shows a second embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same reference numerals in FIG. 3 denote the same constituent parts as those shown in FIG. 1 of the first embodiment, and a detailed description thereof will be omitted. That is, in this embodiment, the voltage regulator 20 connected to the power supply terminal 31 is provided, and the constant voltage output line 39 of the voltage regulator 20 and the power MOSFET
A point where a series circuit of diodes 12 and 14 whose anodes are connected between the gates of T1 is connected;
The difference from the configuration of the first embodiment is that the source of the OSFET 4 is connected to the constant voltage output line 39 of the voltage regulator 20 and the drain is connected to the gate of the MOSFET 3 via the diode 9.

As described above, the semiconductor device 51 of this embodiment is
A constant voltage of, for example, 5 V is generated by the voltage regulator 20, and a negative output maintaining voltage V
_Since the cathode of the clamping diode 14 that determines _SUS is connected, the value of the negative output sustaining voltage _VSUS is stabilized without fluctuation. Further, since the source of the MOSFET 4 is connected to the constant voltage output line 39, the range of the output terminal voltage V _{OUT at which} the MOSFET 3 cannot cut off the power MOSFET 1 is defined _assuming that the voltage of the constant voltage output line 39 is V _DD0. The following equation is used instead of the equation (2).

[0063]

V _OUT > V _DD0 −V _{th (3)} −V _{on (4)} (5) In this embodiment, the source of the MOSFET 4 and the MOSFET
The diode 9 provided between the gates of T3 is connected to the output terminal 33.
Is higher than the voltage V _DD0 of the constant voltage output line 39, the parasitic diode existing between the drain and the body of the MOSFET 4 is forward-biased, and current flows from the output terminal 33 through the resistor 17 to the constant voltage output line 39. It works to prevent that.

In this embodiment, the source of the MOSFET 4 is a constant voltage output line 39 whose voltage is lower than that of the power supply terminal 31.
Since is connected, there is advantage that it between MOSFET4 drain-source breakdown voltage BV _{DSS (4)} is smaller necessary to increase the absolute value of the negative output sustaining voltage V _SUS. That is, in the configuration of FIG. 1, the absolute value of the negative output sustaining voltage _VSUS needs to satisfy Expression (6), but in this embodiment, Expression (7) may be satisfied. Therefore, the negative output sustaining voltage _VSUS in the present embodiment is represented by Expression (8).

[0065]

| V _SUS | <V _DD − | BV _{DSS (4)} |… (6) | V _SUS | <V _DD0 − | BV _{DSS (4)} | −V _{f (9)} … (7) V _SUS = V _{DD0 −BV (14)} −V _{f (12)} −V _{th (1)} (8) Further, since the voltage V _DD0 is the voltage of the constant voltage output line 39, the voltage of the battery 41 As compared with the case where the voltage _VDD is directly used, there is an advantage that the fluctuation of the negative output sustaining voltage _VSUS is reduced and the fluctuation of the cutoff speed is reduced. In other respects, it is needless to say that the same effect as in the embodiment of FIG. 1 is obtained.

A series circuit of the clamping diode 14 and the backflow preventing diode 12 for determining the negative output sustaining voltage _VSUS can be connected between the ground terminal 30 and the output terminal 33. The negative output sustaining voltage V _SUS of the case can be designed in the above equation (8) as V _DD0 = 0V.

The diodes 14 and 12 for determining the negative output sustaining voltage are connected between the constant voltage output line 39 and the gate of the power MOSFET 1 as shown in FIG. 3, and are connected to the power supply terminal 31 as shown in FIG. Diode 1 whose anodes are connected to the gate of power MOSFET 1
2 and the series circuit of the clamping diode 13 are connected and arranged, the value of the normal negative output sustaining voltage _VSUS is kept constant by the clamping diode 14, and the power supply terminal 31 and the output terminal are kept by the clamping diode 13. 3
3, it is possible to protect the power MOSFET 1 from being destroyed even if an overvoltage is applied.
Incidentally, the withstand voltage of each of the clamping diodes 13 and 14 may have a desired value. For example, the voltage of the constant voltage output line 39 is 5 V, and the voltage of the battery 41 is 12
V, and the negative output sustain voltage V _SUS -35 V, power MOSF
Assuming that the withstand voltage of ET1 is about 70V, the withstand voltage of the clamp diode 14 may be set to 37.4V, and the withstand voltage of the clamp diode 13 may be set to 65V. Further, as the clamping diodes 13 and 14, a plurality of diodes may be connected in series so as to obtain a desired required breakdown voltage and may be used as a clamping diode.

Since the source of the MOSFET 4 is connected to the constant voltage output line 39 of 5 V, the MOSFET 4
Breakdown voltage of T4 is the case the power supply terminal voltage is 12V, the negative output voltage V _SUS for realizing -35 V, may be set when a different low-voltage of about 40V in Example 1. still,
The cross-sectional structure of the semiconductor device 51 of the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

<Embodiment 3> FIG. 4 shows a third embodiment of a semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, in FIG. 4, the same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the input signal processing circuit 35
Further provided with an additional output, an inverter 22 having the additional output as an input, a P-channel MOSFET 25 having a gate connected to the output of the inverter 22 and a source connected to the power supply terminal 31, and a gate of the MOSFET 3・ Drain is MOSF instead of resistor 17 between sources
Connected to the gate of ET3 and the source is MOSFE
N-channel MOSFET 23 connected to the source of T3
And a resistor 24 connected between the gate and the source of the MOSFET 23.
Is different from the configuration of the first embodiment in that the drain is connected to the gate of the MOSFET 23.

In the semiconductor device 52 of the present embodiment having the above-described configuration, the M provided in place of the resistor 17 shown in FIG.
The OSFET 23 operates as follows to cut off the MOSFET 3. When the input terminal 32 goes high, one additional output of the input signal processing circuit 35 goes low via the inverter 22 and is applied to the gate of the MOSFET 25. As a result, the MOSFET 25 turns on and the MOSFET
Since the gate of the gate 23 is driven, the MOSFET 23 is turned on and the MOSFET 3 is cut off. When the potential of the input terminal 32 becomes low, the input signal processing circuit 35 and the inverter 2
Since the gate voltage applied to the MOSFET 25 through the gate 2 becomes high potential, the MOSFET 25 is turned off,
Since the electric charge accumulated in the gate of the FET 23 is discharged via the resistor 24, the MOSFET 23 is also turned off. on the other hand,
At this time, the output of the input signal processing circuit 35 applied to the gate of the MOSFET 4 is at a low potential.
Turns on and drives the gate of MOSFET 3, so that M
OSFET3 is also turned on. For other points, see FIG.
Since the configuration and semiconductor structure are the same as those of the first embodiment shown in FIG.

<Embodiment 4> FIG. 5 shows a fourth embodiment of a semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same reference numerals in FIG. 4 denote the same components as those in the second embodiment shown in FIG. 3, and a detailed description thereof will be omitted. That is, in this embodiment, the drain is the power supply terminal 3
1 and a source connected to the anode of a diode 12 for backflow prevention.
And diodes 14, 15 whose cathodes are connected to each other
A diode 13 whose cathode is connected to the power supply terminal 31 and whose anode is connected to the anode of the diode 15; and whose cathode is connected to the anode of the diode 13 and whose anode is connected to the constant voltage output line 39 of the voltage regulator 20. Diode 16 and MOSF
A resistor 18 connected between the gate and the source of the ET 6;
It differs from the configuration of the third embodiment in that it is connected to the gate of ET6.

In the semiconductor device 53 of the present embodiment thus configured, the negative output sustaining voltage V
_Since the current for maintaining _SUS is supplied, the diode 1
The element sizes of 3, 14, 15, and 16 can be reduced. The resistor 18 serves to turn off the MOSFET6 when the output terminal voltage V _OUT is above the negative output sustaining voltage V _SUS.

In this embodiment, the normal negative output sustaining voltage V _SUS
Is determined by the voltage value at which the clamping diode 14 breaks down, and is expressed by equation (9). However, when the power supply voltage of the battery 41 becomes too high and the difference between the power supply voltage _VDD applied to the power supply terminal 31 and the negative output sustaining voltage _VSUS becomes larger than the withstand voltage of the power MOSFET 1, the power M
Maximum negative output sustaining voltage V to protect OSFET1
_SUSmax is set as in equation (10). In other respects, it is needless to say that the same effect as in the embodiment of FIG. 3 is obtained.

[0074]

V _SUS = V _DD0 −V _{f (16)} −V _{f (15)} −BV ₍₁₄₎ −V _{th (6)} −V _{th (1)} (9) V _SUSmax = V _{DD −BV ( 13)} −V _{f (15)} −BV ₍₁₄₎ −V _{th (6)} −V _{th (1)} (Embodiment 5) FIG. 6 shows a fifth embodiment of the semiconductor device according to the present invention. FIG. 2 is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of description, the same reference numerals in FIG. 6 denote the same constituent parts as those shown in FIG. 5 of the fourth embodiment, and a detailed description thereof will be omitted. That is, in this embodiment, instead of the resistor 18 in FIG.
The difference is that a channel MOSFET 28 is used. This MOSFET 28 has a channel width W of MOSF
Smaller than ET6 and its drain and gate are MOS
Connect to the gate of FET and the source is MOSFET
6 and a current mirror with the MOSFET 6.

In the semiconductor device 54 of the present embodiment thus configured, the breakdown current flowing through the diodes 13, 14, 15, 16 is smaller than that of the configuration of FIG. 5, and a desired negative output can be maintained with this small breakdown current. Voltage V _SUS
Can be obtained. Therefore, there is an advantage that the element size of the diodes 13, 14, 15, 16 can be further reduced as compared with the fourth embodiment.

<Embodiment 6> FIG. 7 shows a sixth embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same components as those shown in FIG. 7 of the fourth embodiment in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the source is a power MOS
The fourth embodiment differs from the fourth embodiment in that a P-channel MOSFET 5 having a gate connected to the FET 1, a drain connected to the anode of the diode 8, and a gate connected to the output terminal 33 is newly provided.

In the semiconductor device 55 of the present embodiment thus configured, when the voltage between the gate and the source of the power MOSFET 1 becomes lower than the threshold voltage of the MOSFET 5, the MOS
Since the cutoff operation of the power MOSFET 1 by the FET 2 is completed, there is an effect that the turn-off characteristic of the power MOSFET 1 becomes soft and noise is reduced.

The MOSFET 2 is a power MOSFET
Power MOSFE by discharging the gate charge of
The voltage V of the output terminal 33 at which the cutoff operation of T1 becomes impossible.
_In the case of this embodiment, the range of _OUT is determined by the equation (1) described in the first embodiment.
, But the range of equation (11). However, V _{on (5} ) in equation (11) is the on-voltage of MOSFET5.

[0079]

V _OUT <V _{on (2)} + V _{f (8)} + V _{on (5)} −V _{th (1)} (11) In the case of the present embodiment, between the output terminal 33 and the power supply terminal 31 When a short-circuit failure occurs, the MOSFET 5 is turned off, so that no current flows through the MOSFET 2. Therefore,
There is an effect that it is possible to prevent the MOSFET 2 from being in an overcurrent and overvoltage state and causing element destruction.

<Embodiment 7> FIG. 8 shows a seventh embodiment of a semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, in FIG. 8, the same components as those of the sixth embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, a low on-resistance (for example, about 10Ω) MOSFET 7 having a drain connected to the ground terminal 30, a source connected to the first ground line 34, and a gate connected to the power supply terminal 31 is newly provided. Different. Note that the diode 29 shown in the figure is a parasitic diode, and is an element that is necessarily inserted structurally between the first ground line 34 and the power supply terminal 31, and is present in the semiconductor devices of the first to sixth embodiments. Things.
This parasitic diode 29 is formed between the first ground region including the P-type layers 103b and 108b shown in FIG. 9 and the N-type regions 101, 102a, 104a and 107a.

In the semiconductor device 56 of the present embodiment thus configured, when the battery 41 is normally connected as shown in FIG. 8, the MOSFET 7 is turned on, so that the first ground line 34 The ground terminals 30 have the same potential and operate in the same manner as the embodiment of FIG. On the other hand, when the user mistakenly connects the battery 41 in reverse, a negative voltage is applied to the gate of the MOSFET 7, so that the battery is turned off and the ground terminal 30 is disconnected from the first ground line 34. Therefore, no overcurrent flows from the ground terminal 30 through the parasitic diode 29. For this reason, element destruction due to overcurrent due to reverse connection of the battery 41 can be prevented. In addition,
When the battery 41 is reversely connected, there is also a current flowing from the output terminal 33 to the power supply terminal 31 through a parasitic diode existing between the drain and the body of the power MOSFET 1, but this current is present in the inductive load 40. In this embodiment, there is no problem because the parasitic resistance is suppressed. Therefore, the semiconductor device 56 for driving the inductive load according to the present embodiment can realize reverse connection protection of the battery.

Here, the MOSFET 7 for protecting the reverse connection of the battery shown in FIG.
FIG. 10 is a sectional structural view of the semiconductor device. The other cross-sectional structures are the same as those in FIG. 9, and the manufacturing process conditions are also the same. As shown in FIG.
ET7 is the same vertical type M as MOSFETs 2 and 3 in FIG.
OSFET. The source 113a and the body 111a of the MOSFET 7 are connected to the first
Connected to the P-type layer region 108b serving as a ground region,
The drain electrode 114e of the SFET 7 is connected (not shown) to the ground terminal 30 of the semiconductor device 56 of FIG.
The polycrystalline silicon layer 110a serving as the gate electrode of ET7 is connected to the power supply terminal 31 in FIG. 8 or a voltage line having the same polarity as the power supply terminal 31 (not shown).

With this connection, when the battery is connected to the semiconductor device 56 with the correct polarity, the MOSFET 7 is turned on and the ground terminal 30 is turned on.
Is equal to the potential of the first ground region. On the other hand, when the battery is reversely connected, a negative voltage is applied to the gate, so that the MOSFET 7 is turned off,
The ground terminal 30 is separated from the first ground region. In the case of the present embodiment, since the drain-source breakdown voltage of the MOSFET 7 is 70 V or more, a reverse connection protection voltage of the battery of about 70 V or more can be obtained.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment.
For example, in the above-described embodiment, the MOSFETs 2, 3, 7 and the like are described using vertical MOSFETs which can easily achieve a high withstand voltage. However, horizontal MOSFETs and bipolar transistors (in this case, the drain is a collector, the gate is a base, and the source is a The same effect can be obtained by using (replacement with an emitter), and various design changes can be made without departing from the spirit of the present invention.

[0085]

As is apparent from the above-described embodiments, according to the present invention, the power MOSFET is cut off when the gate voltage of the power MOSFET is higher than the ground voltage and is connected between the gate of the power MOSFET and the control circuit ground. A first MOSFET connected between the gate and the output terminal of the power MOSFET, and performing a cutoff operation when the gate voltage of the power MOSFET is equal to or lower than the power supply voltage, and performing a cutoff operation even when the output terminal voltage becomes a negative voltage. 2 MOSFE
By using T, the power MOSFET driving the inductive load can be cut off at high speed.

Since the gate voltage of the power MOSFET is not limited by the gate breakdown voltage of the first and second MOSFETs, the first and second M
As a result, a high voltage MOSFET of 60 V or more can be used as the OSFET, and a high battery voltage of 24 V or more can be used.

Further, the eighth MOSFET provided between the control circuit ground and the ground terminal is turned off when the battery is reversely connected to disconnect the control circuit ground from the ground terminal. A parasitic diode existing between the power ground and the power supply terminal does not operate, so that destruction of the semiconductor device can be prevented.

[Brief description of the drawings]

FIG. 1 is an inductive load drive circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a waveform diagram showing input / output characteristics of the inductive load drive circuit shown in FIG.

FIG. 3 is an inductive load drive circuit diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is an inductive load drive circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

FIG. 5 is an inductive load drive circuit diagram showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 6 is an inductive load drive circuit diagram showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 7 is an inductive load drive circuit diagram showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 8 is an inductive load drive circuit diagram showing a seventh embodiment of the semiconductor device according to the present invention.

FIG. 9 is a sectional structural view of a main part of the semiconductor device shown in FIG. 1;

FIG. 10 is a sectional structural view of a main part of the semiconductor device shown in FIG. 8;

FIG. 11 is a main part circuit diagram showing a conventional inductive load driving circuit.

[Explanation of symbols]

1: Power MOSFET, 2, 3, 6, 7, 10, 23, 28 ... N-channel MOS
FET, 4, 5, 25 ... P-channel MOSFET, 8, 9, 12, 13, 14, 15, 16, 26, 27 ...
Diodes, 17, 18, 24: Resistor, 19: Boost circuit, 20: Regulator, 29: Parasitic diode, 21, 22: Inverter, 30: Ground terminal, 31: Battery power terminal, 32: Input terminal, 33 ... Output terminal, 34: ground line (first ground line) of control circuit, 35: input signal processing circuit, 36: second ground line 39: constant voltage output line, 40: inductive load, 41: battery, 101: high N-type silicon substrate, 102a, 104a to 104e: N-type buried layer, 103a, 103b: P-type epitaxial layer, 105a to 105e: N-type epitaxial layer, 106: insulating film, 107a to 107d, 113, 113a ... N Type diffusion layer, 108a, 108b, 109, 111, 111a, 11
2. P-type diffusion layer, 115: low-concentration P-type diffusion layer, 110, 110a: polycrystalline silicon layer, 114, 114a: aluminum electrode layer, 114c, 114d: aluminum electrode layer (first ground).

──────────────────────────────────────────────────続 き Continued on the front page (58) Surveyed fields (Int.Cl. ⁷ , DB name) H03K 17/695 H03K 17/04 H03K 17/06 H03K 19/0175

Claims (6)

(57) [Claims] A power MOSFET having a drain connected to a power supply terminal and a source connected to an output terminal; a power MOSFET disposed between a gate of the power MOSFET and a control circuit ground; A first MOSFET that turns off a power MOSFET, a second MOSFET that is arranged between a gate of the power MOSFET and the output terminal, and turns off the power MOSFET based on a voltage of the input terminal; It is connected to the gate and a gate charging circuit for turning on the power MOSFET on the basis of the voltage of the input terminal, graphene gate and the control circuit of the power MOSFET
And the drain source of the first MOSFET.
Current flowing through the parasitic diode between the
A diode for blocking the first MOSFET.
A semiconductor device, which is connected and arranged in series with T. 2. A third MOSFET for turning on the second MOSFET, and a resistor or a fourth MOSFET connected between the gate and source of the second MOSFET for turning off the second MOSFET. further provided consisting claim 1 Symbol mounting semiconductor device of the. 3. A constant voltage power supply for obtaining a predetermined constant voltage from a power supply voltage, wherein the third MOSFET and a third MO are provided between the constant voltage power supply and the gate of the second MOSFET.
3. The semiconductor device according to claim 1, further comprising a series circuit with a diode for blocking a current flowing through a parasitic diode existing between a drain and a source of the SFET. 4. A semiconductor device according to any one of claims 1 to 3, further provided comprising a clamping diode between the gate and the power supply terminal or a constant voltage power source of the power MOSFET. 5. A first diode and a fifth MOSF connected between a gate of the power MOSFET and a power supply terminal.
A sixth MOS in which a series circuit of ET is provided, and a resistor or a drain and a gate are diode-connected between a gate and a source of the fifth MOSFET
An FET, from the gate of the power MOSFET to the fifth MOS
The second is connected to the power supply terminal via the gate of the FET.
A constant-voltage power supply for obtaining a predetermined constant voltage from a power supply voltage applied to the power supply terminal; and a fifth MOS from a gate of the power MOSFET.
The semiconductor device according to the third any one of claims 1 to 4 formed by providing a clamping diode while via the gate of the FET reaches the constant voltage power supply. 6. according to any one of claims 1 to 5, further provided comprising a seventh MOSFET having a gate connected to the output terminal between the gate and the first MOSFET of the power MOSFET Semiconductor device.