JPH0262114A - Switching circuit - Google Patents

Abstract

PURPOSE:To actively use a parasitic diode existing between a drain and a body and to obtain an easy switching circuit by connecting the source and the body of an MOS transistor, making into a signal input terminal, using the drain as a signal output terminal, and using a gate as a control terminal. CONSTITUTION:An input signal voltage Vin is applied to the source side of an N channel MOS transistor M1 connecting a source and a body and an output signal voltage Vout is taken out from a drain side. An N channel MOS transistor M2 is used as a terminal for absorbing the current when the transistor M1 is forcibly off. At the transistor M1, a diode D1 for protecting the gate is provided and the widening value of the input output voltage can be set to the gate pressure resistance or above of the transistor M1. Thus, since a parasitic diode to make a drain into a cathode and to make a body into an anode occurs between the drain and the body of the transistor M1, a negative direction pulse is suppressed to the input pulse.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a switch circuit that conducts or cuts off an input signal using a semiconductor element, and is particularly suitable for controlling a high voltage input signal with a low voltage signal. This invention relates to a switch circuit and its driving method.

[Conventional technology]

Conventionally, regarding analog switch circuits that conduct or cut off input signals using semiconductor elements, see How to Use rI''ET (1983), pages 110 to 114 (CQ
Published by Shuppan Co., Ltd.). Here, a small signal input is applied to the source of a MOS transistor, an output signal is taken from the drain, and the body (substrate) is designed such that the pn junction is not forward biased with respect to the source or drain under any conditions. A method is described in which the gate pressure is set to control signal conduction and cutoff.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the conduction or interruption of high voltage signals, nor does it give consideration to the active use of parasitic diodes between the drain and the body.

A first object of the present invention is to provide a simple switch circuit that actively utilizes a parasitic diode existing between the drain and body of a MOS transistor.

A second object of the present invention is to provide a high-voltage signal switch circuit that particularly controls conduction and cutoff of a high-voltage signal using a low-voltage signal.

A third object of the present invention is to provide a capacitive load driving device that drives a capacitive load with low power consumption.

[Means to solve the problem]

The first object is achieved by connecting the source and body of the MOS transistor, using this as a signal input terminal, using the train as a signal output terminal, and using the gate as a signal control terminal.

The second purpose is to
A protection diode is connected between the sources, and this MO
This is achieved by providing means for connecting the first active element to the gate in order to force the S transistor to turn off.

The third purpose is to use the JP-A-61-1 as a pulse generator.
This is accomplished by using the power recovery circuit described in No. 32997, by using the pulses from this pulse generator as the input to the switch circuit, and by connecting a capacitive load to the output terminal.

[Function] A switch circuit in which the source and body of a MOS transistor are connected and this is used as a signal input terminal, the drain is used as an output terminal, and the gate is used as a signal control terminal, when an n-channel MOS transistor is used as a switching element, When the human power is at a high potential, the output will also be at a high potential, and if a p-channel MOS transistor is used as a switching element, when the input is at a low potential, the output will also be at a low potential, making it impossible to control opening and closing by the gate. However, the former does not malfunction when used as a negative pulse switch that suppresses pulses in the negative direction with respect to input pulses. Also,
The latter does not malfunction when used as a positive pulse switch that suppresses pulses in the positive direction of input pulses.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. M
1 is an n-channel MOS transistor whose source and body are connected; an input signal voltage Vws is applied to the source side and an output signal voltage V00 is taken out from the drain side. Mz is an n-channel MOS transistor, which is used as a current sucking element when Ml is forcibly turned off.

Dl is a diode used as gate protection for Ml,
By using this, it is possible to set the voltage amplitude value of VrN and 700 to be higher than the gate breakdown voltage of M1.

Dl is preferably a Zener diode with a breakdown voltage of about 5 to 30V. Ri is a resistor used to suppress the current value of MS, and is unnecessary if power consumption due to the current flowing through My is not a problem.

FIG. 2 is a time chart showing a method of driving the circuit of FIG. 1. Since there is a parasitic diode between the drain and body of Ml with the drain as the cathode and the body as the anode, when input signal voltage VIN with amplitude VDH is applied, when VIN is in a high voltage state, it will be in the state of control signal voltage Vc. Regardless of this, the output signal voltage VOUT also becomes a high voltage state.

When Vrs falls, if VC is in a low voltage state (Mz is off), the voltage of Vx tries to be held, so M
l is turned on, and V OUT also falls. However, when VIN falls, when Vc is in a high voltage state (Mx is on), Ml is forced to turn off, so V
out maintains a nearly high voltage state. Therefore, it is possible to control whether to conduct or cut off Vrs and VOUT depending on the value of Vc, and it functions as a switch circuit that suppresses negative direction pulses with respect to human input pulses input to Vrw.

FIG. 3 is also a time chart showing a method of driving the circuit of FIG. 1. In this driving method, Vc is brought into a high voltage state in synchronization with the fall of VIN only during a period when it is not desired to fall Moυ. Thereby, the reactive current flowing through Mz due to the control signal voltage Vc can be reduced, and the power consumption of the circuit can be reduced.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, a capacitor C1 is added between the Vx section of the circuit of the first embodiment and the high power supply voltage VH, so that when Mz is off, V
Made it easier for Ml to turn on when rs falls. In this embodiment, the capacitor C1 is placed between the Vx section and the high power supply voltage, but the same effect can be obtained even if it is placed between the Vx section and the ground or VC section.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.
In this embodiment, a diode Dz is added in series with and in the opposite direction to the diode Dz in the circuit of the first embodiment. Therefore, even when the driving method shown in FIG. 2 is used, it is possible to eliminate the reactive current flowing through Mz when Vc is in a high voltage state.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

In this embodiment, a resistor R2 is used in place of the diode D1 in the circuit of the first embodiment.

For example, when a polysilicon resistor is used as R2, it is possible to reduce the area and parasitic capacitance compared to a diode. However, if the value of resistor R2 is too large, it will not be useful as a gate protector for Ml, and if it is too small, it will not be possible to turn on Mz when VIN falls, so be careful when setting the resistance value. It takes.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

In the first embodiment, when VrN falls, even if Vout is kept in a high voltage state, there is a voltage drop at VOUT of about 10% of the voltage amplitude of Vrs.

In this embodiment, in order to prevent this voltage drop and maintain the high voltage state, two p-channel MOS transistors M3.
Ml is connected in a current mirror manner, and the current of transistor M3 is controlled by n-channel MOS transistor M6.

The driving method of this circuit can be the same as in FIGS. 2 and 3 by connecting VCI and Vcz and using the control signal voltage Vc.

FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.
In this embodiment, a current mirror-connected p-channel MOS transistor M+s is used as a means for supplying current to the gate of M1 to turn it on.

Ml and an n-channel MOS transistor M for driving it.
δ is used. In this embodiment, when Mx is on, Vo
Since ut can be raised, the parasitic diode between the drain and body of Ml can be driven without being forward biased. Therefore, it is possible to prevent a reduction in the switching speed of Ml due to the accumulation of minority carriers. Furthermore, by setting the high power supply voltage VH higher than the highest voltage VDH of VIN, Mi can be set in the on state even when VIN is at a high potential, so that a small signal from Vrs can be sent to Voυ over a wide voltage range. Note that the P-channel MOS transistor MS and the n-channel MOS transistor Mio have an inverter configuration, and if Vcz and Vca are connected and the control signal voltage is Vc, the same driving method as in FIGS. 2 and 3 can be used. Can be done.

VL is a signal system power supply voltage.

FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention.
This embodiment has a configuration having the circuit functions shown in FIGS. 7 and 8. The high power supply voltages VHI and VIH2 may be set to the same potential, but by setting Vuz to about 5 to 20 V higher than VHI, it is also possible to set Ml to the on state when VrN is at a high potential. VC! 1 and Vcz and V
If ca is connected and this is set as the Va terminal, the driving method shown in FIGS. 2 and 3 can be used.

FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention. In this embodiment, the input signal voltage Vxu and the output signal voltage Vc
υ is also an effective switch circuit when used at a level below the gate withstand voltage.

FIG. 11 is a truth table for the circuit of FIG.

When the control signal voltages VCON and VIN are both in a low voltage state, V out maintains the previous state of V 0LIT.

FIG. 12 is a circuit diagram showing a ninth embodiment of the present invention. This embodiment is also an effective switch circuit when used at a level where VIN and VOυ are lower than the gate withstand voltage.

FIG. 13 is a truth table for the circuit of FIG. 12.

When both Vcos and VIH are in a low voltage state, p-channel MOS transistor M6 is turned on, so V
QIJT goes into a high voltage state.

FIG. 14 is a circuit diagram showing a tenth embodiment of the present invention. In this embodiment, the n-channel MOS transistor M1 used as a switch element in FIG. 1 is replaced with an npn transistor Q1 and a diode DQL, and the n-channel MOS
This is a switch circuit in which the S transistor M2 is replaced with an npn transistor Qz. As described above, in the circuits described in the embodiments so far, a circuit having the same function can be realized by replacing the MOS transistor Mt with a bipolar transistor having diodes connected in parallel.

FIG. 15 is a circuit diagram showing an eleventh embodiment of the present invention. The embodiments shown so far have shown switch circuits that are effective in suppressing pulses in the negative direction with respect to the reference voltage, but by replacing the polarity of the element with the reverse type, pulses in the positive direction with respect to the reference voltage In this embodiment, an effective switch circuit for suppressing pulses can be realized. In this embodiment, the n-channel MOS transistors used in the embodiment of FIG. A switch circuit is realized.

FIG. 16 is a circuit block diagram showing a twelfth embodiment of the present invention. In this embodiment, whether or not the pulses generated by the pulse generator are sent to two or more loads is determined by opening and closing the switch circuit SW according to the present invention. The opening and closing of the switch is performed based on the control signal voltage VC (ILVc (zL...Vc(N)) sent from the drive circuit.The drive circuit inputs data from the data input terminal into the shift register using a clock signal. It performs the function of transferring the voltage, performing serial-parallel conversion, synchronizing it with a latch signal, and simultaneously sending it to each switch circuit as a control signal voltage.

In addition, in FIG. 16, when the load is capacitive, the pulse generation circuit is replaced by a power recovery circuit (Japanese Patent Laid-Open No. 61-13299
No. 7). In this case, since the power sent from the pulse generator to the load is returned from the load to the pulse generator, a capacitive load drive device with low power consumption can be realized.

FIG. 17 is a circuit block diagram showing a thirteenth embodiment of the present invention. This embodiment describes a method for driving a matrix display device using the switch circuit of the present invention.

- As an example, an example is shown in which the present invention is applied to drive a display device described in Japanese Patent Application No. 113686/1986.

As shown in FIG. 17, the discharge cell has an anode and a cathode.

It is composed of three auxiliary anode electrodes, and the discharge between the anode and the cathode becomes a display discharge, whereas the discharge between the auxiliary anode and the cathode becomes an auxiliary discharge that is not observed from the outside. The cathode resistor RK is provided to prevent one-display discharge and auxiliary discharge from occurring at the same time. Anode voltage V^, cathode voltage V
Assuming that the auxiliary anode voltage is Vs^, the following procedure is required to perform one display discharge. That is, (1) Start auxiliary discharge by setting Vs* to a high potential tvt to a low potential.

(2) Set VSA to low potential yVg to low potential and V^ to high potential to stop auxiliary discharge and start display discharge.

If Vs^ remains at a high potential in step (2), even if V becomes a low potential and V^ becomes a high potential, the display discharge will not start because the auxiliary discharge will not stop.

By utilizing the characteristics of the discharge cells described above, using the positive pulse V^ and the negative pulse VK for the running signal, and using the negative pulse Vs^ for the image signal, any discharge cell on the display matrix can be displayed. display discharge can be performed. In the case of this embodiment, by using the pulse generator as a power recovery circuit, the power consumption of the anode drive circuit and the auxiliary anode drive circuit can be reduced compared to the conventional one. The switch circuit for the F&pole drive circuit is the drive circuit (A) with a built-in positive pulse switch circuit as shown in Figure 15, and the switch circuit for the auxiliary anode drive circuit is the one shown in Figure 1 etc. A drive circuit with a built-in negative pulse switch circuit as shown (B
) and a conventional push-pull type drive circuit (C) for cathode drive, a display device capable of driving with low power consumption can be realized. The driving method described in this embodiment is applicable to capacitive load driving devices such as general plasma displays, EL (electroluminescent) displays, fluorescent display tube displays, and piezoelectric elements.

〔Effect of the invention〕

According to the present invention, it is possible to create a switch circuit that can handle high voltage signals with a simple configuration, and when driving a capacitive load in particular, by using it in conjunction with a power recovery circuit, consumption is reduced compared to driving methods using normal complementary circuits. This has the effect of reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a switch circuit diagram of the first embodiment of the present invention;
3 and 3 are time charts showing a method of driving a switch circuit according to the present invention, and FIGS. 4 to 10 are switch circuit diagrams of other embodiments of the present invention. Figure 11 is the truth table for the switch circuit in Figure 10, and Figure 12 is the truth table for the switch circuit in Figure 10.
The figure is a switch circuit diagram of still another embodiment of the present invention.
Figure 3 shows the truth table for the switch circuit in Figure 12, Figure 14,
FIG. 15 is a switch circuit diagram of still another embodiment of the invention, and FIG. 16 is a block diagram of a switch circuit of still another embodiment of the invention. FIG. 17 is a block diagram of a display device according to an embodiment of the present invention. Mt, Mx, M5. MI M engineering on-channel MO5h
Ransistor, M4. M8. M71 MI, M
□□. M1! ...p-channel Os transistor, Ql, Q
2... npn transistor, Dz, D2. Dtt
, DQt-diode, Rz, Rz, Rzt...
・Resistance, Cs...Capacitor, 'V''r*...Human signal voltage, VO(IT...Output signal voltage, Vc+
Vczt Vczt Vca+ Vcos-control signal voltage, ■H2■H1, vH2...High power supply voltage, V oo
・= Mll electric voltage ■...Signal system power supply voltage. Taku Kaitakuzu "DL-- W Ya Control 4 Poetry Denshi Diagram B■ M + 71 + Yaru M and Torshafu Dz f4 -
)'“Hub! 7 jqXLMIS) Kunshidzuku &1
9 anti-p gain r-t g2 N
Shift VpL--=--= diodes 1 input n 4t-5 each raised 1E (/, I high voltage electric counter M57 manual attack hνδtokux! 7++4 channel n's) run star N+I' Now - Haru t
I super torque 7r chare NθS torque 1jV
tapr 814) p4 @ '% 'l pressure! Figure of illustration

Claims (1)

[Claims] 1. The source and body of a MOS transistor are connected, and this is used as a signal input terminal, and the drain is used as a signal output terminal,
A switch circuit characterized by using a gate as a control terminal. 2. Claim 1, characterized in that a diode is provided between the gate and source of the MOS transistor, and means for forcibly turning off the MOS transistor by a first active element connected to the gate of the MOS transistor is provided. Switch circuit described in section. 3. A second transistor connected to the gate of the MOS transistor
3. The switch circuit according to claim 1, further comprising means for forcibly turning on the active element. 4. When the switch circuit is in a closed state, even if the voltage at the signal input terminal fluctuates, means is provided for holding the output voltage so that the voltage fluctuation at the signal output terminal is reduced. The switch circuit according to items 3 to 3. 5. The switch circuit according to claim 1, further comprising two or more diodes connected in opposite directions between the gate and source of the MOS transistor. 6. The switch circuit according to claim 1, wherein a resistor is provided between the gate and source of the MOS transistor instead of a diode. 7. The switch circuit according to claim 1, wherein there is a period during which the diode provided between the drain and body of the MOS transistor is forward biased during operation of the switch circuit. 8. Instead of the MOS transistor, bipolar
7. The switch circuit according to claim 1, wherein the switch circuit is realized by connecting a transistor and a diode in parallel. 9. The switch circuit according to claim 1, wherein the voltage waveform input to the signal input terminal is a large amplitude pulse waveform. 10. Driving the switch circuit according to claims 1 to 9, characterized in that the signal sent to the control terminal is applied in synchronization with the voltage transition period of the signal sent to the input terminal. Method. 11. The switch circuit according to claims 1 to 8
The signal sent to the control terminal of each switch circuit is
A semiconductor integrated circuit device characterized in that the signal is transmitted from a signal processing circuit having a serial-to-parallel conversion function formed on the same chip. 12. The output terminal of the pulse generation circuit is connected to the signal input terminal of one or more switch circuits according to claims 1 to 9, and a load is connected to the signal output terminal of each switch circuit. A semiconductor circuit characterized by: 13. The capacitive load drive circuit device according to claim 12, wherein the pulse generation circuit is constituted by a power recovery circuit, and the power supplied to the capacitive load is recovered to the pulse generation circuit again. 14. A display device characterized in that the semiconductor circuit according to claim 12 or claim 13 is used for driving a display element.