JPH0266475A - Method for inspecting semiconductor element - Google Patents

Method for inspecting semiconductor element

Info

Publication number
JPH0266475A
JPH0266475A JP63216425A JP21642588A JPH0266475A JP H0266475 A JPH0266475 A JP H0266475A JP 63216425 A JP63216425 A JP 63216425A JP 21642588 A JP21642588 A JP 21642588A JP H0266475 A JPH0266475 A JP H0266475A
Authority
JP
Japan
Prior art keywords
pallet
information
inspection
stage
probe card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63216425A
Other languages
Japanese (ja)
Inventor
Riyuuichi Takebuchi
竹渕 隆一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP63216425A priority Critical patent/JPH0266475A/en
Publication of JPH0266475A publication Critical patent/JPH0266475A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the accuracy of inspection and yield without dropping through-put correspondingly to the sort of a semiconductor element by arranging plural ID information on the proper position of a pallet, arranging a positional information checking signal in the vicinity of the ID information and reading out the ID information or positional information on the pallet concerned. CONSTITUTION:An inspection stage 7 for mounting a pallet 2 storing many semiconductor elements 3 can be driven in the X, Y, Z, and theta directions by driving a motor. A probe card 8 is arranged on a position opposite to the stage 7 and the electric characteristics of the element 3 in the pallet 2 on the stage 7 is inspected by a probe stylus 9 of the probe card 8. A storage board 11 can be vertically moved in accordance with the movement of a supporting shaft 13 connected to the motor 7. In the case of executing an inspection, the pallet 2 is carried from the cassette to the stage 7 by a carrying mechanism and vacuum suction is executed on the stage 7. Then the information of an ID information setting mechanism 5 and a position checking hole 6 formed on a non-section part of the pallet 2 is detected by a proper detecting means shown in Fig.5 to position the pallet 2.

Description

【発明の詳細な説明】 発明の目的 (産業上の利用分野) 本発明は、区画されたパレットに半導体素子を複数収容
した状態で触針によりその電気的特性を検査する半導体
素子の検査方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device testing method for testing the electrical characteristics of a plurality of semiconductor devices housed in a partitioned pallet using a stylus. It is something.

(従来の技術) 従来、完成品のパッケージ工程後のICなど半導体素子
の電気的特性を検査するのには、一般にICハンドラが
使用されていた。このICハンドラは、筒状のマガジン
に1列に設定された複数のICを重力の作用及びオート
ローダ−機構によりハンドラ側面に設けられた検査部に
搬送・位置決めし、検査終了後、重力の作用及びオート
ローダ−機構により性能別に選別するものである。そこ
での半導体素子の位置決めは、筒状のマガジンを利用し
て重力の作用により端部位置合わせが半ば自動的になさ
れていた。
(Prior Art) Conventionally, an IC handler has generally been used to inspect the electrical characteristics of a semiconductor element such as an IC after the packaging process of a finished product. This IC handler transports and positions a plurality of ICs set in a row in a cylindrical magazine to an inspection section provided on the side of the handler using the action of gravity and an autoloader mechanism. It is sorted by performance using an autoloader mechanism. In order to position the semiconductor elements there, a cylindrical magazine was used, and end positioning was done semi-automatically by the action of gravity.

また、特開昭57−147247号公報のように、ハン
ドラによらずに、パッケージングされた半導体素子を区
画されたパレット上にロボットハンド等で多数収容し、
該半導体素子のパットの位置をカメラなどの光学的装置
等で自動認識して被検査半導体素子毎に−々X、Y、Z
、 θ方向の位置合わせし、プローバで電気的特性を検
査する方法も提案されている。
In addition, as in Japanese Patent Application Laid-open No. 57-147247, a large number of packaged semiconductor devices are accommodated on a partitioned pallet using a robot hand or the like, without using a handler.
The positions of the pads on the semiconductor device are automatically recognized using an optical device such as a camera, and the positions of the pads on each semiconductor device to be inspected are
, a method of aligning in the θ direction and inspecting the electrical characteristics with a prober has also been proposed.

(発明が解決しようとする課題) しかしながら、上記のようなICハンドラにおける搬送
・位置決め方法は、主として重力の作用に因っているた
め、機械的端部位置合わせ機構による搬送途中で半導体
素子が詰まったり、摩擦や故障などで半導体検査の歩留
まり悪(するという問題があった。また、このICハン
ドラでは、検査する半導体素子の品種に合わせて、筒状
マガジン及び検査部を合ったものに変える必要があって
手間がかかっていた。
(Problem to be Solved by the Invention) However, since the above-mentioned transport and positioning method in an IC handler mainly relies on the action of gravity, there is a problem that semiconductor elements may become jammed during transport by the mechanical end positioning mechanism. There was a problem that the yield rate of semiconductor inspection was poor due to friction, failure, etc. Also, with this IC handler, it was necessary to change the cylindrical magazine and inspection section to match the type of semiconductor element to be inspected. It took a lot of time and effort.

また、特開昭57−147247号公報のように、検査
時にプローバを用いて被検査半導体素子毎に−々X、Y
、Z、  θ方向の位置合わせを行う方法では、検査装
置のスループットが大幅にダウンすることは避けられず
、又、検査する半導体素子の品種に応じた対応が難しい
という問題があった。
In addition, as in Japanese Patent Application Laid-open No. 57-147247, a prober is used during testing to test each semiconductor device to be tested.
, Z, and θ directions, there is a problem in that the throughput of the inspection apparatus inevitably decreases significantly, and it is difficult to adapt the method to suit the type of semiconductor device to be inspected.

本発明は、上述の課題に鑑み発明されたもので、被検査
半導体素子を各区画に収容するパレットを正確に位置決
めし、半導体素子の品種に対応してスループットをダウ
ンさせることなく検査精度の向上と歩留まりの向上を図
る半導体素子の検査方法を提供することを目的とする。
The present invention was invented in view of the above-mentioned problems, and improves inspection accuracy by accurately positioning pallets that accommodate semiconductor devices to be tested in each compartment, and without reducing throughput in accordance with the types of semiconductor devices. It is an object of the present invention to provide a semiconductor device testing method that improves yield.

発明の越 (課題を解決するための手段) 本発明は、上述の課題を解決するため、パッケージング
された多数の半導体素子を区画されたパレットの定めら
れた位置に収容し触針によりその電気的特性を検査する
方法において、該パレットの適宜位置に、複数のID情
報及びその近傍に位置情報確認用信号を設け、当該パレ
ットのID情報ないし位置情報を読取って該パレット内
の半導体素子の検査を行う構成を採用した。
ADVANTAGES OF THE INVENTION (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention accommodates a large number of packaged semiconductor devices in a predetermined position on a partitioned pallet, and uses a stylus to conduct electricity. In this method, a plurality of pieces of ID information and a position information confirmation signal are provided at appropriate positions on the pallet, and a position information confirmation signal is provided in the vicinity thereof, and the ID information or position information of the pallet is read to inspect the semiconductor elements in the pallet. We adopted a configuration that performs the following.

(作用) パレットの適宜位置に設けた複数のID情報、位置情報
から、被検査体の位置や種別などを自動的に認識し、選
択された検査を可能ならしめた。
(Function) The position and type of the object to be inspected are automatically recognized from a plurality of pieces of ID information and position information provided at appropriate positions on the pallet, making it possible to carry out the selected inspection.

(実施例) 以下、本発明の一実施例について説明する。(Example) An embodiment of the present invention will be described below.

第1図は本実施例の検査方法で使用するパレットで、同
図(a)は概略斜視図、(b)はその収容部の部分拡大
斜視図、第2図は本実施例の検査方法で用いる検査装置
の全体概略を示す説明図である。
Figure 1 shows a pallet used in the inspection method of this embodiment, where (a) is a schematic perspective view, (b) is a partially enlarged perspective view of its storage section, and Figure 2 is a pallet used in the inspection method of this embodiment. It is an explanatory view showing the whole outline of the inspection device used.

第1図及び第2図において、1は検査装置本体、2は図
示しない半導体素子3(例えばチップをマウントしパッ
ケージングされたIC等)を多数収容するパレット、4
は該パレット2の区画された収容室で、この各収容室4
内に上記半導体素子3を各1個づつ収容する。一般には
、このパレット2は、例えば縦450+++m、横45
0mm、高さ10mmに構成され、被検査ICを収容す
るその収容室4は、例えば無区画部分である周縁より約
5m++aのところからLmm間隔をおいて縦20mm
、横10mm、高さ5mmの凹部として1パレット当り
21 X 40 = 840個形成される。
In FIGS. 1 and 2, reference numeral 1 denotes the main body of the inspection apparatus, 2 a pallet containing a large number of semiconductor elements 3 (for example, packaged ICs with chips mounted thereon, etc.), and 4
is a storage chamber into which the pallet 2 is divided, and each storage chamber 4
One each of the semiconductor elements 3 is housed inside. Generally, this pallet 2 is, for example, 450+++ meters long and 45 meters wide.
The storage chamber 4, which accommodates the IC to be tested, is 20 mm long at an interval of L mm from, for example, about 5 m++a from the periphery, which is an undivided portion.
, 21 x 40 = 840 recesses each having a width of 10 mm and a height of 5 mm are formed per pallet.

第1図(b)に示す通り、本実施例では、パレット2の
無区画部分(第1図(b)中表周縁部)に、複数のID
情報(例えば半導体素子の種別、ナス1〜内容、パレッ
ト番号など)設定用ホール5aとピン5bの組合せから
なるID情報設定機構5を設けるとともに、そのID情
報設定機構5をはさんで、位置情報1例えば被検査体の
位置を示す3個の位置情報確認用ホール6 (6a、6
b。
As shown in FIG. 1(b), in this embodiment, a plurality of ID
An ID information setting mechanism 5 consisting of a combination of a hole 5a and a pin 5b for setting information (for example, type of semiconductor element, content, pallet number, etc.) is provided, and position information is set across the ID information setting mechanism 5. 1 For example, three position information confirmation holes 6 (6a, 6
b.

6c)を1間隔を置いて直線上に位置するように設けて
いる。このID情報設定機構5と位置情報確認用ホール
6は、具体的には第3図(a)に示すように設けられて
いる。同図において、6a及び6cは位置情報確認用ホ
ール、5aは複数のID情報設定用ホール、6bは位置
情報確認用のダミーホール(実際に孔が開いていない)
である。
6c) are provided so as to be positioned on a straight line at one interval. The ID information setting mechanism 5 and the position information confirmation hole 6 are specifically provided as shown in FIG. 3(a). In the figure, 6a and 6c are holes for confirming location information, 5a is a hole for setting multiple ID information, and 6b is a dummy hole for confirming location information (no holes are actually opened).
It is.

上記ID情報設定用ホール5aには、第4図に概略的に
示すように、適宜のID番号設定用ビン5bが配置され
、その数及び組合せによりID情報を伝達するもので、
位置情報確認用ホール6a乃至6cを検出する際、パレ
ット2にその位置ずれかない場合に限って同時に当該I
D情報を読取るように構成されている。なお、この位置
情報確認用ホール6は、第3図(b)に示すように2個
としてもよく、少なくとも2個以上であれば、任意に増
減できる。
As schematically shown in FIG. 4, appropriate ID number setting bins 5b are arranged in the ID information setting hole 5a, and ID information is transmitted depending on the number and combination of the bins.
When detecting the position information confirmation holes 6a to 6c, only when the pallet 2 has no positional deviation, the corresponding I
It is configured to read D information. Note that the number of the position information confirmation holes 6 may be two as shown in FIG. 3(b), and the number can be increased or decreased as desired as long as it is at least two or more.

上記位置情報確認用ホール6a乃至6Cを第4+M(a
)に示す本実施例の検出機構により検出した場合の位:
1゛を情報については以下の第1表の通りである。
The above position information confirmation holes 6a to 6C are
) When detected by the detection mechanism of this example shown in
Information on 1゛ is as shown in Table 1 below.

第1表 本実施例においては、検出結果が上記■のときのみパレ
ット2が正確な位置にあるものとして■D情報を読取る
ようにしている。なお、上記位置情報は、ホールの数、
ホールの配列によって種々の機能を持たせるよう変える
ことができるのはいうまでもない。
Table 1 In this embodiment, the pallet 2 is assumed to be in an accurate position and the D information is read only when the detection result is the above. The above location information includes the number of holes,
It goes without saying that the arrangement of holes can be changed to provide various functions.

次に、本実施例の検査方法及びこれに用いる検査装置の
概要を第2図に従って説明する。半導体素子3を多数枚
収容するパレット2を載せる検査ステージ7は、モータ
駆動によりX方向、Y方向。
Next, an overview of the inspection method of this embodiment and the inspection apparatus used therein will be explained with reference to FIG. The inspection stage 7 on which the pallet 2 containing a large number of semiconductor devices 3 is placed is moved in the X and Y directions by motor drive.

Z方向、0方向の駆動が可能である。この検査ステージ
7の対向した位置には、プローブカード8が設けられ、
このプローブカード8のプローブ針9で、検査ステージ
7上のパレット2内の半導体素子3の電気的特性の検査
を行うものである。なお、第2図中、10は上記パレッ
ト2を複数枚収容したカセット、11はその収容台、1
2はモータで、収容台11はモータ7に連結した支持軸
13の動きにより上下動可能に構成されている。
Driving in the Z direction and 0 direction is possible. A probe card 8 is provided at a position facing the inspection stage 7.
The probe needles 9 of this probe card 8 are used to test the electrical characteristics of the semiconductor elements 3 in the pallet 2 on the test stage 7. In addition, in FIG. 2, 10 is a cassette containing a plurality of the above-mentioned pallets 2, 11 is a storage stand thereof, and 1
Reference numeral 2 denotes a motor, and the storage table 11 is configured to be movable up and down by the movement of a support shaft 13 connected to the motor 7.

この検査は、まず、カセット10から図示しない搬送機
構によりパレット2を検査ステージ7上に搬送し、検査
ステージ7で真空吸着する。次いで、パレット2の無区
画部分に形成した前記ID情報設定機構5及び位置確認
用ホール6の情報を、第5図に示すような適宜の検出手
段で検出し、パレット2の位置合わせを行う。ここで、
第5図は光学的な検出手段の一例で、発光部14と受光
センサからなる受光部15を具え光センサによりスキャ
ンして検出するものを示している。なお、特に図示しな
しが、探触ピンを具える検出部を下降させて、各ホール
6a、6cないしID情報設定用ホール5aに夫々差込
まれた所定のピンAいC1ないし5bとの接触により検
出するなどの他の検出手段を用いてもよく、この検出機
構は、実施に応じて任意の検出手段を選択できる。しか
して、本実施例ではこのように検出された位置情報に基
づき、検査ステージ7を図示しない駆動機構によりθ方
向に回転し、検査ステージ7のX方向、Y方向の駆動と
パレットのX方向、Y方向とを一致させて位置合わせを
行う。パレット2の位置合わせ後、検査ステージ7をプ
ローブカード8設定位置まで相対的に移動し、ここで検
査ステージ7をZ方向に上動させて、パレット2に配置
されている各半導体素子3の電極端子であるピン列とプ
ローブカード8のプローブ針9を接触させて、電気的特
性を検査する。この場合、先にID情報設定機構5から
読取った被検査半導体素子3の品種に対応して、テスタ
のプログラム、プローブカード8及び周辺回路の選択を
行なわれ、被検査半導体素子3に合わせた適切な検査が
実施される。
In this inspection, first, the pallet 2 is conveyed from the cassette 10 onto the inspection stage 7 by a conveyance mechanism (not shown), and vacuum suction is carried out on the inspection stage 7. Next, the information of the ID information setting mechanism 5 and the position confirmation hole 6 formed in the non-divided portion of the pallet 2 is detected by an appropriate detection means as shown in FIG. 5, and the pallet 2 is aligned. here,
FIG. 5 shows an example of an optical detection means, which includes a light emitting section 14 and a light receiving section 15 consisting of a light receiving sensor, and detects by scanning with an optical sensor. Although not shown in the drawings, the detection unit including the probe pin is lowered and comes into contact with the predetermined pins A, C1 to 5b inserted into the holes 6a, 6c or the ID information setting hole 5a, respectively. Other detection means, such as detection by , may be used, and any detection means can be selected depending on the implementation. In this embodiment, based on the position information detected in this way, the inspection stage 7 is rotated in the θ direction by a drive mechanism (not shown), and the inspection stage 7 is driven in the X and Y directions and the pallet is driven in the X and Y directions. Positioning is performed by matching the Y direction. After aligning the pallet 2, the inspection stage 7 is relatively moved to the probe card 8 setting position, and here the inspection stage 7 is moved upward in the Z direction to check the electrodes of each semiconductor element 3 arranged on the pallet 2. The pin array, which is a terminal, is brought into contact with the probe needles 9 of the probe card 8 to test the electrical characteristics. In this case, the tester program, probe card 8, and peripheral circuits are selected in accordance with the type of the semiconductor device 3 to be tested that has been read from the ID information setting mechanism 5, and the appropriate one is selected according to the semiconductor device 3 to be tested. A thorough inspection will be carried out.

次に、上記本実施例の作用について説明すると、パレッ
ト2周縁の無区画部分に設けた複数のID情報設定用ホ
ール5aとピン5bの組合せとからなるID情報設定機
構5は、そのピン5aの数、位置により当該パレット2
内の半導体素子3の品種など適宜のID+n報をパレッ
ト上に表す。しかも、この情報の検出は、直線上に並ん
だ位置確認用ホール6の検出を兼ねた検出機構で行うこ
とが可能である。また、このID情報設定用ホール5a
の近傍に、間隔を置いて設けた3個(うち1個はダミー
ホール)の位置情報確認用ホール6a。
Next, to explain the operation of the present embodiment, the ID information setting mechanism 5 is made up of a combination of a plurality of ID information setting holes 5a and pins 5b provided in the undivided portion of the periphery of the pallet 2. Depending on the number and location, the pallet 2
Appropriate ID+n information, such as the type of semiconductor element 3 within, is displayed on the palette. Moreover, this information can be detected by a detection mechanism that also serves to detect the position confirmation holes 6 arranged in a straight line. In addition, this ID information setting hole 5a
Three (one of which is a dummy hole) holes 6a for confirming position information are provided at intervals in the vicinity of the position information confirmation hole 6a.

6b、6cの位置を検出することで、当該パレットのX
、Y、0方向の位置情報を得ることができる。なお、位
置情報及びID情報の検出機構については、光学的検出
機構や機械的検出機構など様々な機構とし得る。
By detecting the positions of 6b and 6c,
, Y, and 0 directions can be obtained. Note that various mechanisms such as an optical detection mechanism and a mechanical detection mechanism may be used as the detection mechanism for the position information and ID information.

上記実施例では、パレットに情報を施した例について説
明したが、パレット内の各被検査体の設けられる位置に
当該情報を設けることにより、ASIC対応でパケット
内の多品種の測定が自動的に可能である。
In the above example, an example was explained in which information was provided on a pallet, but by providing the information at the position of each object to be inspected within the pallet, measurements of various types within a packet can be automatically performed with ASIC compatibility. It is possible.

^匪勿塾困 以上説明したところから明らかなように、本発明の検査
方法によれば、被検査半導体素子を各区画に収容するパ
レットを正確に位置決めでき、半導体素子の品種に対応
してスループットをダウンさせることなく検査精度の向
上と歩留まりの向上を図ることができるという効果があ
る。
As is clear from the above explanation, according to the testing method of the present invention, it is possible to accurately position the pallet that accommodates the semiconductor devices to be tested in each compartment, and the throughput can be adjusted according to the type of semiconductor device. This has the effect that it is possible to improve inspection accuracy and yield without degrading the process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本実施例の検査方法で使用するパレットで、同
図(a)は概略斜視図、(b)はその部分拡大図、第2
図は本実施例の検査方法で用いる検査装置の全体概略を
示す説明図、第3図はパレットに形成した位置確認用ホ
ールとID情報設定機構の一例を示す平面図で、同図(
a)は位置確認用ホールを3個としたもの、(b)は同
じく2個としたもの、第4図はID情報設定用ホール及
びピンを示す概略断面図、第5図は光学的検出機構の一
例を示す概略図である。 1・・・・検査装置本体、2・・・・パレット、3・・
・・半導体素子、4・・・・収容室、5・・・・ID情
報設定機構、5a・・・・ID情報設定用ホール、6a
、6b、6c・・・・位置確認用ホール、A1. C□
、5b・・・・ピン、7・・・・検査ステージ、8・・
・・プローブカード、9・・・・プローブ針。 第1図 第3図 (b) 第4図 第5図
Figure 1 shows a pallet used in the inspection method of this example, where (a) is a schematic perspective view, (b) is a partially enlarged view, and the second
The figure is an explanatory diagram showing the overall outline of the inspection device used in the inspection method of this embodiment, and Figure 3 is a plan view showing an example of the position confirmation hole formed in the pallet and the ID information setting mechanism.
(a) shows three holes for position confirmation, (b) shows two holes, Fig. 4 is a schematic cross-sectional view showing the holes and pins for setting ID information, and Fig. 5 shows an optical detection mechanism. It is a schematic diagram showing an example. 1...Inspection equipment body, 2...Pallet, 3...
...Semiconductor element, 4...Accommodation chamber, 5...ID information setting mechanism, 5a...ID information setting hall, 6a
, 6b, 6c... hole for position confirmation, A1. C□
, 5b...pin, 7...inspection stage, 8...
...Probe card, 9...Probe needle. Figure 1 Figure 3 (b) Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] パッケージングされた多数の半導体素子を区画されたパ
レットの定められた位置に収容し触針によりその電気的
特性を検査する方法において、該パレットの適宜位置に
、複数のID情報及びその近傍に位置情報確認用信号を
設け、当該パレットのID情報ないし位置情報を読取っ
て該パレット内の半導体素子の検査を行うことを特徴と
する半導体素子の検査方法。
A method in which a large number of packaged semiconductor devices are housed in predetermined positions on a partitioned pallet and their electrical characteristics are inspected using a stylus, in which a plurality of ID information and a plurality of ID information located in the vicinity are placed at appropriate positions on the pallet. 1. A method for testing semiconductor devices, comprising providing an information confirmation signal, reading ID information or position information of the pallet, and testing the semiconductor devices in the pallet.
JP63216425A 1988-09-01 1988-09-01 Method for inspecting semiconductor element Pending JPH0266475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63216425A JPH0266475A (en) 1988-09-01 1988-09-01 Method for inspecting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63216425A JPH0266475A (en) 1988-09-01 1988-09-01 Method for inspecting semiconductor element

Publications (1)

Publication Number Publication Date
JPH0266475A true JPH0266475A (en) 1990-03-06

Family

ID=16688364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63216425A Pending JPH0266475A (en) 1988-09-01 1988-09-01 Method for inspecting semiconductor element

Country Status (1)

Country Link
JP (1) JPH0266475A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05121532A (en) * 1990-05-16 1993-05-18 Mitsubishi Electric Corp Tray for mounting ic and handler device
WO2006004117A1 (en) * 2004-07-06 2006-01-12 Dainichi Can Co., Ltd. Marker clip for ic tray
JP2006341873A (en) * 2005-06-08 2006-12-21 Toshiba Corp Tray for electronic component, and method of identifying similar tray for electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165947A (en) * 1986-01-17 1987-07-22 Mitsubishi Electric Corp Conveying jig
JPS62266475A (en) * 1986-05-14 1987-11-19 Hitachi Hokkai Semiconductor Ltd Handler

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165947A (en) * 1986-01-17 1987-07-22 Mitsubishi Electric Corp Conveying jig
JPS62266475A (en) * 1986-05-14 1987-11-19 Hitachi Hokkai Semiconductor Ltd Handler

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05121532A (en) * 1990-05-16 1993-05-18 Mitsubishi Electric Corp Tray for mounting ic and handler device
WO2006004117A1 (en) * 2004-07-06 2006-01-12 Dainichi Can Co., Ltd. Marker clip for ic tray
JP2006341873A (en) * 2005-06-08 2006-12-21 Toshiba Corp Tray for electronic component, and method of identifying similar tray for electronic component

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