JPH0265547A - Signal transmission system - Google Patents

Abstract

PURPOSE:To reduce the data acquisition time after start collision of terminal equipments by allowing a central processing unit to detect signal collision due to start, designating a group estimated to which at least started terminal equipments are all belong and allowing each start terminal equipment to return a subsequent relevant group. CONSTITUTION:A current mode signal sent from a terminal equipment is received based on an output of a current detection circuit 12 and when the presence of terminal equipment collision is discriminated, a high-order group of a started terminal equipment is retrieved and a return signal from the terminal equipment to each synchronizing signal is received while sending a synchronizing signal SYNC at the prescribed period. In the case of cyclic processing, in which timing the return signal is detected is discriminated to decide the high-order group belonging to the starting terminal equipment. A terminal equipment 5 executes the relevant group return processing when the mode MOD is any of high-order, middle-order and low-order group retrieval modes. Thus, the central processing unit 1 can detects a terminal equipment 5 of which group is started.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a random signal transmission system in which a central processing unit and a plurality of terminal devices are connected by a pair of transmission lines, and in particular, the present invention relates to a random signal transmission system in which a central processing unit and a plurality of terminal devices are connected by a pair of transmission lines. The present invention relates to a signal transmission method suitable for remote control for monitoring and controlling loads connected to equipment.

[Prior art] In conventional random transmission, when activation of multiple terminal devices (slave devices) collides, each activated terminal waits for a time corresponding to the product aXt of its own address a and a certain unit time t. Restarting the system after doing so prevented another collision. However, with this method, terminals with large addresses often wait an unnecessary amount of time before restarting, which has the disadvantage that there is a delay in data acquisition on the central processing unit (base unit) side. .

Another possible method is that the central processing unit polls all terminals after detecting a collision, but this also has the disadvantage of requiring time.

[Problems to be Solved by the Invention] This invention was made in view of the problems in the conventional example described above, and aims to shorten the data acquisition time particularly after a terminal startup collision in a random signal transmission system. .

[Means for Solving the Problem] In order to achieve the above object, the present invention provides a signal transmission system in which a central processing unit and a plurality of terminal devices are connected to a pair of transmission lines. When signals collide due to activation, the central processing unit detects this collision and transmits a transmission signal including a mode signal indicating a group reporting request from the activated terminal, and each activated terminal responds to this transmission signal. The central processing unit then outputs a return signal with a timing corresponding to the classification to which the self-address belongs or a pulse width corresponding to this belonging classification, and the central processing unit determines the group to which the initiating terminal belongs based on the return signal, and performs this operation. The method is characterized in that the address of the activated terminal device is detected by performing multiple classifications from the upper group classification to the lower group classification, and the activated terminal device is accessed to obtain terminal data such as monitoring data.

[Operation] According to the present invention having the above configuration, the central processing unit detects a signal collision caused by activation, and then specifies at least a group to which all activated terminal devices are presumed to belong, and assigns each activated terminal device to a group. to send back the lower belonging group within the designated group at the sending timing or pulse width of the return signal.

- To explain with an example, the central processing unit first specifies all the terminals and causes each terminal to send out a return signal at a timing or pulse width according to the value of the upper three bits of its own address. Once the upper 3 bits are determined by this return signal, the terminal group corresponding to the determined value of the upper 3 bits is designated and the value of the middle 3 bits of the 4th to 6th bits is reported. By repeating such polling multiple times, the address of the activated terminal is detected. When detected, the activated terminal is accessed and terminal data such as monitoring data is transmitted.

[Effect] Therefore, according to the present invention, in the above case, when the number of terminals is set to 512 with 9 bits, one of the activated terminals can be detected by polling three times. In this way, the address of the activated terminal device that collided with the random transmission can be detected in a short time at the pole, and the time for obtaining data after the terminal activation collision is shortened.

Furthermore, since collision detection and polling are performed on the central processing unit side, each terminal device does not need to detect signal collisions on transmission lines.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a schematic configuration of a remote control device according to a first embodiment of the present invention. The device in the figure includes a central processing unit 1 as a parent unit, and a plurality of terminal units 5 (5-1) as slave units connected to the central processing unit 1 via a pair of transmission lines 3.
, 5-2, 5-3, . . . ) and a monitoring display panel 7. Each terminal 5-1゜5-2. 5-3. ...
are connected to loads (not shown), such as lighting fixtures, wall switches, illuminance sensors, etc., respectively.

Such a device configuration is known as a remote control device, for example, as shown in Japanese Patent Publication No. 61-3155.
For example, when a central processing unit and a plurality of terminal devices are connected by a pair of transmission lines, as shown in FIG. /CNT and a long pulse RTM for a monitoring signal, and in each terminal, a series circuit of an appropriate current-limiting resistor and a switch element is connected in parallel to the transmission line during the transmission period of the long pulse for a monitoring signal. The switch element is opened and closed according to the monitored content, and the central processing unit detects a current change RPI in the transmission line due to this opening and closing operation.

By the way, when transmitting signals from the terminal to the central processing unit in a current mode that changes the current sinking at the terminal, as in this conventional remote control device (hereinafter referred to as the conventional system), the central processing unit detects Current can be converted into voltage using a resistor or the like and detected. However, since this signal current flows only between the sending terminal device and the central processing unit, this monitoring signal etc. cannot be detected at a position other than between the sending terminal device and the central processing unit.

Therefore, in this conventional system, each terminal device can only detect the signal of the terminal device in the later stage, and it is not possible to detect the signals of all other terminal devices, so it is activated from the terminal device by random transmission. When attempting to transmit (child activation), the activated terminal cannot determine whether there is a signal sent from the previous terminal, that is, whether the transmission line is occupied or a signal collision occurs, and random transmission cannot be performed. Not suitable.

This first embodiment is an improvement on this conventional system, in which the central processing unit 11 detects changes in the current mode signal sent from the terminal, and responds to changes in the current mode signal on the transmission line in accordance with the changes in the signal. By inverting the voltage mode, the current mode signal from the terminal device is converted to a voltage mode signal so that all the terminal devices can detect the output signal of the other terminal device as a voltage.

FIG. 2 shows a functional block configuration of the central processing unit 1. As shown in FIG.

This central processing unit 1 has a collision detection circuit 14, a differentiation circuit 15, and a collision detection circuit 14, a differentiating circuit 15, in contrast to the central processing unit of a conventional system consisting of a signal processing circuit 11, a current detection circuit 12, and a drive circuit 13.
, synchronous signal generation circuit 17 and flip-flop circuit 1
9 is added. The central processing unit 1 is further provided with a keyboard and switches or sensors for data input, and a display device for various displays, such as a CRT, as required.

The signal processing circuit 11 takes in data from the keyboard, switches, sensors, etc. according to a predetermined sequence, collects monitoring data from each terminal, creates control signals based on this data, and sends data to the display device. indicate. Also, a transmission voltage signal consisting of this control signal and the like is created. In the central processing unit of the conventional system,
This voltage signal is input as is to the drive circuit 13,
Since it was sent to the transmission line 3 as a transmission signal, the format of this transmission voltage signal is the same as that shown in FIG. 3(a), which is the transmission signal format from the central processing unit in the conventional system.

Referring to FIG. 3(a), this transmission voltage signal, that is, the transmission signal in the conventional system, consists of a start signal ST consisting of a long pulse signal of 12 levels, and an The transmission signal ADH/CNT consists of a group of short-level pulses and indicates transmission data such as the address ADH and control signal CNT of the destination terminal, and the long pulse signal of "1" level, which transmits monitoring data etc. from the destination terminal. It consists of a return period signal RTM, etc. indicating the return waiting period (or terminal transmission section). Said transmission signal AD
H/CNT is connected to each successive "1" level part and "O" level part in sequence.
Each "level part represents 1 bit of data, and a short 1" or "0° level part indicates data "0°, and a long one indicates data "1." In the example of FIG. 3(a), the signal ADH/CNT is “001.
"..." is shown.

Returning to FIG. 2, the current detection circuit 12 detects the current flowing between the central processing unit 1 and the terminal device via the transmission line 3 (current such as monitoring data as shown by diagonal lines in FIG. 3(a)). mode signal) into voltage.

The drive circuit 13 drives the transmission line 3 with a bipolar signal according to the input signal. For example, if the input signal is at the '1' level, it pulls up the transmission line to +24V, and if the input signal is at the '0# level, it pulls up the transmission line 3. In the central processing unit of the conventional system, the signal voltage output from the signal processing circuit 11 is inputted directly to the drive circuit 13, but in this embodiment, as shown in FIG. The signal ST and the transmission signal ADH/CNT are sent out as they are, but the return period signal RTM outputted from the signal processing circuit 11 during the return period is appropriately processed by the flip-flop circuit 19 before being sent out. The drive circuit 19 and the drive circuit 13 constitute a transmitting circuit 20 of the central processing unit of this embodiment.

The collision detection circuit 14 detects the presence or absence of a terminal collision based on the current value and current waveform detected by the current detection circuit 12.

The differentiating circuit 15 detects changes in the current mode signal sent from the terminal by differentiating the output voltage of the current detecting circuit 12.

The synchronization signal generation circuit 18 generates the synchronization signal 5YNC at a predetermined period only during the signal transmission period (terminal transmission period) RTM from the terminal device to the central processing unit.

The flip-flop (F/F) circuit 19 has a voltage output that rises at the rise of the voltage signal output from the signal processing circuit 11 and the synchronization signal 5YNC output from the synchronization signal generation circuit 17, and falls at the fall of the voltage signal output from the signal processing circuit 11. The output is inverted using the differential output of the differentiating circuit 15 as a trigger. That is, the flip-flop circuit 19 sends a voltage that changes according to changes in the output of the signal processing circuit 11 and the synchronizing signal generation circuit 17 to the drive circuit 13, and when the output of the signal processing circuit 11 is constant, the voltage is detected by the current detection circuit 12. A voltage that is inverted each time the current mode signal changes is sent to the drive circuit 13.

The drive circuit 13 drives the transmission line 3 according to the output voltage of the flip-flop circuit 19, so that the third
As shown in FIGS. 3(a) and 3(b), the start signal ST and the transmission signal ADH/CNT are transmitted to the signal processing device 1.
A voltage mode signal having the same shape as the output waveform from 1 is sent to the transmission line 3, and in the terminal transmission section RTM, a synchronization signal 5YNC is sent from the central processing unit, and the terminal When a current mode signal RPI is sent from the transmission line 3, a voltage mode signal RPV corresponding to this signal RPI is sent to the transmission line 3.

That is, in the transmission system of FIG. 1, during the terminal transmission period RTM, a current mode signal from the terminal device 5 is converted into a voltage mode signal by the central processing unit 1 and sent to the transmission line 3. Therefore, all the terminals and the monitoring display panel 7 use this voltage mode signal to control not only the terminals connected later than themselves, but also the current mode signals from the terminals connected earlier. Contents can be determined. Therefore, in this system, the monitoring display panel 7 can be connected to any location on the transmission line 3. In addition, since each terminal device can determine the signal transmission state of all terminal devices using this voltage mode signal, it can determine by itself the degree of clearance of the transmission line 3 and the presence or absence of signal collision. Therefore, according to this system, it is possible to realize a random transmission method that takes advantage of the characteristics of fewer collisions and faster transmission speed inherent in the random method, without increasing the burden on the central processing unit. Furthermore, when each terminal device sends out a current mode signal, the central processing unit determines whether the current mode signal is received or accepted by the central processing unit by determining the voltage mode signal converted from the current mode signal. You can confirm that. Therefore, there is no need for an answer signal from the central processing unit, and the transmission speed can be increased regardless of the transmission method.

FIG. 4 shows terminal 'j55 in the transmission system of FIG.
The functional block diagram is shown below. This terminal device 5 has a synchronizing signal detection circuit 55, a flip-flop circuit
7 is added. Further, one or more loads 9 are connected to the signal processing circuit 51 .

The receiving circuit 52 receives the voltage mode signal sent to the transmission line 3 from the central processing unit tl. The signal processing circuit 51 operates according to a predetermined sequence, receives and receives a control signal, etc. included in the voltage mode signal received by the receiving circuit 52, and supplies a load drive signal to the load 9 based on this control signal, etc. Alternatively, if the load 9 is a monitoring load, the monitoring signal is detected to create monitoring data, and this monitoring data is output to the transmitting circuit 53 in accordance with the control signal and the like. Transmission circuit 53
connects a resistor between the transmission lines in accordance with the monitoring data output from the signal processing circuit 51, and changes the sink current value in the second terminal device 5. As a result, the monitoring data is sent to the transmission line 3 as a current mode signal. When the output impedance of the drive circuit 13 of the central processing unit is low, there is almost no change in the line voltage of the transmission line 3 due to this current mode signal, but the shaded area RPI in FIG. 3(a) is
This current mode signal is schematically shown.

The synchronizing signal detection circuit 55 is for detecting a voltage mode synchronizing signal sent from the central processing unit 1 to the transmission line 3 based on the output of the receiving circuit 52, and the flip-flop circuit 57 is a signal processing circuit. This is for latching the output of 51.

Figure 5 shows the monitoring display panel 7 in the transmission system of Figure 1.
The functional block diagram is shown below. The monitoring display panel 7 includes a signal processing circuit 71, a receiving circuit 72, a display section 73, and the like.

The receiving circuit 72 receives the voltage mode signal sent from the central processing unit 1 to the transmission line 3. The signal processing circuit 71 operates according to a predetermined sequence, and based on the output of the receiving circuit 72, determines monitoring data etc. from the voltage mode signal obtained by converting the current mode signal sent from the terminal device by the central processing unit, A display signal corresponding to this monitoring data is sent to the display section 73. The display section 73 includes an LED, a lamp, and an L
It consists of display elements such as an ED array, LCD, or CRT, and a drive circuit for driving these display elements, and blinks these display elements to indicate the status of the load, etc. according to display signals input from the signal processing circuit 71. , or by displaying lines, figures, characters, etc. on these display elements.

FIG. 6 shows a specific circuit example of the central processing unit 1 in the transmission system of FIG.

The central processing unit in the figure is a microprocessor (CPU)
The signal processing circuit 11, the collision detection circuit 14, and the collision detection circuit 14 shown in FIG.
Functions corresponding to the differentiating circuit 15, the synchronizing signal generating circuit 18, and the flip-flop circuit 19 are realized by the operation program of the CPU 21.

The central processing unit in the figure further includes an A/D converter 22 for converting the analog output of the current detection circuit 12 into digital data that can be processed by the CPU 21, and an A/D converter 22 for converting the analog output of the current detection circuit 12 into digital data that can be processed by the CPU 21. +26V of
A DC power supply 23 that generates a DC voltage of -24V and +5V for circuits other than this output stage, a zero-cross detection circuit 24 that detects zero-crossing of the AC power supply, and a zero-crossing signal sending circuit for sending a zero-crossing signal to the transmission line 3. 25
, an oscillation circuit 26 that generates a drive clock for the CPU 21,
Reset circuit 2 for setting the CPU 21 to the initial state
It is equipped with 7.

When sending a transmission signal from the central processing unit to the terminal device, C
The PU 21 supplies the drive circuit 13 with a voltage signal having a waveform similar to that shown in FIG. 3, except that the "0" level is Ov and the "1" level is 5V. The drive circuit 13 is a CPU 2
According to the voltage signal from 1, the “0# level is 122V,
A voltage mode signal having a waveform as shown in FIG. 3 and having a voltage of +24 V is sent to the transmission line 3.

The zero cross detection circuit 24 detects the zero cross of the AC power supply and inputs a zero cross signal of '1 level to the CPU 21. In this detection circuit 24, for example, ACloo
AC power of V is supplied to the diode bridge DBI via the isolation transformer TI, and the diode bridge DBI
By applying the full-wave rectified output from the transistor Trl to the base of the transistor Trl and performing ultra-class C amplification, when this full-wave rectified output is OV, that is, at the timing of the zero-crossing of the AC power supply, a 5V zero-crossing is applied to the collector of the transistor Trl. Generate a signal.

The CPU 21 supplies this zero-crossing signal as it is to the zero-crossing signal transmitting circuit 25 when necessary, such as during central activation. In the zero-crossing signal transmission circuit 25, when the zero-crossing signal is input, the analog switch ASI turns off to cut off the voltage signal supply from the CPU 21 to the drive circuit 13, thereby cutting off the signal transmission from the central processing unit to the terminal device. , the photocoupler Pct is driven by a zero-cross signal from the CPU 21 to short-circuit the AC terminals of the diode bridge DB2, thereby short-circuiting the transmission lines 3. As a result, a zero-cross signal of voltage 0 as shown in FIG. 13 is transmitted to the terminal device.

Conventionally, this zero-crossing signal was created in the terminal device, but if it were created in the central processing unit and transmitted to each terminal device, one zero-crossing detection circuit would be sufficient, and each terminal device would have a zero-crossing detection circuit. The circuit configuration can be simplified and the cost can be reduced from the viewpoint of the entire system, compared to the case where the circuit is provided in the circuit.

FIG. 7 shows a specific circuit example of the terminal device 5 in the transmission system of FIG. 1.

The terminal shown in the figure is configured so that its entire operation is controlled by a microprocessor (CPU) 61.
The functions corresponding to the signal processing circuit 51, synchronous signal detection circuit 55, and flip-flop circuit 57 in FIG.
This is realized by the operation program No. 1. 52 and 53 are a receiving circuit and a transmitting circuit, respectively, which are common to those shown in FIG.

Further, 62 is a zero-cross signal receiving circuit, 63 is a self-address setting circuit, 64 is a DC power supply that generates a 5V DC output from an AC power supply, and 65 is a clock generation circuit. Further, C51 is a capacitor for resetting the CPU 61 when the terminal is powered on, and D B 51 is a bipolar (AC) system transmission line 3, a unipolar (DC) system transmission circuit 52, and zero-cross signal reception. This is a diode bridge for matching with the circuit 55.

Various load devices can be connected to this terminal unit, either singly or in various combinations, as required.Here, 91 is a load device that does not require a zero-cross signal, and 92 is a load device that requires a zero-cross signal. The optical device is further illustrated as a switch 93 which is a monitoring load. Note that in each of the load devices 91 and 92, only the load drive section is shown.

The receiving circuit 52 generates signals of 0 and 5 V depending on whether the voltage mode of the transmission line 3 is "0" or "1°," respectively, and supplies them to the CPU 61.

The transmission circuit 53 is supplied with a transmission signal from the terminal device created by the CPU 61 to the central processing unit, and this transmission signal is “
1", a resistor R51 is connected between the lines of the transmission line 3. At this time, the resistor R51 becomes a current sink, and the resistor R51
The current flowing through the transmission line 3 changes the current RPI flowing through the transmission line 3 as shown by the diagonal lines in Figure 3(a), and this is detected by the current detection circuit 12 (Figure 2) of the central processing unit and is transmitted from the terminal device. Current mode signal transmission to the central processing unit takes place.

As shown in FIG. 13, the line voltage of the transmission line 3 is 0 only when a zero-cross signal is sent from the central processing unit, and is otherwise +24V or -22V. In other words, the DC terminal voltage of diode bridge DB51 becomes 0 only when a zero-cross signal is sent, and is approximately +24V at other times.
Or +22V. The zero cross signal receiving circuit 55 adjusts the DC terminal voltage of this diode bridge DB51 to about 1
This is a voltage dividing resistor circuit that divides the voltage into 15.

When the output of the zero-cross signal receiving circuit 62 changes from approximately 5V to 0, the CPU 61 detects it as a large zero-cross signal. Then, every half cycle of the AC power supply, a 5V pulse is created with a phase angle based on this zero-cross signal and the control signal transmitted from the central processing unit, and is supplied to the dimming device 92. As a result, in the light control device 92, the triac T
Z is turned on at a conduction angle specified by the control signal, and a lamp, which is a load (not shown), is dimmed and lit.

On the other hand, when the switch 5W93 is operated in the monitoring load 93, the CF'U 61 detects this and creates monitoring data indicating its on/off state. This monitoring data is sent to the central processing unit in current mode as described above.

Figure 8 shows the monitoring display panel 7 in the transmission system of Figure 1.
A specific circuit example is shown below.

In the figure, 71 is a microprocessor (CPU), 72 and 73 corresponding to the signal processing circuit 71 in FIG.
are the receiving circuit and display section common to those shown in FIG. 5, respectively.

Further, 75 is a DC power supply that generates a 5V DC output from an AC power supply, 76 is a clock generation circuit, and C71 is a capacitor for resetting the CPU 71 when the monitor display device is powered on.

The reception circuit 72 generates reception signals of O and 5V depending on whether the voltage mode of the transmission line 3 is "O" or "1", respectively, and supplies them to the CPU 71. The display section 73 is
It is composed of display elements (light emitting diodes) LED71 to 7o corresponding to the output terminals 0UT71 to 7n of the CPU 71, and transistors Tr71 to 7n for driving them, etc., and the CPU 71 drives it at 5V based on the received signal. When the transistor Tr7x connected to the output terminal 0UT7x that generated the signal is turned on, the LED 7x lights up and a display is made.

Next, while referring to the flowcharts in Figures 9 to 12,
The operation of the system having the configuration shown in FIG. 1 and FIGS. 6 to 8 will be explained.

When the central processing unit 1, the terminal device 5, and the monitoring display panel 7 are powered on, they start operating according to a control program built into each CPU. First, after initializing various memories, flags, registers, etc. built into the CPU, the central processing unit 1 is operated as shown in the flowchart of FIG. 9, the terminal unit 5 is operated as shown in the flowchart of FIG. Each infinite loop process shown in the flowchart of FIG. 11 is executed.

As shown in FIG. 13, these infinite loop processes are executed based on a start signal sent from the central processing unit 1 every half cycle or every cycle of the AC power supply according to the zero cross of the AC power supply.

A. Operation of the Central Processing Unit Referring to FIG. 9, the central processing unit 1 first determines the presence or absence of activation data in step 102.

If there is data to be sent to the terminal, that is, activation data, central activation (parent activation) processing in steps 104 to 114 is executed. If there is no activation data, a start signal for activating the terminal as shown in FIG. 13(1) is sent out in step 120, and then it is determined in step 122 whether or not the terminal is activated. If the terminal is not activated, the process returns to step 102 and waits for the next transmission timing. On the other hand, if activation of the terminal is detected in step 122, it is determined in step 124 whether there is a terminal collision. If there is no collision, step 126
The normal mode processing of steps 128 to 128 is executed, and if there is a conflict, the activated terminal search processing of steps 130 to 170 is executed.

Central startup processing At the time of central startup processing, first, in step 104, a start signal ST, a destination terminal device address ADR, and a control signal as shown in FIG. (Startup data) Transmission data consisting of CNT, etc. is sent from the drive circuit 13 to the transmission line 3 in voltage mode. This transmission data is sent out one bit each time the process of step 104 is passed through. The next step 106 is a step for determining whether or not the process of step 104 has been repeated a predetermined number of times corresponding to the number of bits of the transmission data. Step 10
Return to 4. When the process in step 104 is repeated a predetermined number of times and a voltage mode signal of a predetermined number of bits is transmitted, it is determined in step 106 that the transmission has ended, and the process is continued to the next step 1.
Proceed to 08.

In step 108, a current mode signal sent from the terminal device is received based on the output of the current detection circuit 12. Then, changes in this current mode signal are detected and the output voltage mode of the drive circuit 13 is inverted every time there is a change. As a result, the current mode signal sent from the terminal device is converted into voltage mode signal by the central processing unit and sent out to the transmission line 3, and each terminal device and monitoring display panel can be connected to other terminal devices regardless of their connection position. It is possible to determine the signals sent from the

In step 110, it is determined whether the return has been completed.

In this central processing unit, one bit of return data is transmitted each time the transmission signal reception process of step 108 is executed. Therefore, if the process in step 108 has been repeated a predetermined number of times corresponding to the number of bits of the returned data, it is determined in step 110 that the return has ended;
Processing proceeds to step 112. On the other hand, step lO8
If the number of times of processing has not reached the number of bits of the return data, the return has not yet been completed, and the processing is continued at step 10.
Return to 8.

In step 112, it is determined whether the return data received in step 118 is acceptable. For example, if the destination terminal device returns data with the same content as the control signal CNT as an acknowledgment ACK, this acknowledgment ACK and control signal CNT
It can be determined whether the control data CNT has been normally received by the destination terminal device by comparing the CNT and CNT.

If the returned data is normal, it means that the transmission of the control data etc. was carried out normally, so after canceling the start-up by clearing the start-up data in step 114, step 102
Return to

On the other hand, if the returned data is abnormal, step 114 is skipped and the process returns directly from step 112 to step 102. In this case, the startup data remains as is, so
At the next transmission timing, it is determined in step 102 that activation data is present, and this central activation process is executed again. That is, this central activation process is repeated until the activation data is successfully transmitted.

There is no startup data in normal mode processing step 102, and step 120
If it is detected in step 122 that the terminal device has been activated in response to the start signal for terminal activation transmitted in step 122, and if there is no collision of the terminals in step 124, the process proceeds to step 126.
A normal mode process consisting of a circular process of step 128 and step 128 is executed.

In step 126, a terminal data signal, which is a current mode signal sent from the terminal, ie, one bit of terminal data is received. When the process of step 126 is repeated the same number of times as the number of bits of the terminal data, it is determined in step 128 that signal reception is complete, and the process is continued in step 1.
Return to 02.

Activation terminal search process If it is determined that there is a terminal collision in step 124 before shifting to the normal mode process, steps 130 to 170
Execute the startup terminal search process.

First, in step 130, the upper group (
For example, it is determined whether or not the address of the upper 3 bits should be searched. If a search is to be performed, the cyclic processing of steps 132 and 134 is performed to search for the search result as shown in FIG.
Start signal ST.

mode data MOD indicating that it is a higher search mode;
and a dummy address ADR that does not specify the other party, and transmits data one bit at a time.

Subsequently, in the cyclic process of steps 136 and 138, the synchronization signal 5YNC is sent out at a predetermined cycle, while
Receive return signals from the terminal in response to each synchronization signal.

When the process in step 136 is repeated the same number of times as the number of upper-level groups, it is determined in step 138 that the return has been completed, and the process proceeds to step 140.

In step 140, it is determined at which timing the return signal was detected during the cyclic processing of steps 136 and 138. As a result, the upper group to which the activation terminal belongs is determined. When the process of step 140 is completed, the process returns to step 130.

This time, the top groups have been searched, so step 1
The determination at step 30 is rNOJ, and the process proceeds to step 142.

In this step 142, the determination is rYESJ, and when searching for the middle group, the mode MOD of the transmission data becomes the middle search mode, and the upper address portion of the dummy address is replaced with the upper address determined by the upper search. Otherwise, the same processing as the upper search processing in steps 132 to 140 is executed.

Once the top and middle groups are determined, step 13
The determinations in step 142 and 142 are both rNOJ, and the process proceeds to step 154. In step 154, data consisting of the start signal ST, lower search mode data MOD, and address data ADR in which the upper and middle digits are the determined addresses and the lower dummy addresses are 1
Send bit by bit. If it is determined in step 156 that the transmission has ended, the process advances to step 158.

Steps 158 to 162 are steps 136 to 140 and 146 to 150 in the upper search and middle search.
This is exactly the same process.

When steps 158 to 162 are completed, the address of one of the activated terminals is known.

In the subsequent circular processing of steps 164 and 166, the same start signal ST and the detected terminal address are transmitted. As a result, the activated terminal whose address has been detected is polled.

Therefore, after receiving the data from the activated terminal through the cyclic process of steps 168 and 170, the activated terminal search process is ended and the process returns to step 102.

B. Operation of Terminal Referring to FIG. 10, the terminal 5 first performs step 202.
Then, it is determined whether or not a voltage mode central activation signal as shown in FIG. If a central activation signal is sent from the central processing unit (step 104 in FIG. 9), steps 202 to 230 are performed.
Execute the return process. On the other hand, if it is not sent,
At step 250, the presence or absence of activation data is determined. If there is data to be sent to the central processing unit, that is, activation data, terminal activation (child activation) processing consisting of cyclic processing of steps 260 to 280 is executed. In step 202, if the central activation signal has not been sent and there is no terminal data to be sent from itself to the central processing unit, the process directly returns to the first step 202.

Return processing During the return processing, voltage mode transmission data sent from the central processing unit based on the output of the receiving circuit 52 in the cyclic processing of steps 204 and 206 (steps 104 to 106 in FIG. 9) is processed in this cyclic processing. One bit is received each time.

When the predetermined number of bits have been received, the process proceeds from step 206 to step 208, and step 208
Determine the mode MOD.

If the mode MOD is in the upper, middle, or lower group search mode in step 208, the affiliated group return processing in steps 210 to 232 is executed. On the other hand, if the mode MOD is other than group search mode in step 208, normal return processing in steps 240 to 246 is executed.

In step 210 of the affiliated group return process, it is determined whether or not there is activation data. This belonging group return process is a process that is required only for the starting terminal, so if there is no starting data, that is, if the self is not the starting terminal, the process in step 2 is immediately performed without executing the following process.
Return to 02.

On the other hand, if it is determined in step 210 that activation data is present, it is determined in step 212 whether the mode MOD is the upper search mode. If you are in top search mode, step 2
At step 14, the signal is returned at a return timing corresponding to the upper group to which it belongs, for example, the upper three bits of its own address. This return timing is in response to the first synchronization signal if the value of the upper 3 bits is 000, and again in response to 011.
If so, transmit in current mode in response to the fourth synchronization signal. When the return is completed, the process returns to step 202 via step 216.

If rNOJ is determined in step 212, step 2
At step 18, it is determined whether the mode MOD is the intermediate search mode. If it is the intermediate search mode, in step 220 address data A transmitted next to this mode data MOD is selected.
It is determined whether the upper group indicated by DR matches the upper group to which the user belongs. If there is no match, the search is in progress for a group other than the group to which the user belongs, so the process returns to step 20 without executing any further processing.
Return to 2.

On the other hand, if the determination in step 220 is rYEsJ, this means that the terminal is searching for a terminal in the upper group to which it belongs, so in step 222 it searches for the middle group to which it belongs, for example, the middle three bits of its own address. The signal is sent back at the return timing corresponding to the signal. When the return is completed, the process returns to step 202 via step 224.

If the determination in step 218 is "No", in step 226 the upper and middle groups indicated by the address data ADR transmitted next to this mode data MOD match the upper and middle groups to which the self belongs. Determine whether or not to do so.

If it does not, the process returns to step 202 without executing any further processing, since a search is in progress for a group other than the group to which the user belongs.

On the other hand, if the determination in step 226 is rYESJ, the terminal is searching for a terminal in the upper and middle groups to which it belongs, so in step 228 it searches for the lower group to which it belongs, for example, the lower 3 bits of its own address. The signal is sent back at the corresponding return timing. When the return is completed, the process advances to step 232 via step 230, and after clearing the activation data or canceling the activation in step 232, the process returns to step 202.

This completes the belonging group return processing.

If the mode MOD is other than the group search mode in step 208, normal return processing from step 240 onwards is executed.

In this normal return processing, first, in step 240, it is determined whether the destination address ADH sent from the central processing unit matches the own address. If they do not match, the process returns to step 202 without executing any further processing since the polling is for another terminal.

On the other hand, if the determination in step 240 is rYESJ, the communication is addressed to itself, so in step 228 a return signal such as monitoring data is returned bit by bit in synchronization with the synchronization signal. When the return is completed, the process returns to step 202 via step 246.

The activation terminal search process will be described below with reference to FIG.

FIG. 12(a) shows the first central processing unit 1 after detecting a collision.
shows the polling signal from. In the figure, the return signal RPI is represented by a signal RPV converted into a voltage mode by the central processing unit 1.

Here, the terminal device 5 is divided into eight parts according to the value X of the upper three bits of its own address, and the synchronization signal 5YNC is also divided into eight parts.
A bit return signal is sent so as to be sent back.

That is, in response to the first polling, each activation terminal 5 sends a current mode return signal RPI of "1" level only at the X-th bit, depending on the group to which it belongs. Send out. Thereby, the central processing unit 1 can detect which group of terminal devices 5 has been activated. Here, an example is shown in which terminals in the third group (the upper three bits are 010) and the fourth group (the upper three bits are 011) are activated.

From the second time onwards, polling is performed by specifying the detected group. That is, in the above example, address signal A
First, the upper address of DH is 010 (or 011
), set a dummy address in the lower part, and perform the second polling. On the other hand, only terminal devices whose upper addresses are 010 (or 011) generate current mode return signals RPI of 1" level at timings corresponding to the values of the 4th to 6th bits of their own addresses. Through these two pollings, the central processing unit 1
It is possible to detect up to the upper 6 bits of the address of one of the activated terminals.

FIG. 23(b) shows the polling signal from the central processing unit 1 from the second time onwards after the collision was detected. According to the figure, the second group (value of 3 bits to be detected is 001) generates a return signal. Therefore, if this is the second poll, the address for one (or more) of the activated terminals is 010001...
・Can be detected. Similarly, one of the 512 (9 bits) addresses can be detected by polling three times.

Operation of the C5 Monitoring Display Panel Referring to FIG. If the activation signal has been sent (step 104 in FIG. 9), the process proceeds to step 304; on the other hand, if it has not been sent,
Proceed to step 312.

In step 304, the central processing unit sends out (the ninth
Steps 104-106 in the figure) Voltage mode transmission signal (
central activation data). And next step 3
After detecting the return signal (return data) of the terminal in response to this transmission signal using the voltage mode signal converted by the central processing unit in step 06, it is determined in step 308 whether or not these signals match in content. . This step 308
is a process similar to step 140 (FIG. 9) in the central processing unit. If the two signals match in step 308, it means that data transmission between the central processing unit and the terminal device was performed normally, and therefore, in step 310, a display is performed based on the content of the data transmission.

On the other hand, if the two signals do not match in content in step 308, it means that there was an abnormality in the data transmission between the central processing unit and the terminal device, so the data received in steps 304 and 306 is cleared and the step Return to 302. In this case, data transmission of the same content is repeated until it is executed normally, so when it is executed normally, step 3
10 will be executed, and at that time, in step 310, a display is performed based on the contents of the transmitted data.

If it is determined in step 302 that the terminal has not been activated, the process proceeds to step 312, where it is determined whether or not the terminal has been activated. If none of the terminals is activated, the process returns directly from step 312 to step 302.

If it is determined in step 312 that one of the terminals has been activated, in step 314, each bit of terminal data sent from the activated terminal is detected by the voltage mode signal converted by the central processing unit, In step 316, it is determined whether the terminal signal has been transmitted normally based on whether a signal with a predetermined number of bits has been detected.

If the transmission is normal, a load monitoring display based on this terminal data is performed in step 310.

On the other hand, if it is determined in step 312 that data transmission from the terminal device to the central processing unit has not been performed normally, the process returns from step 316 to step 302. In this case as well, the data transmission for starting the terminal is repeated until it is executed normally, so when it is executed normally, step 310
By proceeding up to the point, it will be monitored and displayed.

[Second Embodiment] FIG. 14 shows a functional block configuration of a central processing unit and a terminal device according to a second embodiment of the present invention.

The central processing unit 1 shown in FIG. 14(a) is the same as that shown in FIG. 2, with the synchronization signal generation circuit 18 removed.

Furthermore, the terminal device 5 in FIG. 14(b) has the synchronizing signal generation circuit 55 and the flip-flop circuit 57 removed from the terminal device 5 in FIG. A return pulse width determining circuit 56 is provided which drives the transmitting circuit 53 with a pulse width corresponding to the address requested for return from the processing circuit 1.

FIG. 15 is a flowchart for realizing the functions shown in FIG. 14(a).

The flowchart in FIG. 9 includes steps 140 and 152.
In the processes of 162 and 162, the address is detected based on the return timing in FIG. 9, whereas the address is detected based on the return pulse width in FIG. 15, but otherwise the process is exactly the same.

FIG. 16 is a flowchart for realizing the function shown in FIG. 14(b).

What is the flowchart in Figure 10? Steps 214 and 222
In the processing of 228 and 228, the difference is that in FIG. 10, a return signal is sent out at a timing corresponding to the address, whereas in FIG. 16, a return signal with a pulse width corresponding to the address is sent out. They are exactly the same.

FIG. 17(a) is a diagram showing the return period signal RTM and the current mode return signal RPI, and FIG. 17(b) is a diagram schematically showing the voltage appearing on the transmission line.

[Application Example of the Invention] In the above description, an example has been described in which the present invention is applied to a signal transmission system in which a voltage mode signal is transmitted from the central processing unit side and a current mode signal is transmitted from the terminal device side. The method of the present invention is also applicable to mutual signal transmission in voltage mode. Further, in the above description, an example has been described in which the present invention is applied to a signal transmission system in which a current mode signal from a terminal device is converted into a voltage mode signal by a central processing unit and sent to a transmission line. Since there is no need to perform collision detection on the terminal device, such conversion is not performed.
It is also applicable to a signal transmission system of the type described in No. 5.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a signal transmission system according to a first embodiment of the present invention, FIG. 2 is a functional block diagram of a central processing unit in the system of FIG. 1, and FIG. 4 is a functional block diagram of the terminal device in the system of FIG. 1; FIG. 5 is a functional block diagram of the monitoring display panel in the system of FIG. 1; Fig. 6 is a circuit diagram showing a specific example of the central processing unit shown in Fig. 2, Fig. 7 is a circuit diagram showing a specific example of the terminal unit shown in Fig. 4, and Fig. 8 is a circuit diagram showing a specific example of the terminal unit shown in Fig. 5. FIG. 9 is a flowchart showing the operation of the central processing unit in FIG. 6; FIG. 10 is a flowchart showing the operation of the terminal device in FIG. 7; FIG. 12 is an explanatory diagram of a transmission signal format for explaining the collision activation terminal detection operation in the first embodiment. FIG. 13 is a transmission signal according to the above embodiment. Detailed format for each operation mode FIG. 14 is a functional block diagram of a central processing unit and a terminal device according to a second embodiment of the present invention, and FIG. 15 is a functional block diagram of a central processing unit according to a second embodiment of the present invention. 16 is a flowchart showing the operation of the terminal device according to the second embodiment of the present invention, and FIG. 17 is a diagram explaining the transmission signal format in the second embodiment. . 1: Central processing unit 3: Transmission line 5-L 5-2. 5-3. ...: Terminal 7: Monitoring display panel 9: Load device 11.51: Signal processing circuit 12: Current detection circuit 14: Collision detection circuit 15 Two-differentiation circuit 18: Synchronous signal generation circuit 19.57: Flip-flop circuit 20 .53: Transmission circuit 21. 61, 71: CPU 55: Synchronous signal detection circuit 55: Return pulse width determination circuit RPI: Current mode signal RPV: Voltage mode signal

Claims (2)

[Claims] (1) In a signal transmission system in which a central processing unit and multiple terminal devices are connected to a pair of transmission lines, when signals collide due to activation of multiple terminal devices, the central processing unit detects this collision. , the activated terminal transmits a transmission signal including a mode signal indicating a group report request, and each activated terminal responds to this transmission signal and outputs a return signal at a timing according to the classification to which its own address belongs. , the central processing unit determines the group to which the activation terminal belongs based on the return signal, and performs this operation multiple times from the higher group classification to the lower group classification to detect the address of the activation terminal, and detects the address of the activation terminal. A signal transmission method characterized by accessing a starting terminal to obtain terminal data such as monitoring data. (2) In a signal transmission system in which a central processing unit and multiple terminal devices are connected to a pair of transmission lines, when signals collide due to activation of multiple terminal devices, the central processing unit detects this collision. , transmits a transmission signal including a mode signal indicating a group report request from the activated terminal, and each activated terminal responds to this transmission signal by outputting a return signal with a pulse width corresponding to the classification to which its own address belongs. Then, the central processing unit determines the group to which the activation terminal belongs based on the return signal, and detects the address of the activation terminal by performing this operation multiple times from the higher group classification to the lower group classification, A signal transmission method characterized in that terminal data such as monitoring data is obtained by accessing the activated terminal device.