JPH03203434A - Signal transmission equipment - Google Patents

Abstract

PURPOSE:To quickly receive the start of a slave and to increase a response speed by forming a starting part and a receiving part by a common format out of a transmission signal having the starting part and the receiving part for receiving the start of a slave, a mode part indicating a master starting mode or a slave starting mode, and a data part indicating the contents of control and monitor. CONSTITUTION:Each of transmission signals outputted from a central processing unit(CPU) 1 and respective terminal equipments 3 have the starting part, the receiving part for receiving slave start, the mode part indicating the master starting mode or the slave starting mode, and the data part indicating the contents of control and monitor, and even if the modes of respective transmission signals are different, the formats of the starting parts and the receiving parts are made common in respective signals. When a receiving circuit 21 receives a voltage mode transmission signal transmitted from the CPU 1 to a transmission line 2, a signal processing circuit 23 operates in accordance with a prescribed sequence, receives a control signal or the like included in the voltage mode transmission, signal received by the circuit 21, supplies a load driving signal based upon the control signal or the like to a load 24, and when the load 24 is a load to be monitored, detects its monitoring signal to form monitoring data, and outputs the monitoring data to a transmission circuit 22 in accordance with the control signal or the like.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention connects a central processing unit and a plurality of terminal devices with a pair of transmission lines, and transmits a transmission signal from the central processing unit to the terminal devices. The present invention relates to a signal transmission device that transmits.

(Prior Art) Conventionally, as this type of signal transmission device, there is a cyclic method in which a central processing unit sequentially circulates and accesses each terminal device. However, regardless of whether there is a change in status,
Since all terminals are accessed sequentially, it takes time to learn about necessary changes in the status of terminals.

There is also random transmission, in which only necessary terminals are activated and status changes are detected.

In this random transmission, there is a parent activation mode in which data is transmitted from the central processing unit to the terminal device, and a child activation mode in which data is transmitted from the terminal device to the central processing unit. When transmitting through a pair of transmission lines, for example, a voltage signal is used for the transmission signal from the central processing unit to the terminal device, and a current signal is used for the transmission signal from the terminal device to the central processing unit. ing. Therefore, parent startup mode and child startup mode
By changing the format, child startup is prevented in parent startup mode.

(Problem to be Solved by the Invention) However, when a child activation occurs, a series of processes for the child activation are performed from the central processing unit in the parent activation mode, so until the processing is completed, other terminal devices It is not possible to accept child startup from.

Furthermore, some devices periodically insert a series of normal mode operations that can accept child activations in the middle of a series of processing, but even when child activations are not generated from other terminals,
This process has the problem of slowing down the process.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal transmission device that quickly accepts child activation and does not delay processing.

[Structure of the invention]

(Means for Solving the Problems) The present invention connects a central processing unit and a plurality of terminal devices through a pair of transmission lines, controls and monitors a load connected to one terminal device, and also controls and monitors a load connected to one terminal device. In a signal transmission device that performs parent activation starting from the device and child activation starting from the terminal device, the transmission signal output from the central processing unit and the terminal device includes a start part, a reception part that accepts the child activation, and a parent activation part. It has a mode section indicating whether it is a startup mode or a child startup mode, and a data section indicating control and monitoring contents, and the format of the start section and reception section is common even for the transmission signals in different modes. It is something.

(Function) The present invention makes the format of the start part and the reception part of the transmission signal the same in the child activation mode and the parent activation mode,
By receiving the activation from the child activation in the reception section, even during a series of processing of the parent activation, the process can be interrupted and the child activation can be accepted.
If no child activation has occurred, the parent activation continues.

(Embodiment) An embodiment of the signal transmission device of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a central processing unit, and a plurality of terminal devices 3, a monitoring display panel 4, etc. are connected to this central processing unit 1 via a pair of transmission lines 2. Each terminal 3 is connected to a load such as a lighting fixture, a wall switch, an illuminance sensor, etc. (not shown).

As shown in FIG. 2, this central processing bag r111 is connected to a current detection circuit 11 that detects a current mode transmission signal from the terminal device 3, and to this current detection circuit 11,
Data is captured according to a predetermined sequence, and each terminal device 3
A signal processing circuit 1 that collects data and creates a voltage signal for transmission consisting of a control signal etc. based on this data.
2, is similarly connected to the current detection circuit, and the current detection circuit 1
! The differential circuit 13 generates a differential output every time the output voltage changes, and the transmitting circuit 14 is connected to the signal processing circuit 12 and the differential circuit 13 and transmits a voltage signal for transmission to the transmission line 2. . The transmitting circuit 14 also includes a flip-flop circuit (F/F) +5 as a voltage inverting means that is inverted by the differential output of the differentiating circuit 13, and converts the signal output from the flip-flop circuit 15 into a voltage signal for transmission. and a drive circuit 16 that outputs the signal. Note that the central processing unit 1 is further connected to a keyboard and switches or sensors for data input, and a display device such as a CRT for various displays, as required.

As shown in FIG. 3, the transmission signal includes a start part that instructs to start in both parent activation and child activation formats, a reception part that accepts child activation, a mode part that indicates whether it is parent activation mode or child activation mode, and It has a data section for sending out various data, and the start section and reception section have a common format. If the data is for parent activation, the voltage signal for transmission is a start signal ST consisting of a long pulse signal of "1" level, and a short pulse signal of "1" level that is 1/2 of the required number of bits. It consists of a group of pulses,
Address ADR and control signal CN of destination terminal 3
Unlike the transmission ADR/CNT indicating transmission data such as T, and the long pulse signal of "1" level in the conventional example shown in FIG. It is made up of a return period signal RTM, etc. indicating a return period of monitoring data etc. from. Then, the transmission signal A
DR/CNT consists of each successive "1" level part and "
Each "0" level part represents one bit of data, and a short "1" or "0" level part indicates data "0", and a long one indicates data "1".

Then, in the central processing unit of FIG. 2, the current detection circuit 1
1 converts the current of a current mode transmission signal such as monitoring data shown by diagonal lines in FIG. 4 (1) flowing between the central processing unit 1 and the terminal device 3 via the transmission line 2 into voltage. .

Further, the differentiating circuit 13 detects a change in the current mode transmission signal transmitted from the terminal device 3 by differentiating the output voltage of the current detecting circuit 11.

The voltage output signal from the flip-flop circuit 15 rises at the rising edge of the voltage signal output from the signal processing circuit 12, and falls at the falling edge of the voltage signal output from the signal processing circuit 12.
The differential output of the differentiating circuit 13 is used as a steering wheel to perform a steering operation and invert the output.

That is, when the output of the signal processing circuit 12 is constant, the flip-flop circuit 15 detects a voltage that changes according to a change in the output of the signal processing circuit 12, every time the current mode transmission signal detected by the current detection circuit 11 changes. The voltage is changed to an inverted voltage and transmitted to the drive circuit 16.

Depending on the output voltage of the flip-flop circuit 15, the drive circuit 16 drives the transmission line 2 with a bipolar signal based on the input signal. For example, if the input signal is at the "1" level, the transmission line 2 is pulled up to +24V, and if it is at the "0" level, it is pulled down to -22V. As shown in FIGS. 4(a) and 4(b), the start signal ST and the transmission signal ADR/CNT are transmitted to the transmission line 2 as voltage mode transmission signals having the same shape as the output waveform from the signal processing circuit 12. At the same time, during the return period, a voltage mode transmission signal RPV corresponding to the current mode return signal RPI from the terminal device 3 is transmitted to the transmission line 2.

Further, as shown in FIG. 5, in the terminal device 3, a reception circuit 21, a transmission circuit 22, etc. are connected to the transmission line 2, a signal processing circuit 23 is connected to the reception circuit 21 and the transmission circuit 22, and the signal processing circuit 23 is connected to the transmission line 2. One or more loads 24 are connected to the signal processing circuit 23 .

Then, the receiving circuit 21 connects the central processing unit 1 to the transmission line 2.
When the signal processing circuit 23 receives the voltage mode transmission signal transmitted to the receiver circuit 21, the signal processing circuit 23 operates according to a predetermined sequence, receives and receives the control signal, etc. included in the voltage mode transmission signal received by the receiving circuit 21. , supplies a load drive signal based on this control signal etc. to the load 24, or if this load 24 is a monitoring load, detects the monitoring signal to create monitoring data, and transmits this monitoring data in accordance with the control signal etc. Output to circuit 22. Then, the transmitting circuit 22 changes the resistance between the transmission lines 2 and changes the sink current value in the terminal device 3 in accordance with the monitoring data output from the signal processing circuit 23. Thereby, the monitoring data is transmitted to the transmission line 2 as a current mode transmission signal. Note that when the output impedance of the drive circuit 16 of the central processing unit 1 is low, there is almost no change in the line voltage of the transmission line 2 due to this current mode transmission signal.

Furthermore, as shown in FIG. 6, the monitoring display panel 4 connects a receiving circuit 25 to the transmission line 2, and continuously connects a signal processing circuit 26, a display section 27, and the like.

Then, when the receiving circuit 25 receives the voltage mode transmission signal transmitted from the central processing unit 1 to the transmission line 2, the signal processing circuit 26 operates according to a predetermined sequence, and based on the output of the receiving circuit 26, the signal processing circuit 26 The monitoring data etc. are determined based on the voltage mode transmission signal which is converted by the central processing unit 1 from the current mode transmission signal sent from the device 3, and the display unit 2
7, a display signal corresponding to this monitoring data is transmitted. Note that the display section 27 includes display elements such as LEDs, liacs, LED arrays, LCDs, or CRTs, and a drive circuit for driving these display elements, and receives display signals input from the signal processing circuit 26. Accordingly, the status of the load etc. is indicated by blinking these display elements or by displaying lines, figures, characters, etc. on these display elements.

A specific circuit of the central processing unit 1 is shown in FIG. 7, for example.

The central processing unit 1 includes a microprocessor (CPU) 31
The functions corresponding to the signal processing circuit 12, the differentiation circuit 13, and the flip-flop circuit 15 are based on the operation program of the microprocessor.

Further, an analog-to-digital converter (A/D converter) 32 for converting the analog output of the current detection circuit 11 into digital data that can be processed by the microprocessor 31 and supplying the digital data, for example, a drive circuit 1 from an AC power source.
a DC power supply 33 that generates +24V 124V for the output stage of No. 6 and +5V DC voltage for circuits other than this output stage;
Zero cross detection circuit 3 that detects zero cross of AC power supply
4. Equipped with a zero-cross signal transmission circuit 35 for transmitting a zero-cross signal to the transmission line 2, an oscillation circuit 36 for generating a driving clock for the microprocessor 31, and a reset circuit 37 for setting the microprocessor 31 to an initial state. .

When transmitting a transmission signal from the central processing unit 1 to the terminal device 3, the microprocessor 31 determines that the rOJ level similar to the waveform shown in FIG. 4(b) is OV, and the "1" level is 5V.
A voltage signal of 1 is supplied to the drive circuit 16. Further, the drive circuit 16 transmits a voltage mode transmission signal having a waveform as shown in FIG. Send to 2.

The zero cross detection circuit 34 connects, for example, an AC loov commercial AC power source to a diode bridge DB via an isolation transformer T, connects a resistor R7 and a capacitor C5 between the output terminals of the diode bridge DB, and also grounds the negative electrode. The connection point of resistor R1 and capacitor C9 is connected to the base of phototransistor Tr through resistor R2, and the collector of this transistor Tr is connected to +5V of DC power supply 33 through resistor R3. It is connected to the processor 31, and its emitter is grounded. And control transformer T.

The voltage is stepped down by diode bridge DB, full-wave rectification is performed by diode bridge DB, and base current is applied to the base of transistor Tr to convert
By performing class amplification, when this full-wave rectified output is OV, that is, at the zero-crossing timing of the commercial AC power supply, the transistor Tr is turned off, and the transistor Tr+ is turned off.
A 5V zero cross signal "1" is generated at the collector of the

Furthermore, the microprocessor 31 supplies the zero-crossing signal as it is to the zero-crossing signal transmitting circuit 35 when necessary, such as during central activation. This zero cross signal transmission circuit 3
5 connects an analog switch AS between the OUT terminal for the drive circuit 16 of the microprocessor 31 and the drive circuit 16, and connects the inverter circuit 1 n v from the OUT terminal for the zero-cross signal transmission circuit 35. Connect to analog switch AS via j5. Furthermore, the base of a transistor Tr is connected to the OUT terminal for the zero-cross signal transmission circuit 35 via a resistor R4, the emitter of this transistor Tr2 is grounded, and the collector is connected to a light emitting diode LED and a resistor R1. +5■
Connect to. Furthermore, the light emitting diode LED constitutes a phototransistor PTr and a photocoupler PC,
The collector and emitter of the phototransistor PTr are connected to a diode bridge DB2, one end of the diode bridge DB is connected to the transmission line 2, and the other end is grounded.

When a zero-cross signal is input, the supply of voltage signals from the microprocessor 31 to the drive circuit 16 is cut off by turning off the analog switch A S +, thereby stopping the signal transmission from the central processing unit 1 to the terminal device 3. At the same time, the zero-cross signal drives the photocoupler PC, short-circuits the AC terminals of the diode bridge DB2, and short-circuits the lines of the transmission line 2. Due to this short circuit, a zero-cross signal of voltage 0 is transmitted to each terminal device 3.

Further, in the drive circuit 16, the base of an NPN type transistor Tr or a PNP type transistor Tr4 is connected to the analog switch AS via a resistor R6 or a resistor R7. The emitter of the NPN phototransistor Tr is grounded, and the collector is connected to two resistors R.
8. R91'i is connected to the +24V output terminal of the DC power supply 33. Further, the emitter of the transistor Tr is connected to the +24V output terminal of the DC power supply 33 via diodes D, D, the base of the transistor Tr is connected to the connection point of the resistors R8 and R1, and the collector is connected to the transistor Tr6. connected to the base of this transistor Tr
The collector of 6 is connected to the -F24V terminal of the DC power supply 33 via a resistor R1°, and the emitter is connected to one end of the transmission line 2.

On the other hand, the emitter of the PNP type transistor Tr4 is connected to the +5V output terminal of the DC power supply 33, and the collector is connected to the resistors R8 and R1.
2 to one 24V output terminal of the DC power supply 33. Further, the emitter of a transistor Tr7 is connected to one 24V output terminal of the DC power supply 33 via diodes D3 and D4, and the base of the transistor Tr is connected to a resistor R11.
, R1□, and its collector is connected to the base of the transistor T8, and the DC power supply 33 is supplied with 24 V through the collector resistor R1 of this transistor Tr8.
The emitter is connected to one end of the transmission line 2. Furthermore, the other end of the transmission line 2 is grounded via a resistor R8.

Then, by outputting a positive or negative output from the OUT terminal for the drive circuit 16, the transistor Tr,
Alternatively, one of the transistors Tr4 is turned on, and an output of +24V or -24V is made to the transmission line 2.

Further, the current detection circuit 11 is connected to a resistor R from the other side of the transmission line 2.
It is connected to the inverting input terminal of operational amplifier OP or the non-inverting input terminal of operational amplifier OP2 via IM or resistor R96. The non-inverting input terminal of the operational amplifier OP is grounded, a resistor R+7 is connected between the inverting input terminal and the output terminal, and the output terminal is connected to a diode D and a resistor R58.
It is connected to an analog-to-digital converter 32 via.

On the other hand, the inverting input terminal of the operational amplifier OP2 is grounded, a resistor R19 is connected between the non-inverting input terminal and the output terminal, and the output terminal is connected to the diode D via the diode D6 and the connection point between the resistor RIB. It is connected to the.

Further, the transmitting circuit 36 is an OS of the microprocessor 31.
Connect a crystal oscillator Cr between the C, terminal and the OSC, terminal, and connect a capacitor C2 or a capacitor C1, each with one end installed at the OSC, terminal and the OSC, terminal, and connect the 0SC2 terminal to the inverter circuit 1nv2.
It is connected to the CK terminal of the analog-to-digital converter 32 via.

Further, a specific circuit of the terminal device 3 is shown in FIG. 8, for example.

In Figure 8, 41 is a microprocessor (CPU)
This microprocessor 41 has a signal processing circuit 23
It has the function of receiving circuit 21 and transmitting circuit 22.
is connected.

In this receiving circuit 21, the collector of a transistor Try is connected to the positive output side of a matching diode bridge DB connected to the transmission line 2 via a resistor R2+, and the emitter of the transistor Tr is grounded. , the base is connected to the OUT terminal of the microprocessor 41 via a resistor R22. Further, the transmitting circuit 22 is connected to the other end of the transmission line 2, and is connected to the transistor T through the resistor R2, .
r12, and this transistor T r
The collectors of , , are connected to DC through resistor R24? It is connected to the IN terminal of the microprocessor 41, its emitter is grounded, and a resistor R2+q and a diode D7 are connected in parallel between the base and emitter.

The receiving circuit 21 generates a signal of 0 or 5 V depending on whether the voltage mode of the transmission line 2 is "10" or "1" and supplies it to the microprocessor 41. On the other hand, the transmission circuit 22 is supplied with a transmission signal to the central processing unit l from the terminal device 3 created by the microprocessor 41, and only when this transmission signal is "1" is a resistor R2 installed between the transmission lines 2. Connect. At this time, the resistor R21 becomes a current sink, and the current flowing through the resistor R2 causes the current to flow through the resistor R2.
As shown in the figure, the current RPI flowing through the transmission line 2 changes, and this is detected by the current detection circuit 11 of the central processing unit 1, so that current mode signal transmission from the terminal device 3 to the central processing unit 1 is performed. .

The microprocessor 41 includes a zero-cross signal receiving circuit 42, a self-address setting circuit 43, and a clock generation circuit 4.
4, a load drive circuit 45, a monitoring load 46, and an initialization capacitor C4 are connected.

In addition, the zero-cross signal receiving circuit 42 is connected to a voltage dividing resistor R2b and a resistor R27 that divide the voltage between the output terminals of the diode bridge DB to about 175, and these resistors R2
The connection point between 6 and the resistor R2□ is connected to the IN terminal of the microprocessor 41.

The line voltage of the transmission line 2 becomes 0 only when the central processing unit 1 transmits the zero-cross transmission, and at other times it is +
It is 24V or -24V.

Further, the self-address setting circuit 43 includes a resistor R'! whose one end is grounded. l+ R121R*v and R□ are connected to pull-up switches Sw, Sw, Swv and 8w4, respectively, and each self-address switch SW,
The self-address is set by turning on/off 3w2, SWq, and Sw.

Furthermore, the 03CI terminal of the microprocessor 42, the OS
A crystal oscillator Cr2 is connected between the terminals C and C, and capacitors C6 and C7 each have one end grounded.
is connected.

Further, in the load drive circuit 45, the microprocessor 41
The OUT terminal of the transistor T
connected to the base of rlq, transistor T r +a
The collector of is connected to a DC power supply DC via a light emitting diode LED2, LEDI and a resistor R3.

And these light emitting diodes LED2. LED...
Photothyristor PTh or photothyristor i'
At T b 2, each photocoupling pc2
, pc, is configured. Furthermore, resistors R17, RIM and capacitors CIl, CI2 are connected to the gates of these photothyristors PTh and PTh, respectively, a resistor R39 is connected in parallel to these photothyristors PThPTh2, and a capacitor C (Q is connected in series, a triac TZ is connected to the resistor R19 and the capacitor C+'t connected in series, a resistor R4o is connected to the gate of this triac TZ, and one end of the triac TZ is connected to a commercial The other end of the AC power source is connected to one end of a load, the other end of the commercial AC power source and the other end of the load are connected, and a constant 7ttrE element DA is connected between the commercial AC power sources.

The microprocessor 41 detects the time when the output of the zero-cross transmitter/receiver circuit 42 changes from approximately 5V to 0 as a zero-cross signal, and transmits this zero-cross signal and the central processing unit 1 every Y cycles of the commercial AC power supply. Create 5 ■ pulses with a phase angle based on the control signal transmitted from 1
．． , is supplied to the load drive four-way 45. As a result, in the load drive circuit 45, the triac TZ is turned on at the conduction angle specified by the front control signal, and a lamp, which is a load (not shown), is dimmed and lit.

Further, the monitoring load 46 is composed of a resistor R41 connected to a DC power supply DC, and a switch Swq whose one end is grounded.

When the switch Swq in the monitoring load 46 is operated, the microprocessor 41 detects it and creates monitoring data indicating whether it is on or off. This monitoring data is transmitted to the central processing unit 1 in current mode.

A specific circuit of the monitoring display panel 4 is shown in FIG. 9, for example.

Reference numeral 51 denotes a microprocessor (CPU), which has the function of the signal processing circuit 26, and is connected to the receiving circuit 25 and the display section 27.

The receiving circuit 25 connects a transistor Tr to one end of the transmission line 2 via a diode DI+ and a resistor R42.
16 is connected, the collector of this transistor Tr, 6 is connected to the DC power supply DC2 via the resistor 43, and also to the IN terminal of the microprocessor 51, and the emitter is connected to the other end of the transmission line 2. It is grounded, and a resistor R44 is connected between the base and emitter.

Furthermore, the display section 27 has a resistor R4 connected to each OUT terminal.
The bases of the transistors Tr, , , are connected through a resistor R46 and a light emitting diode LED, respectively.
and is connected to a DC power supply DC2.

Then, the receiving circuit 25 determines that the voltage mode of the transmission line 2 is 10.
” or “1”, a reception signal of 0 or 1 is generated and supplied to the microprocessor 51, and the display section 27 displays the corresponding phototransistor T.
The light-emitting diode LED is turned on by r, ,
, lights up and a display is made.

Furthermore, the clock circuit 52 is connected between the 08CI terminal and the OSC terminal of the microprocessor 51 using the oscillator Cr of this product.
< is connected, and capacitors CI and C10, each of which has one end grounded, are connected.

Further, an initializing capacitor CI7 whose one end is grounded is connected to the reset terminal.

Next, the operation will be explained with reference to a flowchart.

When the central processing unit 1, the terminal device 3, and the monitoring display panel 4 are powered on, they start operating according to a control program built into each microprocessor 31, 41, and 51.

First, initialize the various memories and registers built into each microprocessor 31, 41, and 51,
After that, infinite loop processing shown in each flowchart is executed.

First, the operation of the central processing unit 1 will be explained with reference to the flowchart shown in FIG.

First, the central processing unit 1 checks whether there is startup data. l+ is disconnected (step 101). If there is start data to be sent to the terminal device 3, a start signal S as shown in FIG. 4(b) is sent.
T is transmitted from the drive circuit 16 to the transmission line 2 in voltage mode (step 102). Then, the receptionist sends a signal (Step 103), determines whether or not there is an acceptance of terminal activation (Step 1[14), and determines whether to activate the terminal (Step 1o5), that is, the central processing unit 1
determines whether to start the terminal after transmitting, for example, 10 operations, and if there is no acceptance of terminal startup in step 104 and if it is determined not to start the terminal in step 105, the parent startup mode is selected. Step 106
), data is transmitted (step!07). Thereafter, it is determined whether the process of step 1G2 has been repeated a predetermined number of times corresponding to the number of bits of the transmission data (step +03), and if the number of times of processing is less than the predetermined number of times, the process returns to step 102. When the process of step +02 is repeated a predetermined number of times and voltage mode transmission signals of a predetermined number of bits are transmitted, it is determined that the transmission has ended. next,
Take in the output of the current detection circuit 11 (step +09'
), it is determined whether there is a current mode transmission signal from the terminal device 3 (step 110).

That is, if a current mode transmission signal is not detected within a predetermined time (for example, 600 as), it means that one bit of the return signal of the return data corresponding to the section to which the predetermined time belongs is "0", If detected, it means that the return signal is "1".

If it is determined in step +10 that there is a return signal, the transmission voltage from the drive circuit 16 is inverted in step I11.
), waits until no return signal is detected (step +12), and then inverts the transmission voltage again to return to the original voltage mode (step 113).

Through these processes, "1" of the current mode return signal is converted to "0" of the voltage mode return signal. On the other hand, if the return signal is not detected, it is skipped. In this case, the current mode transmission signal is "0" and the voltage mode transmission signal remains "1", so it is the same as converting the current mode transmission signal to the voltage mode transmission signal.

Then, it is determined whether or not the return data from the terminal device 3 has been completed.In step 14, it is determined whether the conversion process from the current mode transmission signal to the voltage mode transmission signal has been completed for all bits of the returned data. If not, the return has not been completed, and the process returns to step 109 to repeat the process.

On the other hand, when the process has been executed the same number of times as the number of bits of the returned data, it is determined in step 114 that the return from the terminal device 3 has been completed, and, for example, the transmitted control signal CN
This is done by causing the same signal as T to be returned as a confirmation response ACK, and determining whether or not this acknowledge response matches the control signal CNT transmitted by itself.

If the returned data is normal, it means that the transmission of the returned data was carried out normally, and the activation is canceled by clearing the activation data or the like (step 111).

On the other hand, if the returned data is abnormal, the process returns to step 101. In this case, the startup data remains as is, so
It is determined in step 101 that there is activation data, and this central activation process is executed again.

That is, this central activation process is repeated until the activation data is successfully transmitted.

Further, if it is determined in step 101 that there is no activation data, and if it is determined that the terminal is activated in step 105, a start signal ST is transmitted (step +17),
A current mode activation signal is sent from the terminal device 3 (step 118'), and a current mode transmission signal transmitted from the terminal device 3 is received (step 119). Then, the output of the current width circuit 11 is inspected (step 120). If the current mode transmission signal is detected, the transmission signal corresponding to the current timing of the terminal data is "l", so the transmission voltage from the drive circuit 16 is inverted (step 12+), and the current mode transmission is performed. The process waits until no signal is detected (step 122), and then inverts the transmission voltage from the drive circuit 16 again to return the voltage mode of the transmission line 2 to its original state (step 123).

On the other hand, if the return signal is not received even after waiting for the predetermined time in step 120, the bit corresponding to the current timing of the terminal data is rOJ, and the process proceeds. In this case, the transmission voltage from the drive circuit 16 to the transmission line 2 is not inverted.

Next, it is determined whether or not the reception of current mode transmission signals corresponding to all bits of terminal data from the terminal device 3 has been completed, that is, all current mode transmission signals of a predetermined number of bits are converted into voltage mode transmission signals. It is determined whether the conversion has been performed (step 124). If you have not finished receiving, proceed to step 1.
Return to step 19 and repeat the process. Then, when the process is repeated as many times as the number of bits of the terminal data, the necessary processing for the terminal data, such as receiving all bits of the terminal data and converting a current mode transmission signal to a voltage mode transmission signal, is completed. It is determined that reception is complete, and step 10 is performed.
Return to 1.

Next, the operation of the terminal device 3 will be explained with reference to the flowchart shown in FIG.

The terminal device 3 first determines whether a voltage mode central activation signal has been transmitted from the central processing unit a1 (step 2).
01). If a central activation signal is transmitted from the central processing unit 1 and there is activation data to be transmitted to the terminal device 3, it is determined whether the data signal is received and this data signal is repeated a predetermined number of times corresponding to the number of bits of the transmitted data. If the number of processed equal bits is less than the predetermined number of bits (step 203), the process returns to step 201, and when the reception of the predetermined number of bits is completed, the first return signal of the return data is sent from the transmission circuit 22 to the transmission line 2 in current mode. (step 204).

This current mode return signal is received by the central processing unit 1 and converted into a voltage mode transmission signal.
It is determined whether the content matches the transmitted return signal (step 21 [1). If they match, step 20
Since one bit of the return signal transmitted at step 9 was received by central processing unit 1 and converted from current mode to voltage mode, the transmission of that bit was carried out normally.

Then, it is determined whether or not normal transmission of all bits of the return signal has been completed (step 2+1'); if return of all bits has not been completed, step 20
Return to step 9 and repeat the process. On the other hand, if all bits have been returned, the return processing is ended (step 211) and the process returns to step 201. Further, if the return signal and the received signal do not match in step 228, the return signal of the return data was not correctly received by the central processing unit @l, and the process returns to step 201. In this case, since the central processing unit 1 cannot obtain the predetermined number of bits of return data, the central activation process is executed again. Therefore, the terminal device 3 has to perform the return processing again in response to this, and the central processing unit 1 performs the central activation processing and the terminal device 3 performs the return processing in response to this. is repeated.

If it is determined in step 20+ that there is no central activation signal,
f11 determines whether or not there is activation data in the terminal device 3 (step 202). If it is determined that there is no activation data, return to step 201 and transmit the data], (step 21
3), cut off the voltage mode of transmission line 2, and disconnect this voltage
The content of the E-mode transmission signal is compared with the transmitted current-mode transmission signal (step 214). If these signal contents match, the current mode transmission signal sent by r1 is received by the central processing unit l, and ? It can be determined that it has been converted to 11F mode. As long as it is determined that the activation data has been correctly received, this cyclic process continues until it is determined that the transmission of the activation data has been completed (step 215). Then, after clearing the startup data or canceling the startup (step 21G), the process returns to step 20+.

On the other hand, if the contents of the current mode transmission signal transmitted in step 214 and the received voltage mode transmission signal are different, the current mode transmission signal transmitted from the terminal device 3 is correctly received by the central processing unit 1. It was determined that the
The circulation process is interrupted and the process returns to step 20+. in this case,
Since the startup data of the terminal device 3 remains as is, when the central processing unit 1 transmits a start signal for terminal startup and the process proceeds to step 212, it is determined that there is startup data, and this terminal startup process is executed again. be done.

That is, this terminal activation process is repeated until the activation data is normally transmitted to the central processing unit 1.

Furthermore, the operation of the monitoring display panel 4 will be explained with reference to the flowchart shown in FIG.

The monitoring display panel 4 first determines whether a central activation signal has been transmitted from the central processing unit 1 (step 301).

If the central activation signal is transmitted from the central processing unit 1,
An electric FE mode transmission signal transmitted from the central processing unit @1 is detected (step 302). After detecting the return signal of the terminal device 3 in response to this transmission signal using the voltage mode transmission signal converted by the central processing unit 1 (step 303), it is determined whether or not these signals match in content.
11 (step 304). 2 at step 304
If the two signals match, it means that the data transmission between the central processing unit 1 and the terminal device 3 was carried out normally, and therefore a display is performed based on the content of the data transmission (step 305).

On the other hand, if the two signals do not match in content in step 304, this means that there was an abnormality in data transmission between the central processing unit 1 and the terminal device 3, so the received data is cleared and the process returns to step 301. In this case, since data transmission of the same content is repeated until it is executed normally, the process of step 305 will be executed when it is executed normally, so at that time, in step 305, the transmitted data will be Provide content-based display.

Further, if there is no central activation in step 301, it is determined whether the terminal has been activated (step 3o6). If none of the terminals 3 is activated, the process returns to step 30+.

If it is determined in step 306 that one of the terminal devices 3 has been activated, a step is performed in which each bit of the terminal data transmitted from the activated terminal is detected by the voltage mode transmission signal converted by the central processing unit 1. 307), it is determined whether the terminal signal is normally transmitted based on whether a signal with a predetermined number of bits is detected or not (step 308).
). Then, if the transmission is normal, load monitoring based on this terminal data is displayed in step 305.

On the other hand, in step 308, from the terminal device 3 to the central processing unit 1
If it is determined that the data transmission to has not been performed normally, the process returns to step 301.

In this case as well, terminal-activated data transmission is repeated until it is successfully performed.

In the above embodiment, the central processing bag! ! ! We have described a system in which a return signal RTM of level "1" is transmitted during the return period when "1" is returned from the terminal device 3, but as shown in FIG.
As shown in , the return signal RTM may be at the "0" level. However, the polarity of the voltage mode converted from the current mode transmission signal is as shown in Figure 13 (b) and Figure 4 (b).
As shown in , the characteristics are opposite.

Next, a second example will be described.

In this embodiment, instead of the return period signal RTM of the first embodiment shown in FIG. 14(e), as shown in FIG. 14(b), transmission data is transmitted during the terminal transmission period such as the return period. By transmitting a synchronization signal S\NC indicating the transmission timing for each bit from the central processing unit 1 to the transmission line 2 in voltage mode, the timing of signal transmission from the terminal device 3 is determined by the central processing unit! It is managed by il.

The central processing unit 1 in FIG. 15 has a synchronization signal generation circuit 61 that generates a synchronization signal 5YNC at a predetermined end only during the signal transmission period from the terminal device 3 to the central processing unit 1 in the device in FIG.
The flip-flop circuit 19 is configured to invert the output from the signal processing circuit 12 not only by the differential output of the differentiating circuit 15 but also by the synchronizing signal 5YNC. Note that the function of the synchronization signal generation circuit 61 is also performed by the microprocessor 31.

The terminal device 3 in FIG. 16 has a receiving circuit 21 in addition to the one in FIG.
A synchronization signal detection circuit 62 that detects a voltage mode synchronization signal 5YNC transmitted from the central processing unit 1 to the transmission line 2 based on the output of the signal processing circuit 23, and a flip-flop circuit 63 that latches the output of the signal processing circuit 23 are added. , when the synchronization signal detection circuit 62 detects the synchronization signal 5YNC, the transmission circuit 2
2, the latch output of the flip-flop circuit 63 is transmitted to the transmission line 2 in current mode. The microprocessor 31 also has the functions of the synchronization signal detection circuit 62 and flip-flop circuit 63.

Next, the operation will be explained with reference to a flowchart.

First, the operation of the central processing unit 1 will be explained with reference to FIG.

The central processing bag rW1 first sends a start signal (Step +02), then sends an acceptance signal (Step IQ3), and determines whether there is a terminal activation acceptance (Step +04'), and there is no terminal activation. Step 13 (1)
, If there is parent activation data, it is determined whether or not to start the terminal (step 105 '').When starting the terminal, in addition to the case where it is determined that the terminal has been activated in step 104, it is also determined whether there is parent activation data. (Step 101+) If there is no parent activation data, it is the normal mode, and if there is parent activation data, the process shown in FIG. 14(b) is performed according to the flowchart shown in FIG. A start signal ST as shown in FIG.

Address ADR and control signal CN of destination terminal 3
Transmission data consisting of T, etc. is transmitted from the drive circuit 16 to the transmission line 2 in voltage mode (step 102). In addition,
The reception section of the transmission signal determines whether the terminal is in startup mode or normal mode, etc., and performs processing.

In this return signal reception process, n=1 is set (step +31), and the n-th synchronization signal 5YNC is transmitted from the drive circuit 15 (step 132). Here, the synchronizing signal 5YNC is a short pulse of level "1", and thereafter maintains the level rOJ. After that, when the terminal device 3 sends a current mode return signal, the current detection circuit 1
When the output voltage of the drive circuit 16 changes and the transmission of a return signal is detected (step 110), the transmission voltage pulse from the drive circuit 16 is inverted L (step 111), and the nth bit of the return data is "1". Step 1
33), wait until the return signal is no longer detected. Step +13), invert the transmission voltage from the drive circuit 16 again and return the transmission line 2 to the original voltage mode, level "0", that is, the current mode. The return number of “
1'' to 1-1'' of the voltage mode return signal.

Note that when 1 bit (return signal) of the return data to be transmitted is 11, the terminal 3 transmits the current mode transmission signal ``11''.
1", but does not transmit a current mode signal when it is rOJ.

Therefore, in the circulation process of step 134, a predetermined period of time (for example, 60
0μs), the nth bit of the returned data is “
0'' (step +35), the control variable n is incremented (step 136).

Without this return signal, the transmission voltage of the drive circuit 16 remains "0", and as a result, on the transmission line 2,
"0" in the return signal in current mode is represented by "0" in voltage mode. That is, the current mode return signal is converted onto the transmission line 2 as a voltage mode transmission signal regardless of whether the level is "0" or "1".

Then, it is determined whether processing such as detection, level judgment, and conversion into a voltage mode signal of the return signal from the terminal device 3 in the current mode has been completed for all bits of the return data (step 114), and the process returns. .

Next, normal mode processing will be explained with reference to the flowchart shown in FIG.

If the terminal activation is not accepted in step 104, and if the terminal is not activated in step 105, a start signal for normal mode is transmitted to the transmission line 2 (step 117).
). Next, step 14 sets the control variable m to 1.
1), synchronization signal 5Y of the m-th E1 from the drive circuit 16
Send NC (step 142). Next, the output of the current detection circuit 11 is inspected in a circulation process. Here, the synchronizing signal 5YNC is a short pulse of level "1", and a terminal period of level "0" for detecting a terminal signal of terminal data follows this synchronizing signal 5YNC.

Similarly to the return signal reception process, in this terminal signal reception process, when a current mode terminal signal is transmitted from the terminal device 3, the output voltage of the current detection circuit 11 changes. When a change in the output voltage of the current detection circuit 12, that is, the transmission of a terminal signal is detected, it is determined that there is a terminal signal.Step +43
), the transmission voltage from the drive circuit 16 is inverted (step 145).

Then, it is determined that the m-th bit of the terminal data is "1" (step 146), and the process waits until the current mode terminal signal changes to rOJ again (step +22).
), the transmission voltage from the drive circuit 16 is inverted again to return the voltage mode of the transmission line 2 to level "0" (step 123). Through these processes, "1" of the current mode terminal signal is converted to "1" of the voltage mode transmission signal. Note that when the terminal signal, which is 1 bit of data transmitted from the terminal device 3 to the central processing unit 1, is [IJ], it is a current mode transmission signal [1] transmitted from the terminal device 3, but in rOJ. At some point, the current mode transmission signal is "0", which is the same as a no-signal state.

Further, when a predetermined time has elapsed in step 144, it is determined that the m-th bit of the terminal data is 10'' (step +47), and then the control variable m is incremented (step 124). When the current mode terminal signal is "0", the transmission voltage of the drive circuit 16 remains "0" and does not change, but even in this case, the current mode terminal signal is converted to a voltage mode transmission signal. In other words, the current mode terminal signal is converted into a voltage mode transmission signal and transmitted to the transmission line 2, regardless of whether the level is rOJ or "1". Further, in step 124, the control variable m indicates the number of processed bits, and if the control variable m does not reach the number M of bits of the terminal data, all bits of the terminal data have not been received. In this case,
The current is returned to step 142 and the terminal signal reception process is repeated.

On the other hand, if the control variable m becomes equal to the number of bits M of the terminal data in step 124, it means that all bits of the terminal data have been received. In this case, the synchronization signal 5YNC is output (step +49), and it is determined whether there is data to be transmitted or not (step 150). If there is no data to be transmitted, the normal flag is set and the process returns to step +01. Also, if you have data to send, just set the new data! 52), resets the normal flag (step +53'), and returns to step 101.

Furthermore, the operation of the terminal device 3 will be explained with reference to the flowchart of FIG. 19.

In the terminal device 3, first, the central processing unit 1 performs a series of operations, for example, 10 times, and determines that the terminal is not activated. It is determined whether the signal is a start signal for mode (step 201). Central processing unit 1
A start signal in the normal mode is received from , and if it is determined that there is a monitoring input, the self address and monitoring data are set as terminal data (step 222). Furthermore, after setting the control variable m (step 223)
, wait until the synchronization signal 5YNC is received (step 224), and if the synchronization signal 5YNC is received, determine whether the m-th bit of the terminal data (terminal signal) is "1" (step 213) .

If it is "1", wait for a predetermined time (step 225),
A terminal signal in current mode of "1" is transmitted from the transmitting circuit 22 to the transmission line 2 (step 226). The control variable m is incremented (step 227), and it is determined whether transmission of all bits of the terminal data has been completed (step 215). If signal transmission for all bits has not been completed, the process returns to step 224 and repeats the process. On the other hand, if signal transmission for all bits has been completed, the terminal activation process is completed and the process returns to step 201.

In addition, in the above, an example is explained in which the synchronization signal 5YNC is transmitted in a 1:1 correspondence with each bit of the return data or terminal data, that is, the return signal or the terminal signal. Alternatively, only one synchronization signal may be sent, for example for only the first bit.

Further, in step 201, if there is no normal start signal, as shown in FIG. , it is determined whether the destination address ADR matches the own address (step 211). If the destination address ADR does not match the self address, the control signal CNT that follows was sent to another terminal 3, so step 2
01 and waits until the next start signal.

On the other hand, when the destination address ADR and the self address match in step 211, the control variable n is set to l (step 2+2), and then the process waits until the synchronization signal 5YNC is received (step 213). Then, if the synchronization signal is received, a predetermined period of time (for example, 5011S
) After waiting (step 214 >), it is determined whether the n-th bit (return signal) of the returned data is "1" (step 215).

If it is "1", the transmission circuit 22 transmits a current mode return signal of "1" to the transmission line 2 (step 203).

On the other hand, if the T1-th bit of the return data is "0" in step 215, the current mode return signal of "0" is the same as no signal, so the process directly proceeds. Then, the control variable 0 is incremented (step 2+6), and it is determined whether transmission of all bits of the return data has been completed (step 205).

If all bits have not been returned, the process returns to step 213 and repeats the process for the next bit. On the other hand, if all bits have been returned, the process returns.

According to the second embodiment, as shown in FIG. 14(b), the central processing unit 1 transmits the synchronization signal 5YNC indicating the transmission timing for each bit of the transmission data during the terminal transmission period such as the return period. By transmitting in voltage mode to line 2, the timing of signal transmission from terminal device 2 is managed by central processing unit 1, so the transmission timing may be affected by the status of terminal device 3 or delays caused by repeaters. There is no deviation, and the timing can be adjusted by the central processing unit 1.

In any of the embodiments described above, if the terminals 3 are prioritized, the processing of the terminal 3 with a higher priority can be performed while the terminal 3 with a lower priority is being processed.

〔Effect of the invention〕

The present invention provides a start section of a transmission signal that includes a start section, a reception section that accepts child activation, a mode section that indicates whether the mode is parent activation mode or child activation mode, and a data section that indicates control and monitoring contents. By using a common format for the reception section, it is possible to quickly accept child activations, thereby increasing the response speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of the signal transmission system according to the first embodiment of the present invention, FIG. 2 is a functional block diagram of the central processing unit, and FIGS. 3 and 4 are diagrams explaining the format of the transmission signal. , FIG. 5 is a functional block diagram of the terminal device, FIG. 6 is a functional block diagram of the monitoring display panel, FIG. 7 is a circuit diagram showing a specific example of the central processing unit shown in FIG. 2, and FIG. 8 is a functional block diagram of the central processing unit shown in FIG. 9 is a circuit diagram showing a specific example of the terminal shown in FIG. 6, FIG. 9 is a circuit diagram showing a specific example of the monitoring display panel shown in FIG. 6, and FIG. 10 is a flowchart showing the operation of the central processing unit shown in FIG. , 1st
1 is a flowchart showing the operation of the terminal device shown in FIG. 8, FIG. 12 is a flowchart showing the operation of each monitoring display panel shown in FIG. 9, and FIG. 13 is a transmission diagram showing a modification of the first embodiment. FIG. 15 is a functional block diagram of the central processing unit according to the second embodiment of the present invention; FIG. 16 is a functional block diagram of the terminal device; Figures 17 and 18 are 15th
19 and 20 are flowcharts showing the operation of the terminal device shown in FIG. 16. FIGS. 1. Central processing unit, 2. Transmission line, 3. Terminal, RP
I--Current mode signal, RPV--Voltage mode signal. 269-

Claims (1)

[Claims] (1) A central processing unit and a plurality of terminal devices are connected by a pair of transmission lines, and a load connected to the terminal devices is controlled and monitored, and a parent boot is started from the central processing unit and from the terminal devices. In a signal transmission device that performs child activation, the transmission signal output from the central processing unit and the terminal device includes a start part, a reception part that accepts the child activation, and whether the transmission signal is in parent activation mode or child activation mode. A signal transmission device comprising a mode section indicating a mode and a data section indicating control and monitoring contents, wherein the format of the start section and reception section is common even for the transmission signals of different modes.