JPH02200095A - Signal transmission system - Google Patents

Abstract

PURPOSE:To prevent malfunction and an abnormal operation from being performed at the time of short-circuitting or releasing a transmission line by providing a bit '0' or '1' which always goes to a prescribed value in transmission data from a terminal equipment. CONSTITUTION:A central processing unit 1 is provided with a rise detection circuit 16, a synchronizing signal generation circuit 18, and a flip-flop circuit 19 other than a signal processing circuit 11, a current detection circuit 12, and a driving circuit 13. At such a case, each terminal equipment is constituted so that a marker bit which always goes to '0' can be attached on return data in a master start-up mode, and the signal processing circuit 11 in the central processing unit 1 detects the marker bit, and performs a prescribed transmission short-circuit processing in the case of detecting no marker bit '0' and all the bits of the return data as '1's by judging it as the short-circuit of the transmission line. In such a way, the malfunction or the abnormal operation due to the erroneous recognition of data can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal transmission system in which a central processing unit and a plurality of terminal devices are connected by a two-wire transmission line, and in particular, the present invention relates to a signal transmission system in which a central processing unit and a plurality of terminal devices are connected by a two-wire transmission line. The present invention relates to a signal transmission system suitable for remote control that monitors and controls connected loads.

[Problem to be solved by the invention] By the way, in such a signal transmission system, the central processing unit detects the current flowing from itself to the transmission line,
Based on the amount of this current, the transmitted data from the terminal device is identified, for example, by setting "1" when the current is large and "0" when it is small. For this reason, when the transmission line is short-circuited, the system may mistakenly assume that data with all bits of "1" has been transmitted, causing abnormal operation of the system. In particular, when a repeater is connected between the central processing unit and the terminal equipment, this repeater acts as a buffer, so short circuits in the transmission line on the terminal equipment side than the repeater can be avoided on the central processing unit side. Detection was impossible or nearly impossible. Further, when the transmission line is opened, all bits are recognized as "0", and in this case as well, there is a risk of malfunction or abnormal operation.

In view of the above-mentioned problems in the conventional type, an object of the present invention is to provide a signal transmission system in which a central processing unit and a plurality of terminal devices are connected via a two-wire transmission line, and to prevent malfunctions when the transmission line is short-circuited or opened. The purpose is to prevent abnormal operation.

[Operation] According to the above configuration, the data transmitted from the terminal always becomes "0" or "1" at a certain bit.

Therefore, the central processing unit can detect a short circuit in the transmission line based on not detecting ``Om'' in this bit, or detect an open in the transmission line based on not detecting ``1'' in this bit. Can be done.

[Effects] As described above, according to the present invention, a short circuit or an open circuit in a transmission line can be reliably detected by the central processing unit, and malfunctions and abnormal operations due to such a short circuit or open circuit in the transmission line can be prevented.

[Means for Solving the Problems] In order to achieve the above object, in the signal transmission system of the present invention, "0" and "1" are always included in the data transmitted from the terminal.
A bit is provided that has a predetermined value.

[Example] Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a schematic configuration of a remote control device according to an embodiment of the present invention. The device in the figure includes a central processing unit 1 as a parent unit, and a two-wire transmission line 3 (3a,
A plurality of terminal devices 5 (5a, 5b) as child devices connected via terminals 3b, 3c), etc.

5c), a repeater 8 connected between transmission lines 3a and 3b
a and a repeater 8 connected between the transmission lines 3b and 30
It is equipped with b etc. Each terminal device 5 is connected to a load (not shown), such as a lighting fixture, a wall switch, an illumination sensor, etc., respectively.

Such a device configuration is known as a remote control device, for example, as shown in Japanese Patent Publication No. 61-3155.
For example, a central processing unit and a plurality of terminal devices are connected by a two-wire transmission line, and the central processing unit transmits short pulse ADR/ CNT and a long pulse RTM for a monitoring signal are transmitted, and a series circuit of a current limiting resistor and a switch element is connected in parallel to the transmission line in each terminal device to monitor during the transmission period of the long pulse for a monitoring signal. The switch element is opened and closed according to the contents, and the central processing unit detects the current change RPI in the transmission line due to this opening and closing operation.

By the way, when transmitting signals from the terminal to the central processing unit in a current mode that changes the current sinking at the terminal, as in this conventional remote control device (hereinafter referred to as the conventional system), the central processing unit detects Current can be converted into voltage using a resistor or the like and detected. However, since this signal current flows only between the sending terminal device and the central processing unit, this monitoring signal etc. cannot be detected at a position other than between the sending terminal device and the central processing unit.

Therefore, in this conventional system, each terminal can only detect the signals of the terminals in the later stages, and it is not possible for all terminals to detect the signals of all other terminals, so the random When a terminal device attempts to initiate an activation during transmission (child activation), the initiating terminal device is able to determine whether there is a signal sent from the previous terminal device, that is, whether the transmission line is occupied or signal collision occurs. However, it was not suitable for random transmission.

This embodiment is an improvement on this conventional system, in which the central processing unit 1 detects changes in the current mode signal sent from the terminal, and inverts the voltage mode on the transmission line according to the rising edge of the signal. By doing so, current mode signals from terminals are converted to voltage mode signals so that all terminals can detect the signals sent from all other terminals as voltages.

FIG. 2 shows a functional block configuration of the central processing unit 1. As shown in FIG.

This central processing unit 1 has a rise detection circuit 16, a synchronization signal generation circuit 18, and a flip-flop circuit 19 added to the central processing unit of a conventional system consisting of a signal processing circuit 11, a current detection circuit 12, and a drive circuit 13. It is.

The central processing unit 1 is further provided with a keyboard and switches or sensors for data input, and a display device for various displays, such as a CRT, as required.

The signal processing circuit 11 takes in data from the keyboard, switches, sensors, etc. according to a predetermined sequence, collects monitoring data from each terminal, creates control signals based on this data, and sends data to the display device. indicate. Also, a transmission voltage signal consisting of this control signal and the like is created. In the central processing unit of the conventional system,
This voltage signal is input as is to the drive circuit 13,
Since it was sent to the transmission line 3 as a transmission signal, the format of this transmission voltage signal is the same as that shown in FIG. 3(a), which is the transmission signal format from the central processing unit in the conventional system.

Referring to FIG. 3(a), this transmission voltage signal, that is, the transmission signal in the conventional system, consists of a start signal ST consisting of a long pulse signal of #1 level, and 1 bit of the required number of bits.
The transmission signal ADR/CNT consists of a group of "1" level short pulses of /2 number and indicates transmission data such as the address ADR of the destination terminal and the control signal CNT, and a "1" level long pulse signal. It is composed of a return period signal RTM, etc. indicating a return waiting period (or terminal transmission section) for monitoring data etc. from the previous terminal device.The above-mentioned transmission signal ADH
/CNT is sequentially connected to each successive “1° level portion” and “0”
Each rubel represents 1 bit of data,
If the “1” or “0” level part is short, it is data.”
0'' and the longer one is 1#. Figure 3 (a
), the signal ADR/CNT is "001...
” is shown.

Returning to FIG. 2, the current detection circuit 12 detects the current flowing between the central processing unit 1 and the terminal device via the transmission line 3 (current such as monitoring data as shown by diagonal lines in FIG. 3(a)). mode signal) into voltage.

The drive circuit 13 drives the transmission line 3 with a bipolar signal according to the input signal. For example, if the input signal is at the "1" level, it pulls up the transmission line 3 to +24V; In the central processing unit 1 of the conventional system, the signal voltage output of the signal processing circuit 11 is inputted to the drive circuit 13 as it is, but in this embodiment, the signal voltage output as shown in FIG. As shown, the start signal ST and the transmission signal ADH/CNT are sent out as they are, but the return period signal RTM output from the signal processing circuit 11 during the return period is transmitted to the flip-flop circuit 1.
9, the image is processed as appropriate before being sent out. This flip-flop circuit 19, together with the drive circuit 13,
It constitutes the transmitting circuit 20 of the central processing unit 1 of this embodiment.

The rise detection circuit 16 detects the rise of the current mode signal sent from the terminal by differentiating the output voltage of the current detection circuit 12.

The synchronization signal generation circuit 18 generates the synchronization signal 5YNC at a predetermined period only during the return waiting period (terminal transmission period) RTM from the terminal to the central processing unit.

The flip-flop (F/F) circuit 19 has a voltage output that rises at the rising edge of the voltage signal outputted from the signal processing circuit 11 and the synchronization signal 5YNC outputted from the synchronization signal generation circuit 18, and falls at the falling edge thereof. The output is inverted using the detection output of the rising edge detection circuit 16 as a trigger. That is, the flip-flop circuit 19 is connected to the signal processing circuit 11 during the sending period of the address signal and the control signal.
Drive circuit 1 that changes the voltage according to the output change of
3, and the output of the signal processing circuit 11 is constant during the waiting period for return from the terminal, the current mode signal detected by the current detection circuit 12 or the synchronization signal output from the synchronization signal generation circuit 18 is " When it rises from “0” to “1”, “
When the synchronizing signal output falls from '1' to '0#', a voltage which becomes '0' is sent to the drive circuit 13.

The drive circuit 13 transmits data according to the output voltage of this flip-flop circuit 19! By driving I3, the start signal ST and the transmission signal ADR/CNT are voltage mode signals having the same shape as the output waveform from the signal processing device 11, as shown in FIGS. 3(a) and 3(b). transmission line 3
At the same time, in the terminal transmission section RTM, a synchronization signal 5YNC is sent from the central processing unit,
When a current mode signal RPI is sent from the terminal in response to this synchronization signal 5YNC, a voltage mode signal RPV corresponding to this signal RPI is sent to the transmission line 3.

That is, in the transmission system of FIG. 1, during the terminal transmission period RTM, a current mode signal from the terminal device 5 is converted into a voltage mode signal by the central processing unit 1 and sent to the transmission line 3. Therefore, all terminals use this voltage mode signal to determine the content of not only terminals connected later than themselves, but also current mode signals from terminals connected earlier. Can be done. Therefore, since each terminal device can determine the signal transmission state of all terminal devices based on this voltage mode signal, it can determine by itself the degree of clearance of the transmission line 3 and the presence or absence of signal collision. Therefore, according to this system, there are fewer collisions without increasing the burden on the central processing unit.
It is possible to realize a random transmission method that takes advantage of the inherent high transmission speed of the random method. Furthermore, when each terminal transmits a current mode signal, the central processing unit determines the voltage mode signal converted from the current mode signal, thereby ensuring that the current mode signal is correctly received by the central processing unit. You can check whether the Therefore, an answer signal from the central processing unit is not required, and the transmission speed can be increased regardless of the transmission method.

In addition, in the apparatus shown in FIG. 1, as a mode for collecting monitoring data of each terminal, the central processing unit 1 sends a transmission request signal including a destination address and a control signal to the transmission line 3, and in response , a central activation mode that receives the monitoring data of the terminal device returned from the destination terminal device, and a self-address and monitoring data that are randomly sent from the terminal device that generated the call request, such as when the monitoring data changes. A child activation mode is set in which transmission data including transmission data is received. Here, each terminal device is configured to add a marker bit that is always "0" to the returned data in the parent activation mode.

The signal processing circuit 11 in the central processing unit 1 determines the state of the transmission line by detecting this marker bit. If this marker bit "0" is not detected and all bits of the return data are detected as "1", it is determined that a transmission line short circuit has occurred and a predetermined transmission line short circuit process is performed.

This makes it possible to distinguish between return data in which all bits are "1" and transmission line short circuits, and to prevent malfunctions or abnormal operations due to data:A recognition. In contrast,
In the conventional system, the return data from the terminal device did not include the above-mentioned marker bits, so it was not possible to distinguish between the return data in which all bits were "1" and the transmission line short circuit.
This caused malfunction or abnormal operation.

Note that by adding a marker bit that is always "1", it is possible to detect an open transmission line, for example, a disconnection.

FIG. 4 shows a functional block diagram of the terminal device 5 in the transmission system of FIG. 1. This terminal device 5 includes a signal processing circuit 5
1. A synchronizing signal detecting circuit 55 and a flip-flop circuit 57 are added to the conventional system terminal device consisting of a receiving circuit 52, a transmitting circuit 53, a self-address setting circuit 63, etc. Further, one or more loads 9 are connected to the signal processing circuit 51 . Furthermore, a rectifier circuit (not shown) is provided which rectifies the ±24V bipolar pulse sent from the central processing unit 1 and uses it as a power source for operating the terminal.

The receiving circuit 52 receives the voltage mode signal sent from the central processing unit 1 to the transmission line 3, and the synchronization signal detection circuit 55 receives the voltage mode signal sent from the central processing unit 1 to the transmission line 3 based on the output of the receiving circuit 52. Detects voltage mode synchronization signal.

The signal processing circuit 51 operates according to a predetermined sequence, receives and receives a control signal, etc. included in the voltage mode signal received by the receiving circuit 52, and supplies a load drive signal to the load 9 based on this control signal, etc. Alternatively, if the load 9 is a monitoring load, the monitoring signal is detected to create monitoring data, and this monitoring data is output to the transmitting circuit 53 in accordance with the control signal and the like.

Further, following the monitoring data, a marker bit signal of "1" is always output to the transmitting circuit 53. Return data consisting of these monitoring data and marker bit signals is sent one bit at a time to the transmitting circuit 53 each time one synchronizing signal is detected by the synchronizing signal detecting circuit 55. Transmission circuit 5
3 connects a resistor between the transmission lines in accordance with the monitoring data output bit by bit from the signal processing circuit 51 and the "1" level of the marker bit signal, and changes the sink current value in the terminal 5. Thereby, the monitoring data and the marker bit signal are sent to the transmission line 3 as a current mode signal. Central processing unit drive circuit 13
When the output impedance of is low, there is almost no change in the line voltage of the transmission line 3 due to this current mode signal, but the shaded area RPI in FIG. 3(a) schematically shows this current mode signal.

The flip-flop circuit 57 is for latching the output of the signal processing circuit 51.

FIG. 5 shows repeater 8 (8) in the transmission system of FIG.
Fig. 8a, 8b) shows a functional block diagram. Such a repeater 8 is used for signal amplification and correction of waveform distortion when the transmission line becomes long, and when the transmission line becomes long or the number of terminal devices increases, the power supply from the central processing unit increases the number of terminal devices. It is inserted in the middle of the transmission line 3 in order to supply power to the terminal device when the power supply is insufficient, and includes a voltage waveform receiving circuit 81, a coupling circuit 82, 83, an amplifier 84 .
85, voltage signal driver 86, timing generation circuit 8
7, a current detection circuit 88, a current signal driver 89, a power supply circuit 90, and the like.

The voltage waveform receiving circuit 81 and the current signal driver 89 are the receiving circuit 52 and the transmitting circuit 53 of the terminal device 5, respectively.
The voltage signal driver 86 and current detection circuit 88 are configured similarly to the current detection circuit 12 and drive circuit 13 of the central processing unit 1, respectively. Further, the coupling circuits 82 and 83 are for direct current isolation between input and output, and the amplifiers 84 and 85 are for signal amplification and waveform shaping. Further, the power supply circuit 90 is for supplying power to the terminal device 5 connected to the side of the repeater 8 opposite to the central processing unit 1.

In this repeater 8, for example 8a, the central processing unit 1
A voltage waveform receiving circuit 81 similar to that of the terminal 5 receives transmission signals sent from the terminal 5b to the terminal 5b and voltage signals such as synchronization pulses, and the amplifier 84 performs amplification and waveform shaping. The voltage signal driver 86 similar to the above is driven and transmitted to the terminal device 5b side. Further, a current signal such as a return signal from the terminal device 5b is received by a current detection circuit 88 similar to that of the central processing unit 1, and is amplified and waveform-shaped by an amplifier 85. drive the driver 89 and send it to the central processing unit 1 side. Therefore, this repeater 8 appears to be a terminal device when viewed from the central processing unit 1 side, and appears to be a central processing unit when viewed from the terminal device side.

The central processing unit side and the terminal side of the repeater 8 are DC-insulated by a coupling circuit 82, 83 such as a photocoupler or an isolation transformer, and power is supplied to the terminal side from a repeater power supply 90.

Moreover, the reason for performing waveform shaping is as follows. That is, the voltage signal from the repeater 8 to the terminal device 5 is as shown in FIG.
It is sent as a ±24V bipolar pulse signal as shown in a),
On the terminal side, this signal is rectified and used as a power source. Therefore, the voltage signal such as the synchronization signal S
When switching to , a current as shown in FIG. 6(b) flows into the transmission line and the capacity of the rectifier circuit of the terminal device 5. This current is detected by the current detection circuit 88 and drives the current driver 89. When repeaters are connected in multiple stages, the width of this current signal increases, and this may be mistakenly detected as a signal from the original terminal by the central processing unit 1, resulting in malfunction or transmission failure. Therefore, during a certain period including the switching time, the timing generation circuit 87 generates a current return inhibition signal DIS as shown in FIG. 6(c).
The current signal at the time of polarity reversal is prevented from being transmitted to the central processing unit 1 side. FIG. 2D shows a current signal waveform sent from the repeater 8 to the central processing unit 1 side.

Figure 7 shows Middle I! 8 is a flowchart showing the current signal relay operation in the device 8. FIG.

That is, in step 801, the current signal driver 89
Set the output to '0'. Subsequently, in step 802, the process waits until the output of the voltage waveform receiving circuit 81 falls. When this output falls, timer T is reset in step 803 and then started in step 804. In the following step 805, the timer T waits until a predetermined time T has elapsed, and when the time T1 has elapsed, the process advances to step 806. In step 806, it is determined based on the output of the current detection circuit 88 whether or not a current signal from the terminal device has been received. If received, the output of the current signal driver 89 is set to "1" in step 807,
On the other hand, if the signal has not been received, the outputs of the eight current signal drivers are set to "0" in step 807, and then the process proceeds to step 809. In step 809, the time value of timer T is checked again. If time T2 has not yet come, the process returns to step 806 and repeats steps 806 to 809. On the other hand, if time T2 has been reached, the process returns to step 801 and repeats steps 801 to 809. As a result, the relay of the current signal from the terminal device to the central processing unit 1 is enabled (ENB) only in the interval from time T1 to T2, and is prohibited in other intervals (DIS).
) to be done.

FIG. 8 shows a specific circuit example of the central processing unit 1 in the remote control device shown in FIG.

The central processing unit in the figure is a microprocessor (CPU)
The signal processing circuit 11 and the rising edge detection circuit 16 shown in FIG.
, synchronous signal generation circuit 18 and flip-flop circuit 1
The functions corresponding to 9 are realized by the operation program of the CPU 21.

The central processing unit in the figure further includes an A/D converter 22 for converting the analog output of the current detection circuit 12 into digital data that can be processed by the CPU 21, and an A/D converter 22 for converting the analog output of the current detection circuit 12 into digital data that can be processed by the CPU 21. +26V of
A DC power supply 23 that generates a DC voltage of -26V and +5V for circuits other than this output stage, a zero-cross detection circuit 24 that detects zero-crossing of the AC power supply, and a zero-crossing signal sending circuit for sending a zero-crossing signal to the transmission line 3. 25
, an oscillation circuit 26 that generates a drive clock for the CPU 21,
Reset circuit 2 for setting the CPU 21 to the initial state
It is equipped with 7.

When sending a transmission signal from the central processing unit to the terminal device, C
PU21 has a waveform similar to that shown in FIG. 3(b), but 0
A voltage signal whose level is OV and whose level is 5V is supplied to the drive circuit 13.
According to the voltage signal from U21, the “0” level is 124V
Then, a voltage mode signal having a 1° level of +24V and a waveform as shown in FIG. 3(b) is sent to the transmission line 3.

The zero-crossing detection circuit 24 detects the zero-crossing of the AC power supply and inputs a zero-crossing signal at the '1# level to the CPU 21. In this detection circuit 24, for example, AClo
oV AC power is supplied to the diode bridge DBI via the isolation transformer T1, and this diode bridge D
By applying the full-wave rectified output from the BI to the base of the transistor Trl and super-class-C amplifying it, when this full-wave rectified output is Ov, that is, at the timing when the AC power supply zero-crosses, the collector of the transistor Trl receives 5. generates a zero-cross signal.

The CPU 21 supplies this zero-crossing signal as it is to the zero-crossing signal transmitting circuit 25 when necessary, such as during central activation. In the zero-crossing signal transmission circuit 25, when the zero-crossing signal is input, the analog switch ASI turns off to cut off the voltage signal supply from the CPU 21 to the drive circuit 13, thereby cutting off the signal transmission from the central processing unit to the terminal device. , the photocoupler PCI is driven by a zero-cross signal from the CPU 21 to short-circuit the AC terminals of the diode bridge DB2, thereby short-circuiting the transmission lines 3. As a result, a zero-cross signal of voltage 0 as shown in FIG. 12 is transmitted to the terminal device.

Conventionally, this zero-crossing signal was created in the terminal device, but if it were created in the central processing unit and transmitted to each terminal device, one zero-crossing detection circuit would be sufficient, and each terminal device would have a zero-crossing detection circuit. The circuit configuration can be simplified and the cost can be reduced from the viewpoint of the entire system, compared to the case where the circuit is provided in the circuit.

FIG. 9 shows a specific circuit example of the terminal device 5 in the transmission system of FIG. 1.

The terminal shown in the figure is configured so that its entire operation is controlled by a microprocessor (CPU) 61.
The functions corresponding to the signal processing circuit 51, synchronous signal detection circuit 55, and flip-flow knob circuit 57 in FIG.
This is realized using 61 operating programs. 52 and 53 are a receiving circuit and a transmitting circuit, respectively, which are common to those shown in FIG.

Further, 62 is a zero-cross signal receiving circuit, 63 is a self-address setting circuit, and 64 is a full-wave rectifier of the +24V bipolar pulse sent to the transmission line 3 from the central processing unit or repeater 8 to generate a 5V DC output. 65 is a clock generation circuit.

Furthermore, when the power of this terminal device is turned on, the C51 uses the CPU61
A capacitor DB51 for resetting is a diode bridge for matching the transmission line 3, which is a bipolar (AC) system, with the transmitting circuit 52 and zero-cross signal receiving circuit 55, which are unipolar (DC) systems.

Various load devices are connected to this terminal unit as needed, either singly or in various combinations. The following is an example of a switch. Note that in each of the load devices 91 and 92, only the load drive section is shown.

The receiving circuit 52 generates signals of 0 and 5 V depending on whether the voltage mode of the transmission line 3 is "0" or "1", respectively, and supplies them to the CPU 61.

The transmission circuit 53 is supplied with a transmission signal from the terminal device created by the CPU 61 to the central processing unit, and this transmission signal is
'', a resistor R51 is connected between the transmission lines 3.

At this time, the resistor R51 becomes a current sink, and the current flowing through the resistor R51 changes the current RPI flowing through the transmission line 3 as shown by diagonal lines in FIG. Current mode signal transmission from the terminal device to the central processing unit is performed by the detection in FIG.

As shown in FIG. 12, the line voltage of the transmission line 3 is 0 only when a zero-cross signal is sent from the central processing unit, and is otherwise +24V or -24V. In other words, the DC terminal voltage of the diode bridge D B 51 becomes 0 only when the zero cross signal is sent, and is approximately +2 at other times.
It becomes 4V. The zero-cross signal receiving circuit 62 is a voltage dividing resistor circuit that divides the DC terminal voltage of this diode bridge DB51 into approximately 175 volts.

When the output of the zero-cross signal receiving circuit 62 changes from approximately 5V to 0, the CPU 61 detects it as a zero-cross signal. Then, every half cycle of the AC power supply, a 5V pulse is created with a phase angle based on this zero-cross signal and the control signal transmitted from the central processing unit, and is supplied to the dimming device 91. As a result, in the light control device 91, the triac T
Z is turned on at a conduction angle specified by the control signal, and a lamp, which is a load (not shown), is dimmed and lit.

On the other hand, in the monitoring load 92, the switches 5W91 to 94
is an individual switch, switch 5W95 is a setting switch, and switch 5W9B is a specific switch. When any of these switches is operated, the CPU 61 detects it and creates monitoring data indicating its on/off status. This monitoring data is sent to the central processing unit in current mode as described above.

The individual switches 5W91 to 5W94 are for changing the lighting state of the plurality of light control devices 91 assigned to each one, and the setting switch 5W95 is for changing the lighting state of the plurality of light control devices 91 assigned to each one, and the setting switch 5W95 is for changing the lighting state of the plurality of light control devices 91 assigned to each one.
This is for resetting the lighting pattern changed by 94 as the current lighting pattern. Specific switch 5W
Reference numeral 96 is for inverting the signal of a predetermined bit of transmission data from the terminal device to the central processing unit. For example, if the most significant bit of the terminal device with its own address "0001" is inverted by pressing this specific switch 5W9B, the terminal device's own address will be rl 001J. therefore,
It is possible to send setting signals and the like to the terminal device having its own address r1001J from the terminal device having its own address r0001J. This makes it possible to assign patterns (groups) to terminal devices that do not have individual switches, such as sensors, without changing the mode of the central processing unit. Therefore, processing is also simple.

Next, the operations of the central processing unit 1 and the terminal device 5 shown in FIGS. 1-9 will be explained with reference to the flowcharts shown in FIGS. 10-11.

When the central processing unit 1 and the terminal device 5 are powered on, they start operating according to a control program built into each CPU.

First, after initializing various memories, flags, registers, etc. built into the CPU, the central processing unit 1 is operated as shown in the flowchart of FIG.
Each infinite loop process shown in the flowchart of FIG. 1 is executed.

A. Operation of the Central Processing Unit Referring to FIG. 10, the central processing unit 1 first determines the presence or absence of activation data in step 102.

If there is data to be sent to the terminal, that is, activation data, the central activation (parent activation) processing of steps 104 to 142 is executed, and if there is no activation data, steps 150 to 18 are executed.
0 normal mode processing is executed.

Central start-up process During the central start-up process, first, in step 104, a start signal ST, a destination terminal address ADR, and a control signal (start-up signal) as shown in FIG. Data) Transmission data consisting of CNTs, etc. is sent from the drive circuit 13 to the transmission line 3 in voltage mode.

This transmission data is sent out one bit each time the process of step 104 is passed through. Next step 1
06 is a step for determining whether the process of step 104 has been repeated a predetermined number of times corresponding to the number of bits of the transmission data. If the number of times of process of step 104 is less than the predetermined number of times, the process returns to step 104. return. When the process of step 104 is repeated a predetermined number of times and a voltage mode signal of a predetermined number of bits is sent out, step 10
In step 6, it is determined that the transmission is completed, and the process proceeds to the next step, step 110.
Proceed to.

In step 110, a synchronizing signal consisting of a voltage pulse of level '1'' is generated.Subsequently, in step 112, the output of the current detection circuit 12 is taken in, and in step 114, it is determined whether or not there is a current mode signal from the terminal. Similarly to each of the above embodiments, in this embodiment as well, the terminal device 5 receives one bit (return signal or terminal signal) of the data to be sent.
If it is “1°,” the current mode signal will be sent, but if it is “0”
When , the current mode signal is not sent out. Therefore, here, if a current mode signal is not detected within a predetermined time (for example, 600 μs), it means that one bit (return signal) corresponding to the section of the data to be sent to which the predetermined time belongs is 0°. However, if detected, it means that the bit (return signal) is "1".

If it is determined in step 114 that a return signal is present, the sending voltage from the drive circuit 13 is inverted in step 118. If no return signal is detected, step 118
In other words, the process directly proceeds to step 132 without inverting the output voltage from the drive circuit 13.

In step 132, it is determined whether the return from the terminal device has been completed. Synchronization signal generation (step 110) and return signal reception (step 1) for all bits of returned data
If step 12) has not been completed, the return process has not yet been completed, so steps 132 to 110 are completed.
The process returns to step 110 and repeats steps 110 to 132.

On the other hand, when the processes of steps 110 to 132 are executed the same number of times as the number of bits of the returned data, step 1
At step 32, it is determined that the return from the terminal device has been completed, and the process proceeds to step 136. In step 136, it is determined whether all bits of the received return data are a12. Since the return signal from the terminal device 5 includes at least one "0" level signal as a marker bit signal, normally it is impossible for all bits to become "1". Therefore, if all bits are "1", it is determined that there is an abnormality such as a short circuit in the transmission line, and step 1
At step 38, error processing such as issuing a warning is executed. On the other hand, if at least one "0" level signal is received in the determination at step 136, it is determined that normal operation is in progress;
Processing proceeds from step 136 to step 140. In step 140, it is determined whether the returned data is normal. This determination can be made, for example, by returning the same signal as the transmitted control signal CNT as an acknowledgment ACK, and determining whether or not this acknowledgment ACK matches the control signal CNT itself transmitted. Alternatively, a status signal indicating the normality/abnormality detection result of transmission/reception in the terminal device may be added to the end of the return data from the terminal device, and the determination in step 140 may be made depending on whether or not this status signal is received.

If the returned data is normal, the startup is canceled by clearing the startup data in step 142, and then step 1
Return to 02.

On the other hand, if the returned data is abnormal, step 142 is skipped and the process returns directly from step 140 to step 102. In this case, the startup data remains as is, so
It is determined in step 102 that activation data is present, and this central activation process is executed again. That is, this central activation process is repeated until the activation data is successfully transmitted.

Normal mode processing If it is determined in step 102 that there is no startup data,
Next, in step 150, a start signal and an initial synchronization signal for starting the terminal as shown in FIG. judge. A predetermined time (for example, 600 μs) for the synchronization signal following this first start signal.
If there is no response from any terminal device, there is no terminal activation, and the process returns to step 102.

On the other hand, when a terminal activation signal as shown in FIG. 12 (3) is detected in step 154, it is determined that the terminal has been activated, and the process proceeds to step 156, and steps 156 to 180
Executes normal mode processing.

During this normal mode processing, first, in step 156, the first synchronization signal is sent out, and then in step 158, the output of the current detection circuit 12 is taken in.

As mentioned above, in this embodiment, if there is no current mode signal within a predetermined time (for example, 600 μs), it means that one bit of the terminal data corresponding to the section to which the predetermined time belongs is “0”; The presence of a signal means that the bit is 1''. In step 160, the output of the current detection circuit 12 that has been taken in is inspected. If the current mode signal is detected, the bit corresponding to the current timing of the terminal data is checked. (terminal signal) is "1°," after inverting the output voltage from the drive circuit 13 in step 164, the process proceeds to the next step 180.

On the other hand, if the terminal signal is not received even after the predetermined time has elapsed in step 160, the bit corresponding to the current timing of the terminal data is "0", so step 164
The process skips step 160 and proceeds directly to step 180. In this case, the voltage sent from the drive circuit 13 to the transmission line 3 is not inverted.

Step 180 includes synchronization signal transmission processing (step 156), reception processing (step 158), and signal presence/absence determination processing (step 160) for all bits of terminal data.
) etc. is completed. If these processes have not been completed, the process returns to step 156 and the processes of steps 156 to 180 are repeated.

When the processes in steps 156 to 180 are repeated as many times as the number of bits of the terminal data, it is determined in step 180 that reception has ended, and the process proceeds to step 190. Step 19
If it is 0, it is determined whether all bits of the received return data are 1''.

If all bits are "1", it is determined that there is an abnormality such as a short circuit in the transmission line, and error processing such as issuing a warning is executed in step 138. On the other hand, if it is determined in step 190 that at least one "O" level signal has been received, it is determined that normal operation is in progress, and the process returns from step 190 to step 102.

Note that the determination in step 136 or 190 is rYEsJ.
In this case, the transmission state is inspected by further activation one or more times, and the error processing at step 138 is performed only when the determination at step 136 or 190 becomes YESJ multiple times in succession. You can also do this.

B. Operation of the terminal device Referring to FIG. 11, the terminal device 5 first performs step 202.
It is determined whether or not a voltage mode central activation signal has been sent from the central processing unit. If the central processing unit has sent out the central activation signal by the process of step 104 in FIG. 10, the process advances to step 204, and steps 204 to
230 is executed. On the other hand, if the data has not been sent, it is determined in step 250 whether or not there is activation data.

If there is data to be sent to the central processing unit, that is, activation data, terminal activation (child activation) processing consisting of cyclic processing of steps 256 to 280 is executed.

In step 202, the central activation signal is not sent;
If there is no terminal data to be sent from itself to the central processing unit, the process returns to the first step 202.

Return processing During return processing, data is sent from the central processing unit based on the output of the receiving circuit 52 in the circular processing of steps 204 and 206 (steps 104 to 106 in FIG. 10).
The transmission data in voltage mode is
Receive bit by bit.

Then, when the reception of a predetermined number of bits is completed, step 2
The process proceeds from step 06 to step 210, and in step 210 it is determined whether the address data in the received transmission data matches the own address. Note that if the transmission method is not the checksum method, this determination is made in step 202.
This may be done by receiving the address data at the step. If the addresses match as determined in step 210, the process proceeds from step 210 to step 216, and if they do not match, the process returns to step 202.

Step 216 waits until a synchronization signal is received. When the synchronization signal is received, the process waits for a predetermined time (for example, 50 μs) in the subsequent step 222, and then, in step 224, one bit of return data (return signal) is sent from the transmission circuit 53 to the transmission line 3 in current mode. This current mode return signal is received by the central processing unit (step 112 in FIG. 10), which inverts the output voltage mode from the central processing unit (step 118 in FIG. 10).

Next, in step 226, it is determined whether the return signal is "1". If “1”, process step 228
If it is "0", the process advances to step 230.

In step 228, the voltage mode signal of the transmission line 3 is received, and it is determined whether or not this received signal matches the return signal sent immediately before. If they match, step 2
Since the return signal sent out at step 24 was received by the central processing unit and the voltage mode of the transmission line was inverted, the transmission of that bit was performed normally. In this way, each terminal device checks the transmission of only the "1" level return signal for monitoring data, and does not check the transmission of the "0" level return signal, thereby making it possible to transmit multiple terminals. Can be set to the same address. By doing this, for example, a 1-bit signal is sufficient for switch on/off information, so multiple switches connected to different terminals can be assigned corresponding to the bits of the same address, and one terminal This eliminates the waste of bits that are not assigned a load, such as when one address is occupied.

Furthermore, the number of terminals for the same number of loads can be reduced, and the frequency of collisions in random transmission can be reduced, thereby improving response speed.

In step 230, it is determined whether all bits of the return signal have been successfully transmitted. If all bits of the return data including the self address, monitoring data and marker bit signal have not been returned yet, step 21
Returning to step 6, the processes of steps 216 to 230 are repeated for the next bit (return signal). On the other hand, if all bits have been returned, the return processing is completed and the process returns to step 202.

If the returned signal and the received signal do not match in content in step 228, that bit of the returned data (returned signal)
was not correctly received by the central processing unit, the process returns directly from step 228 to step 202. In this case, the central processing unit cannot obtain return data of a predetermined number of bits (step 140 in FIG. 10). Therefore, the startup cancellation process (step 142) is skipped.
Central startup processing is executed again. Therefore, the terminal device has to perform the return process again in response to this, and the central activation process of the central processing unit and the corresponding return process of the terminal device are repeated until the return data is transmitted normally. It turns out.

Terminal Start-up Process During the terminal start-up process, in step 256, the CPU waits for reception of a synchronization signal sent out in the process of step 150 or step 156 in FIG. 10 of the central processing unit. When this synchronization signal is received, the process proceeds to step 258 for a predetermined period of time (
After waiting for 50 μs, for example, in step 260, one bit of terminal data (terminal signal) is sent from the transmitting circuit 53 to the transmission line 3 in current mode. This current mode terminal signal is received by the central processing unit (step 160 in FIG. 10), and the voltage mode sent from the central processing unit to the transmission line is inverted (step 164).

Next, in step 262, it is determined whether the terminal signal is 1 bit in the self address. If it is the self address, the process proceeds to step 262, and if it is not the self address, the process proceeds to step 264. In step 264, it is determined whether the terminal signal is "1".
If so, the process proceeds to step 268, and if it is "0", the process proceeds to step 270.

In step 268, the voltage mode signal of the transmission line 3 is received, and it is determined whether this received signal matches the terminal signal sent immediately before. If they match, step 2
Since the terminal signal sent out at 60 was received by the central processing unit and the voltage mode of the transmission line was inverted, it means that the transmission of that bit of the terminal data was carried out normally.

In the next step 270, it is determined whether normal transmission of all bits of the terminal signal including the self address, monitoring data, and marker bit signal has been completed. If terminal signal transmission for all bits has not been completed, step 25
Returning to step 6, the processes of steps 256 to 270 are repeated for the next bit of terminal data (terminal signal). On the other hand, if signal transmission for all bits has been completed, this terminal activation process is completed and the process returns to step 202.

On the other hand, if the contents of the current mode signal transmitted in step 260 and the voltage mode signal inspected in step 268 are different, it is determined that the current mode signal sent from the terminal was not correctly received by the central processing unit. Then, the cyclic processing is interrupted in step 268 and the process returns to step 202. In this case, the startup data for the terminal device remains as is, so when the central processing unit sends a start signal for terminal startup (step 150 in FIG. 10) and the process advances from step 202 to step 250, this step At step 250, it is determined that activation data is present, and this terminal activation process is executed again. That is, this terminal activation process is repeated until the activation data is normally transmitted to the central activation process.

[Application Example of the Invention] In the above description, an example has been described in which the present invention is applied to a signal transmission system in which a voltage mode signal is transmitted from the central processing unit side and a current mode signal is transmitted from the terminal device side. The method of the present invention is also applicable to mutual signal transmission in voltage mode. However, in this case, a marker bit signal of level "1" is sent from the terminal, and the central processing unit can detect a short circuit in the transmission line based on the fact that this "1" is not detected.

The present invention is also applicable to a system that does not convert a current mode signal from a terminal into a voltage signal, such as that disclosed in Japanese Patent Publication No. 61-3155.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a remote control system according to an embodiment of the present invention, FIG. 2 is a functional block diagram of a central processing unit in the system of FIG. 1, and FIG. FIG. 4 is a functional block diagram of the terminal device in the system of FIG. 1. FIG. 5 is a functional block diagram of the repeater in the system of FIG. 1. , a timing chart for explaining the operation of the repeater in the system of FIG. 1, FIG. 7 is a flowchart for explaining the operation of the repeater in the system of FIG. 1, and FIG. 8 is a timing chart for explaining the operation of the repeater in the system of FIG. 9 is a circuit diagram showing a specific example of the terminal device in FIG. 4; FIG. 10 is a flowchart showing the operation of the central processing unit in FIG. 8; FIG. 11 is a circuit diagram showing a specific example of the terminal device in FIG. , FIG. 9 is a flowchart showing the operation of the terminal device, and FIG. 12 is a detailed format for each operation mode of the transmission signal in the device of FIG. 1. 1: Central processing unit 3: Transmission line 5-1. 5-2. 5-3. ...: Terminal 8: Repeater 9: Load device 11.51: Signal processing circuit 12: Current detection circuit 15: Differential circuit 16: Rise detection circuit 18゜19゜20゜21゜PI PV 55: Synchronous circuit 57 :Flip-flop circuit 53:Transmission circuit 61.71:CPU:Current mode signal:Voltage mode signal

Claims (1)

[Claims] In a signal transmission system in which a central processing unit and a plurality of terminal devices are connected via a two-wire transmission line, the terminal device always transmits “0” in data transmitted from the terminal device.
1. A signal transmission system comprising: a signal processing means that includes a bit having a predetermined value among "1" and "1".