JPH0265413A - Muting circuit - Google Patents

Abstract

PURPOSE:To eliminate a shock noise by giving a time constant with a resistor and a capacitor in the case of transition to the state detecting digital 0, applying a bias to 1st and 2nd transistors(TRs), turning on them, thereby applying muting. CONSTITUTION:When an input signal is digital 0, and output point (a) of a digital 0 detection circuit 6 is switched from 'high' to 'low' with a time constant alpha. Since a capacitor 10 is connected to a positive power supply from a midpoint between resistors 11, 12 connecting in series with the output of the digital 0 detection circuit 6, a potential at a point (b) of the base of a TR 18 connected through the resistor 14 is decreased with a time constant determined by the capacitor 10 and the resistor 11. Since muting is applied slowly in a time beta after the output of the digital 0 detection circuit 6 goes to a low level, the shock noise is almost eliminated.

Description

[Detailed Description of the Invention] Industrial Field of Application This invention enables a D/A conversion system for converting digital signals to analog signals to avoid noise and to obtain a good S/N ratio. This relates to muting circuits.

Conventional Technology A conventional example is shown in FIG. FIG. 5 shows a circuit that uses the output of the digital O detection circuit 6 as it is;
The logic output of the detection circuit 6 is "high" when the input signal becomes digital 0, and "low" when the input signal is not digital ○.
shall be. By setting the resistor 25 to a smaller value than the resistor 24.28, the output of the digital 0 detection circuit becomes 6.
When it goes high, transistor 27 is forward biased by the ratio of resistor 25 and resistor 26, and mutes the signal line. Reverse bias is applied and muting is canceled. Resistors 28 and 29 are signal line dividing resistors, and resistor 26 is for improving distortion.

Problems to be Solved by the Invention Although the conventional circuit shown in FIG. 6 is simple and rational, when muting is applied, the transistor suddenly turns on, producing a shock sound on the signal line. It is a problem that such an abnormal sound is produced even though the input signal is 0.

Means for solving the problem In order to solve such problems, the present invention uses a digital
It is equipped with a digital ○ detection circuit that detects a signal, receives the output of the digital 0 detection circuit, and is equipped with a first buffer transistor and a second muting transistor, and when the state shifts to a state in which digital /L10 is detected. teeth,
A resistor and a capacitor provide a time constant, bias the first and second transistors, turn them on and perform muting operation, and when a signal other than digital/L10 comes in, a diode is used to increase the speed. When muting is applied by the configuration in which the first transistor is cut off and the muting operation of the second transistor is canceled, there is no shock noise at all by applying the muting with a certain time constant, and When muting is canceled, it is canceled instantly, so high-quality signal playback is possible without distorting the sound.

Function: By having the configuration of the present invention, it is possible to provide a D/A conversion system that does not produce shock noise and can obtain a high S/N ratio.

EXAMPLES Hereinafter, examples of the present invention will be explained with reference to the drawings. Second
The figure shows an example of a D/A conversion system.

A digital input signal 1 is sent to a signal processing circuit 2, a digital filter 3. D/j"!J exchange u4, o-y<Sfilter 5
The signal passes through the signal processing circuit 2 to become the analog output signal 8, but apart from this flow, it passes from the signal processing circuit 2 to the digital 0 detection circuit 6, and the muting circuit 7 mutes the analog signal. . Utilizing the delay while the digital signal passes through the digital filter 3 and the D/A converter 4, the digital ○ detection circuit 6 detects 0 of the digital signal before it becomes an analog signal.
is detected and the muting circuit 7 is controlled. FIG. 1 shows an embodiment of the muting circuit of the present invention. FIG. 3 shows voltage waveforms at various parts when the signal becomes digital /F10, and FIG. 4 shows voltage waveforms at various parts when the signal changes from digital 0 to a signal other than digital 0.

In FIG. 1, the logic of the output of the digital ○ detection circuit 6 is as follows:
When the digital signal reaches Q, it is “low”, and when it is other than 0, it is “high”
Assume that the transition from "high" to "1 low" has a certain time constant α, and the transition from "low"' to "high" does not have a time constant and changes instantaneously.The input signal changes to digital ○. When this happens, the six output points of the digital/L10 detection circuit 6 switch from "high" to "6 low" with a time constant α as shown in FIG. 3a.

Since the capacitor 1o is connected to the positive power supply between the resistor 11 and the resistor 12 which are connected in series to the output of the digital/i10 detection circuit 6, the base b of the transistor 18 connected through the resistor W14 is The potential at the point decreases as shown in Figure 3 with a time constant determined by the capacitor 10 and resistor 11. When the base potential of the transistor 18 biased by the diode 17 and the resistors 15 and 16 drops to 0.6 to 0.7 volts between the base and emitter, the transistor 18 turns on and the transistor 2o is turned on through the resistor 20. A current is supplied to the base, and the potential at the 0 point rises as shown in FIG. 3C, turning on the transistor 20 and applying muting through the resistor 21 connected from between the resistors 22 and 23 of the signal line. In this way, the output of the digital) vo detection circuit is low.
After that, the muting starts slowly and there is almost no shock sound.

Conversely, when the input signal changes from 0 to a signal that is not ○, the output of the digital O detection circuit instantly changes from "low" to "1 high" as shown in Figure 4 a.The potential at point a is 11
．． Diode 13 connected to bypass 12
, and further through resistor H14, it immediately reaches the base of transistor 18, so transistor 18 instantly goes into the cut-off state as shown in Figure 4, and through resistor 2o, it reaches the base of transistor 18 as shown in Figure 4C. The potential drops and transistor 20 immediately enters the cut-off state. The resistor 19 is a resistor that applies a negative bias to prevent distortion rate adjustment due to leakage current of the transistor 18. In this way, when the input signal is no longer digital O, this muting circuit immediately cancels muting, but the digital signal passes through the digital filter and D/A converter before being converted to an analog signal. , muting does not destroy the first part of the signal.

Note that the above explanation is for one channel, but if a plurality of muting transistors are used, a multi-channel muting circuit can be obtained.

Effects of the Invention As described above, the present invention provides a muting circuit that enables high-quality muting without squeaks, crackling sounds, etc., and provides a higher SIN ratio.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the muting circuit of the present invention, Fig. 2 is a block diagram of an embodiment of the D/A conversion system, and Fig. 3 is a circuit diagram of an embodiment of the muting circuit of the present invention. digital)
Figure 4 shows the voltage waveform diagram of each part when the voltage becomes 1.10.
FIG. 6 is a circuit diagram of an embodiment of a conventional muting circuit. 1...Digital input signal, 2...Signal processing circuit, 3...Digital filter, 4...
...D/AF conversion RL 5...Low pass filter, 6...Digital ○ detection circuit, 7.
... Muting circuit, 8 ... Analog output signal, 11.12, 14, 15° 16.19, 2
0,21.22,23,24゜25.28.28.29
...Resistor, 13.17...Diode, 10...Capacitor, 1B, 20°27.
...Transistor. Name of agent: Patent attorney Shigetaka Awano and 1 other person f1
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-J15$413, /7---Die it' lθ -m-Koshite'〉4.20---) U〉Jister 1 Fig. 2z3 / I Fig. 3

Claims (1)

[Scope of Claims] A digital O detection circuit that detects a digital O signal is provided, and a first
buffer transistor and a second muting transistor, and when transitioning to a state in which digital O is detected, bias is applied to the first and second transistors by providing a time constant with a resistor and a capacitor. When a signal other than digital O is input, the first transistor is cut off at high speed using a diode.
A muting circuit characterized in that the muting operation of the second transistor is canceled.