JPH0263297B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to stably improve the performance of a MOS type semiconductor device, and particularly to solve problems associated with miniaturization.

In order to increase the speed and density of MOS type semiconductor devices,
Gate lengths are becoming shorter year by year, leading to so-called short channels. However, along with this, it has emerged as an important issue how to solve the so-called short channel effect, such as increased variation in threshold value V _T , decreased drain breakdown voltage, and even increased drain leakage current.

For example, with current technology, if a gate pattern with a width of 3 microns is formed on a mask, when it is transferred onto polysilicon, the width will be approximately 2.5 microns, and the depth of the source/drain diffusion layer (approximately 0.5 microns). The effective channel length is approximately 1.5 microns, which is calculated by subtracting twice the actual channel length (microns). In order to miniaturize the gate pattern on the initial mask, it is necessary to improve the mask pattern and effective channel length, such as improving the transfer accuracy in photolithography and etching, and starting technology to form shallow source/drain diffusion depths. The difference must be reduced. Various improvements have been made in this direction, for example, even with arsenic ion implantation to form shallow junctions, the junction depth x _J is approximately 0.25 to 0.3 microns, and 2x _J
This results in a difference of 0.5 to 0.6 microns, which together with the transfer error creates a difference of 1 micron. Even with this, the n-channel is better because it can use an impurity with a small diffusion coefficient, such as arsenic, but the p-channel uses an impurity with a large diffusion coefficient, such as boron, so it is more difficult to shorten the gate length. Therefore,
There are major obstacles to miniaturization of complementary MOS integrated circuits using both p and n channels.

In the present invention, an oxide film is deposited on the gate, impurities are introduced at a position a desired distance from the gate, and the spread of the source/drain diffusion layer into the channel region directly under the gate is minimized.
The goal is to reduce the difference between the effective channel length and the gate length to obtain a miniaturized MOS type semiconductor device with less short channel effect.

The configuration of the present invention will be explained below with reference to FIGS. 1 to 7. Although an example of an n-channel will be described, the present invention can be similarly applied to a p-channel and therefore also to a complementary MOSIC.

(Fig. 1) After forming a field oxide film 2 on a desired region of the surface of a p-type silicon substrate 1 by selective oxidation, a gate oxide film 3 is formed on the exposed surface of the substrate 1 to a thickness of about 500 Å by thermal oxidation. Let it grow.

(FIG. 2) Next, polycrystalline silicon (hereinafter abbreviated as polysilicon) 4 which is to become a gate is formed to have a desired gate length _l.sub.G. Preferably, plasma or reactive sputter etching with Freon gas is used to obtain highly accurate dimensions for the mask pattern.

(FIG. 3) Next, gate oxide film 3 is etched off using polysilicon 4 as a mask, and then film 5 is deposited or coated on the surface of substrate 1 including polysilicon 4. As the film 5, a vapor-grown oxide film, which is necessary in the next step, will be used. The thickness of the coating 5 is t _f defined by the flat portion as shown, but there is a portion thicker than the width Δ _f near the end of the polysilicon 4 . This is because the film 5 also adheres and grows on the end surface 4a of the polysilicon 4, and approximately Δ _f
can be said to be equal to Δ _f .

(Fig. 4) Next, to form the source/drain, phosphorus ions of the opposite conductivity type as the substrate 1, such as phosphorus ions, are heated at an accelerating voltage such that the range R _p is slightly larger than the thickness t _f of the coating 5. When ions are implanted at , implantation layers 6 and 6' are formed at positions approximately Δ _f away from polysilicon gate 4. The value of _Δf is selected to be approximately 0.4 to 0.5 microns.

(FIG. 5) Next, heat treatment is performed at a temperature of about 1000° C. to expand the n-type injection layers 6, 6' and form diffusion layers 61 and 61' reaching the ends of the gate 4. These diffusion layers 61, 61' are source/drain diffusion regions. Source/drain diffusion layer 61, 61'
The effective channel length L _eff is the distance between the gate length l _G
It is formed to be about 0.1 to 0.2 microns shorter. Since a vapor-phase grown oxide film is used as the coating 5, impurity diffusion in the oxide film is much slower than that in polycrystalline silicon, for example.By heat treatment after ion implantation, the positional relationship in which the source/drain region just reaches the gate edge can be adjusted. Can be specified precisely.

(Fig. 6) Next, the contact hole 7 in the coating 5,
7' is provided. Although not shown, a contact opening to the polysilicon 4 is also formed at the same time.

(FIG. 7) Next, metal wiring lines 8 and 8' for connection between circuit elements are formed. Although not shown, metal wiring for signal transmission to the polysilicon gate 4 is also formed at the same time.

With the above steps, the manufacturing process of the MOS type semiconductor device is completed.

According to the present invention, an oxide film is deposited on the gate, impurities are implanted at an acceleration voltage that is approximately the same as or greater than the thickness of the oxide film, and the source/drain layer is located at a position separated from the gate by a predetermined distance. Therefore, even if the source/drain layer is expanded by heat treatment, the effective channel length L _eff will not become too small. That is, gate length l _G and effective channel length
The difference in L _eff can be made extremely small. Therefore, the difference between the design dimension of the gate length on the mask and the effective channel length is almost determined only by the photolithography and etching steps used to form the gate.
In this way, the fact that the effective channel length is closer to the design dimension than in the past means that the design dimension can be made smaller at the beginning. The present invention brings about effects such as increased speed due to reduced capacity. Furthermore, as is clear from FIG. 5 onward, since the overlapping portion between the source/drain 61, 61' and the gate 4 is extremely small, the capacitance between the gate and source and between the gate and drain is small. Since gate-drain capacitance has a negative effect on high frequency characteristics, the MOS type semiconductor device according to the present invention also has excellent high speed performance.

These effects were brought about by forming the injection layers 6, 6' at a distance of Δ _f from the gate 4;
The present invention has the advantage of high precision and good controllability in mask alignment because it is a self-aligning method that does not rely on the operator's senses such as side etching. This is an important feature.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views of a semiconductor device, respectively, for explaining a method according to an embodiment of the present invention. 1...Substrate, 2...Field oxide film, 3...
Gate oxide film, 4... polysilicon, 5... film, 6, 6'... injection layer, 61, 61'... diffusion layer.

Claims (1)

[Claims] 1. A step of forming a gate oxide film and a gate on a semiconductor substrate, a step of depositing an oxide film of a desired thickness on the semiconductor substrate including the gate, and a step of depositing the oxide film to a desired thickness from a direction perpendicular to the surface of the substrate. a step of implanting impurities at an accelerating voltage such that the distance is equal to or greater than the thickness of the oxide film to form a source/drain at a position away from the edge of the gate, and placing the source/drain just at the edge of the gate; 1. A method for manufacturing a MOS type semiconductor device, comprising the step of heat treatment to achieve the desired temperature.