JPH0263231A - Digital signal multiplex circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of n-set of multiplex circuits each connecting to m-set of signal lines and to simplify wiring among circuit components by inputting n-set of channels each consisting of m-set of channels in parallel with m-set of n-stage parallel/serial shift registers and multiplexing m-set of signals subjected to serial processing for n-set. CONSTITUTION:m-Set of signals of a bit rate f0 given to n-set of channels C1-Cn respectively are inputted to shift registers S1-Sm in parallel by n-set of lines each. The signals on the channels C1-Cn become m-line serial signals b1-bm by n-channel by giving serial shift to the signals in each shift register by a frequency of f0Xn. When the m-line of signals b1-bm are multiplexed by a serial/ parallel conversion circuit (PS) T, a multiplex signal (a) by n-channel each consisting of m-bit with a bit rate of f0XnXm is produced. Thus, the wiring is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a digital signal transmission circuit in which information channels are separated and multiplexed for each predetermined number of bits. In particular, it relates to the circuit configuration of the multiplex circuit.

〔overview〕

The present invention converts an n-channel input with continuous n bits as an information unit and a bit rate of fo into an m-channel signal with a bit rate of f and Xn, and then , the information unit is m consecutive bits, and the bit rate is f0×n×m.
In the means for generating channel multiplexed signals, the wiring configuration can be simplified by using m shift registers with n stages in the first stage and a parallel-to-serial conversion circuit in the second stage.

[Conventional technology]

FIG. 3 shows the configuration of a conventional digital signal multiplexing circuit.

The first signal of each of the n channels 61 to C7 is connected to an n:l serial-to-parallel conversion circuit (hereinafter referred to as a PS circuit).

) U1, and similarly, the second to mth signals are distributed and input to each of the PS circuits U2 to PS circuits. The respective input signals are multiplexed n:l by the PS circuit, -U. These m output signals are further multiplexed into one by an m:1 PS circuit, and one channel m
A signal a for n channels composed of bits is generated.

[Problem that the invention seeks to solve]

Such conventional digital signal multiplexing circuits require complicated circuit connections between each channel C3-C, . and PS circuits U1-U, so they have the disadvantage of requiring complicated wiring. be.

The present invention aims to eliminate such drawbacks, and aims to provide a digital signal multiplexing circuit with simpler wiring than the conventional example.

[Means for solving problems]

In the present invention, m consecutive bits are used as an information unit, and the bit rate is f. The first digital signal is inputted in parallel with an n-channel first digital signal, and the first digital signal is converted into an m-channel second digital signal with a bit rate of f0×n, using consecutive n bits as an information unit. The conversion means and this n-channel second digital signal are input in parallel, m consecutive bits are used as an information unit, and the bit rate is f. In the digital signal multiplexing circuit, the first converting means has a bit rate f.

m shift registers each having n stages of registers shifted by xn shift signals, each of m β (1≦β≦n) stage registers has m
The first bit signal of each of the first digital signals is provided.

[Effect]

The information unit is m consecutive bits, and the bit rate is f.

The n-channel first digital signal is input in parallel to m shift registers having n stages of registers shifted by a shift signal with a bit rate f0xn, and n ! Each of the β-th bit signals of the m second digital signals is applied to each of the (1≦!≦n) stages of registers, and consecutive n bits are used as an information unit, and the bit rate is f.

This first digital signal is converted into a second digital signal of m channels with xn. The n-channel second digital signals are input in parallel to a parallel-to-serial conversion circuit, with consecutive n bits as an information unit and a bit rate of f. x
It is converted into a 1-channel third digital signal of nXm.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. FIG. 2 is a timing chart relating to the signals in the numbered part of the first diagram.

In this embodiment, as shown in FIG. 1, the bit rate [.

It is equipped with m shift registers having n stages of registers that are shifted by xn shift signals, where m continuous bits are the information unit, and the bit rate is f. n-channel first digital signals are input in parallel, and this shift register inputs the first bit signal of the m second digital signals to each of the n β (1≦β≦n) stage registers. Shift registers 81 to S are first converting means for converting the first digital signal into an m-channel second digital signal with continuous n bits as an information unit and a bit rate of foxn. ,and,
These n-channel second digital signals are input in parallel, consecutive n points are used as information units, and the bit rate is r.
. A parallel-to-serial conversion circuit T is provided as a second conversion means for converting into a third digital signal of one channel of XnXm.

Next, the operation of this embodiment will be explained based on FIGS. 1 and 2. n channels C1-C,.

n signals of each of m pit-rays +-f0 are input in parallel to shift registers 81 to 81 to S, respectively. f in this shift register. By shifting the signals 01 to C7 in series at the frequency xn, the signals 01 to C7 become serial signals for m channels of n channels -bm. Furthermore, these m signals ~b1
When multiplexed by the PS circuit, the pit rate f0×n×m
A multiplexed signal a for n channels each consisting of m pits is generated.

〔Effect of the invention〕

As explained above, according to the present invention, one set of m channels 1
Since n sets are input in parallel to m n-stage parallel-serial shift registers, and m serialized signals from the n sets are multiplexed, the circuit configuration of a multiplex circuit of m sets of n sets is as follows. This has the effect of simplifying the wiring between circuit elements.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. FIG. 3 is a block configuration diagram showing the configuration of a conventional example. 81~8...Shift register, T, U+ -U-.
...Parallel-serial conversion circuit (PS circuit), a...Multiple signal (n multiplex of m bits), b, ~b,...Multiple signal (n
multiplex), CI-c,...input signal (in units of m), d
, ...Medium speed clock (frequency = f, Xn), d2.
...Low speed clock (fo). Patent applicant: NEC Corporation, -1, agent: Naotaka Ide, patent attorney
1 bit-------------=-id2 -I-----1 11-i to...乍shoulder 2 Moxibustion Eiji lecture fan 3 ro

Claims (1)

[Claims] 1. First digital signals of n channels with continuous m bits as an information unit and a bit rate of f_0 are input in parallel; consecutive n bits as an information unit and a bit rate of f_0× A first converting means converts the first digital signal into a second digital signal of m channels, which is n, and inputs the second digital signal of n channels in parallel, and sets the continuous m bits as an information unit, and the bit rate is is f
and a second converting means for converting into a third digital signal of one channel of _0×n×m, the first converting means converts n to a third digital signal of one channel of bit rate f_0×n. It has m shift registers each having registers in stages, and this shift register has m l (1≦l≦n) stages.
A digital signal multiplexing circuit characterized in that the l-th bit signal of the m first digital signals is applied to each of the registers in the stage.