JPH026256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Viterbi decoding circuit, and more particularly to a Viterbi decoding circuit that operates on burst-like convolutionally encoded data sequences.

[Technical background of the invention and its problems]

In satellite communications and the like where wireless power is limited, error correction codes are used to save wireless power, and error correction technology using maximum likelihood estimation, which has a large coding gain, has recently been attracting particular attention.

Figure 1 shows earth transmitting stations 2a and 2 via satellite 1.
This is a multiple access communication form in which signals are transmitted from stations b, ...2i, ... to the earth receiving station 2r. In this case, on the transmitting side, as shown in FIG.
is encoded by an error correction encoder 4, and a modulated signal is sent out via a modulator 5. On the other hand, on the receiving side, a demodulator 6 demodulates the received signal, and an error correction decoder 7
The decoded data d is obtained by decoding at the .

In such satellite communication systems, time division multiple access is often used in order to effectively use the transmission power on the ground and on the satellite. Each earth transmitting station 2 in Figure 1
From a, 2b, ..., 2i, ..., Fig. 3 A, B,
Burst signals 3a, 3 as shown in ..., I, ...
a', 3b, 3b', . . . , 3i, 3i', .

Therefore, when convolutional encoding and Viterbi decoding are used as error correction encoding methods, it is necessary that the Viterbi decoder on the decoding side operates accurately for such burst-like received data. It won't happen.

Now, the Viterbi decoding method uses a grid diagram (hereinafter referred to as a trellis) as shown in Figure 4 that visually represents the structure of the target convolutional code, that is, all possible encoding code sequences (usually called paths). ), by sequentially determining the encoding code sequence that is probabilistically closest to the actually received symbol sequence (this is called the maximum likelihood path). It decodes transmitted symbols.

More specifically, at each decoding step, for each internal state on the trellis, one surviving path, i.e., one of all possible paths starting from the initial state and leading to that state, is connected to the actual received signal sequence. The path with the minimum distance (this is called a path metric) and the path metric of that path are sequentially determined and stored to refer to the algorithm.

However, a distinctive feature of the Viterbi algorithm is the fact that the sufficiently past portions of the surviving paths stored for each internal state gradually converge to a single common path; Decoding is performed by directly using the oldest common bit of the surviving path (assumed to be stored in the form of information bits) stored in an appropriate finite length for each internal state as the decoding output. It will be done.

In this case, it should be noted that a decoding delay corresponding to the storage length of the surviving path occurs in the decoded output.

Now, if the input data to the decoder is generated continuously, the occurrence of such a decoding delay is not considered to be much of a problem, but if the input data is a burst-like data sequence as shown in Figure 3, A special new problem arises when receiving .

To explain this point, refer again to the waveforms in FIG. 3. R in the figure is a multiplexed data sequence that reaches the receiving station of interest, and it is now assumed that one frame of this theta sequence is composed of n bursts. Individual bursts constituting one frame may be transmitted from different transmitting stations, or one transmitting station may have multiple channels and occupy multiple bursts within one frame. , from the decoder's standpoint, they can be considered independent of each other.

The operation of the Viterbi decoder in such a case is to perform decoding by treating each burst signal occupying the same position in each frame as a series of related data sequences. Therefore, the Viterbi decoder independently decodes n types of data sequences, each in the form of a burst, and at this time, it is necessary to decode them in a time-division manner according to the form of the received signal. It is something.

By the way, such an operation is possible by controlling only the path metric storage circuit or the surviving path storage circuit, which stores path metrics and surviving paths, using an appropriate control signal that indicates the burst position, among the main circuits that make up the Viterbi decoder. You can see that it is possible by doing this.

However, as mentioned above, new difficulties arise due to the decoding delay in Viterbi decoding, for example, when one transmitting station occupies multiple bursts in one frame.

FIG. 5 shows, as a specific example, that one transmitting station
The relationship between the transmission data sequence α, encoded data sequence β, and decoded data sequence γ when the first and second bursts are occupied in a frame is schematically shown.

Because the Viterbi decoder considers and decodes each burst signal at the same position in each frame as a series of related data sequences, and due to the unavoidable signal delay in Viterbi decoding, the final decoded data sequence becomes a state like γ.

That is, when the signal of the first burst in the first frame, which is indicated by diagonal lines in the encoded data β, is decoded, the decoding result cannot fit within the first burst in the first frame of the decoded data series γ, and a portion of the signal is is decoded separately into the first burst of the second frame. Therefore, the temporal order of the original transmission data sequence α is destroyed, and such a decoding pattern is extremely inconvenient for the receiving side when performing various data processing thereafter, and subsequent handling becomes difficult. There were flaws.

[Purpose of the invention]

This invention was made based on the above circumstances, and is such that transmission data corresponding to one burst in one frame is separated into two consecutive frames for a time-division multiplexed burst-like input data sequence. It is an object of the present invention to provide a Viterbi decoding circuit that can correctly decode one burst without performing additional decoding and facilitates subsequent signal processing.

[Summary of the invention]

This invention provides a branch metric generation circuit,
In addition to the ACS circuit, the path metric storage circuit, and the surviving path storage circuit, it is equipped with an editing circuit that inputs the decoded data output from the surviving path storage circuit and outputs the aligned decoded data. The present invention is characterized in that burst signals are decoded by regarding them as a series of related data sequences, and each burst of the transmitted data sequence is correctly decoded as one burst on the decoding side.

〔Effect of the invention〕

This invention provides a Viterbi decoding circuit that operates on time-division multiplexed burst-like input data sequences with a simple editing function, so that one burst of transmitted data in one frame can be correctly processed as one burst on the decoding side. This allows the data processing function after decoding to be improved.

Furthermore, such editing processing is performed in burst units that constitute a frame in complete synchronization with the original decoding operation of the Viterbi decoding circuit that operates on burst-shaped input data. The present invention not only can easily accommodate changes in the number of bursts constituting a frame, but also has the advantage of being able to minimize additional circuitry for data editing.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 6, 11 and 12 are input terminals for a received signal and a burst control signal, respectively, and 13 is an output terminal for outputting aligned decoded data after editing.

The Viterbi decoding circuit of this embodiment, generally designated by the reference numeral 20, includes a branch metric generation circuit 21,
ACS circuit 22, path metric storage circuit 23,
It is composed of a surviving path storage circuit 24 and an editing circuit 25.

In the circuit shown in FIG. 6, a branch metric generating circuit 21 receives the received signal supplied from the input terminal 11 and generates a branch metric.
The ACS circuit 22 inputs this branch metric and the path metric output from the path metric storage circuit 23, and performs addition, comparison, and selection on these.
By performing the calculation, an updated path metric and a surviving path designation signal are generated and output to the path metric storage circuit 23 and the surviving path storage circuit 24, respectively.

In the path metric storage circuit 23,
The updated path metrics calculated by the ACS circuit 22 are stored as input signals, and are read out in the next decoding step and sent to the ACS circuit 2.
2 as one of the input signals.

The surviving path storage circuit 24 operates in synchronization with the path metric storage circuit 23, and the surviving paths are read out in synchronization with the path metrics being read out from the path metric storage circuit 23. At this time, the ACS circuit 22 outputs the surviving path. An updated surviving path is designated in accordance with the surviving path designation signal, and the selected surviving path is again input to the surviving path storage circuit 24 and stored.

Note that this series of circuit operations is controlled by a burst control signal input through the input terminal 12, and in particular, by controlling the path metric storage circuit 23 and the surviving path storage circuit 24, each frame is The above decoding operation is performed by regarding each burst signal at the same position as a series of related input data sequences.

In particular, the editing circuit 25 plays an important role in this Viterbi decoding circuit, and arranges the decoded data based on the decoded data output from the surviving path storage circuit 24 and the burst control signal from the input terminal 12. The decoded data that has been sorted out is output from the output terminal 13.

The operation of the editing circuit 25 will be described in detail below.
Referring again to the decoded data sequence in Figure 5, when normal decoding is performed, the transmitted data corresponding to one burst of one frame is separated across two frames, as shown in γ in the figure. Since the data is decoded in the same state, it is necessary to combine the separated and decoded data by appropriate means as shown in δ in the figure.

FIG. 7 shows the principle for realizing such an editing function, and shows that it can be performed by controlling one memory circuit. In FIG. 7, in order to make the explanation accurate, the length of one decoded burst is r, and the decoded data string before editing is separated into (rd) and d pieces over two frames. It is assumed that Here, it is assumed that the decoding up to the k-th frame has been completed and the decoding of the (k+1)-th frame has newly started. Furthermore, since the editing processing for each burst constituting a frame is the same, the explanation will focus on the processing for one burst.

Therefore, it is assumed that the storage circuit corresponding to the editing circuit 25 stores unprocessed decoded data corresponding to the k-th frame shown in FIG. 7a.

Here, in synchronization with the start of decoding of the (k+1)th frame, one time slot length of each decoded data is divided into two as shown in FIG. If we start from address (d+1), go back to address 1 via address r, and then execute to address d, on the other hand, we start writing from address 1 and write to the last address r, resulting in the kth and ( The decoded data separated across the (k+1)th two frames can be accurately joined.

That is, in the first half of reading from address (d+1) to address r, the k-th frame decoded data is read out, and in the subsequent second half of reading from address 1 to address d, newly captured data is (k+1).
The portion of the decoded data of the frame that is connected to the previous frame is read out via writing to the storage circuit, and as a result, the decoded data that was separated over two frames is correctly converted into one burst of transmitted data. It can be arranged as follows.

At the end of one cycle of such circuit operation, the unprocessed decoded data of the newly decoded (k+1)th frame is stored in the storage circuit in the same way as when editing started. By sequentially performing the above-described editing processing, sorted decoded data can be obtained.

Specifically, such an editing circuit can be easily realized by using RAM (random access memory) with an appropriate capacity.

Further, processing for different bursts constituting one frame can be performed by using the burst control signal that controls the original decoding operation as is, as in the case of the path metric storage circuit 23 and the surviving path storage circuit 24. This can be realized by controlling only the storage area of the storage circuit. Note that, as can be seen from the above explanation, such editing processing is performed in complete synchronization with the original Viterbi decoding operation.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without changing the gist.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the form of multiple access communication using satellites, Figure 2 is a schematic diagram of the transmitter and receiver sides using error correction coding, and Figure 3 is an explanation of time division multiple access. Figure 4 is a concrete example of a trellis showing the structure of a convolutional code, and Figure 5 is a waveform diagram of a burst signal when one transmitting station occupies the first and second bursts in one frame. FIG. 6 is an explanatory diagram showing the relationship between a transmitted data series, an encoded data series, an unaligned decoded data series, and an edited decoded data series. FIG. 6 is a block diagram showing the configuration of an embodiment of the present invention. Figure 7a,
FIG. 1b is an explanatory diagram showing the relationship between writing and reading when the editing circuit is configured by a storage circuit. 1: Satellite, 2a, 2b...2i...: Earth transmitting station,
2r: earth receiving station, 3a, 3b...3i...: burst signal, 4: error correction encoder, 5: modulator, 6:
demodulator, 7: error correction decoder, 11, 12: input terminal, 13: output terminal, 20: Viterbi decoding circuit,
21: Branch metrics generation circuit, 22:
ACS circuit, 23: path metric storage circuit, 2
4: Survival path storage circuit, 25: Edit circuit.

Claims (1)

[Claims] 1. A branch metric generation circuit that receives a received signal as an input and generates a branch metric, and a branch metric output from the branch metric generator circuit and a path metric output from a path metric storage circuit as input. an ACS circuit that generates an updated path metric and a surviving path designation signal by performing addition, comparison, and selection operations thereon, and outputs these to the path metric storage circuit and the surviving path storage circuit, respectively; A path metric storage circuit that stores path metrics as input signals and outputs these values in the next decoding step to be used as one of the input signals to the ACS circuit, and a path metric storage circuit that stores surviving paths in synchronization with the operation of this path metric storage circuit. A surviving path that selects an updated surviving path based on the surviving path designation signal outputted from the ACS circuit and stores it again, determines the decoding result from the oldest bit of these surviving paths, and outputs the value as decoded data. the path metric storage circuit, comprising: a storage circuit; and an editing circuit that receives the decoded data output from the surviving path storage circuit and outputs the aligned decoded data;
The survival path storage circuit and editing circuit are controlled by a burst control signal, and decode each burst signal at the same position in each frame as a series of related data sequences, and decode each burst of the transmitted data sequence on the decoding side. However, the Viterbi decoding circuit is characterized in that it correctly decodes one burst. 2 Using a storage circuit as the editing circuit, one time slot of each decoded data is divided into two in synchronization with the start of decoding of the burst of interest in each frame, and the first half is set to read mode and the second half is set to write mode, and the corresponding one of the previous frame is 2. The Viterbi decoding circuit according to claim 1, wherein data is spliced by sequentially reading data in the latter half of a burst and sequentially writing data in the first half of the burst of interest in the current frame and then reading it again. 3. The Viterbi decoding circuit according to claim 2, wherein a random access memory is used as the storage circuit.