JPH02196525A - Path memory input method in viteribi decoder - Google Patents

Abstract

PURPOSE:To save a memory capacity by supplying the data of an addition comparator directly to a path memory as a memory data, applying initial setting to a reproduced data caused in the path memory directly and saving the succeeding data. CONSTITUTION:A conventional K-th bit is arranged to the 1st stage bit of a path memory 14, the output of an addition comparator 12 is stored to the 1st stage bit K of the path memory 14 from a data terminal D as the K-bit input at the start of Viterbi demodulation as it is. After the setting of the 1st stage bit is finished, the output of the addition comparator 12 is fed again to selector input (SEL) to revise a required path memory sequentially. Since the 1st stage bit is used as the K-th bit, memory bits up to (K-1)th bits are entirely eliminated and the constitution of the path memory 14 is considerably simplified.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a path memory input method for a Viterbi decoder, and in particular to a path memory input method that can reduce the path memory capacity by setting the initial value of the path memory to a certain value. This invention relates to improvements in memory input methods.

[Prior Art] Satellite communication mainly mediated by geostationary orbit satellites has been put into practical use as a variety of commercial communications, and its effectiveness as a medium compatible with fixed point broadcasting or mobile communication has been significantly expanded.

In recent years, digital technology has been introduced into this type of satellite communication, and digitally modulated signals are transmitted as data, and this is digitally demodulated in a receiving section.

In such digital satellite communications, as is well known, satellite lines have different characteristics in terms of propagation delay time and noise distribution than terrestrial data lines. It is necessary to adopt error control techniques based on

In other words, in a satellite link, the noise added to the transmission path can be considered to be various types of Gaussian noise, and if the transmission speed is low enough to ignore code amount interference, the noise between each code can be considered to be independent. Conceivable. Further, the satellite link can be expressed as a discrete, memoryless, binary symmetric communication path.

Therefore, various error control techniques are used in satellite communications while taking advantage of these characteristics.

Convolutional coding is a well-known conventional error control method, in which the information bits that are transmitted are transmitted in long blocks rather than in long blocks.
This encoding scheme is particularly suitable when information is input to the encoder continuously, so that sequences of information symbols are automatically encoded. That is, the information symbols are successively shifted through K (constraint length) stages of shift registers, and for each shift v
encoded symbols are generated and transmitted. The V encoded symbols are generated by parity checking, ie, by ORing the contents of the several stages of the shift register. The length K of the shift register is called the code constraint length, and the coding rate is R-1/v. Generally, it is known that the error rate of randomly selected convolutional codes decreases exponentially as the constraint length increases.

On the other hand, the Viterbi decoding method is used as an algorithm for decoding the above-mentioned convolutional code.

According to the Viterbi decoding algorithm, the two buses leading to a given node are examined, the bus that is most likely to have been used by the encoder is selected, and this most likely bus (residual bus) is saved and is thrown away. This procedure is then repeated for all states at each grid level.

Figure 2 shows a schematic configuration of the conventional Viterbi decoding system, in which input signals P and Q taken in from a satellite line are shown.
is converted into a signal by the input interface 10, subjected to Viterbi decoding by the addition comparator 12, and then stored in the path memory 14.

In the illustrated conventional device, a plurality of metric memories 16 are connected to the summing comparator 12.

In the summing comparator 12, the cumulative metrics of the two buses connected at each node are compared, only the bus with the largest total,quantity is saved, the other buses are discarded, and this procedure is repeated to collect all remaining buses. is determined.

The remaining buses are sequentially stored in the path memory 14.

As described above, in Viterbi decoding, the decoding operation is always processed by forward addition comparison without going backwards.
A simple operation is repeated in which various metrics are determined for each stage of decoding, a cumulative metric is obtained, and an appropriate bus is determined by making a choice between the two.

However, of course, since the above operations are performed for each state, the complexity of the decoder is proportional to the number of states and has the characteristic of increasing exponentially with the constraint length of the code. Therefore, this drawback requires a huge amount of memory (2) (-1XL (L is the number of information bits)) bits of remaining path memory to store the information of all the buses.

As is clear from the figure, the output data of the addition comparator 12 is normally used as selector data of the path memory 14, and at this time, the most probable bus is selected, and usually "0" or "1" is the path path. stored in memory. In this way, the path memory is sequentially updated in, for example, 40 steps (m), and finally the output circuit 18 outputs the most probable row signal from each path memory. The maximum cumulative metric value of the metric memory 16 is used to select the maximum cumulative metric value, and the row of the path memory 14 corresponding to this maximum cumulative metric value is retrieved from the output circuit 18.

FIG. 3 shows the input structure of such a conventional path memory, and the path memory 14 has m bits, for example 4 bits.
It has a memory stage of 0 bits, and its row is -1 to N-2.
(K is the constraint length of convolutional encoding).

Each of these path memories is connected to a selector input (S E
The output data of the addition comparator 12 is used as a selector signal to control the power of the remaining bus to each path memory.

[The problem that the invention tries to solve! ] As mentioned above, the Viterbi decoding method has the advantage of easy encoding and operation, but on the other hand, it requires a huge amount of memory, and it is difficult to use the serial method using general-purpose memory, which is generally easy to implement. The timing design is complicated, and the operating speed is 1/2 K-' of the parallel method.
It had the following drawbacks.

In particular, according to the conventional path memory input method, the addition and comparison results are sequentially stored in the bits of each path memory,
For example, it is necessary to sequentially store all nodes of 30 bits in the path memory, and as a result, there is a problem in that a large capacity of the path memory is required.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an improved Viterbi decoding method that can easily perform path memory input in Viterbi decoding and reduce the circuit scale. be.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses the output of the addition comparator simply as selector data of the path memory when inputting the path memory using the output data of the addition comparator. It is characterized by being able to be treated as input data itself, rather than as input data itself.

[Operations] Therefore, according to the present invention, it is possible to make the stored contents of the path memory the output of the direct addition comparator itself.

As a result of a detailed study of the contents of the path memory in Viterbi decoding, the inventor noticed that the contents of the second bit of the path memory appear as the same contents as the output of the addition comparator used as the path memory selection signal. did.

In other words, if the constraint length in convolutional encoding is K, the output of the addition comparator will inevitably appear at the bit-th bit in the path memory.The inventor focused on the reproduction state of this memory content, and Since the same bus information pattern is reproduced in the path memory selection signal and the constraint length bit, as is clear from the above description of the invention, in the present invention, the addition comparator is used for the path memory selection signal. The output of the addition comparator is stored directly in the bit of the path memory, and this allows -1 to be input.
The feature is that the bit path memory capacity can be reduced.

[Example] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

The Viterbi decoder according to the present invention also has a configuration similar to that shown in FIG. 2 described above, however, as shown in FIG. It has a configuration in which the output of the addition comparator 12 is directly taken in.

That is, the output of the addition comparator 12 is supplied to each selector input (SEL) of the path memory 14, as in the conventional case.
Information such as "0" or "1" based on the addition comparison result can be stored in each bit of the path memory 14, and the output of the addition comparator 12 itself can be supplied from the inverter to the input terminal.

According to the present invention, the path memory 14 arranges the conventional second bit as the first stage bit, and passes the output from the data terminal as a bit input at the beginning of Viterbi demodulation. It is characterized in that it is stored as is in the first stage bit K of the memory 14.

As mentioned above, in the case of a constraint length, by utilizing the fact that the same bit information pattern as the initial bit appears in the K-th bit, the configuration of the path memory 14 itself is reduced by -1 compared to the conventional one. It has a bit configuration and is characterized in that the output of the direct addition comparator 12 is stored as is in the first stage.

Therefore, according to the present invention, rOJ or "1" is selectively supplied from the first stage bit in accordance with the output of the sequential addition comparator 12, whereas The output of the comparator 12 is directly supplied to the data input rather than the conventional selector input, thereby allowing the second reproduced path memory pattern to be stored in the path memory 14 at the beginning of Viterbi decoding.

After the setting of this initial stage bit is completed, the output of the addition comparator 12 is again changed to the selector manually (S) as in the conventional case.
EL), and the necessary path memory updates are performed sequentially.

Therefore, according to the present invention, as is clear from the configuration of the path memory 14 in FIG. This makes it possible to significantly simplify the configuration of the path memory 14.

[Effects of the Invention] As explained above, according to the present invention, since the data of the addition comparator is directly supplied to the path memory as memory data, the reproduced data generated in the path memory is directly initialized and the subsequent data is This makes it possible to reduce the path memory base by (K-1) bits with respect to the constraint length K, thereby reducing, for example, the conventional path memory length m-40. If the constraint length is -7,
It becomes possible to achieve a memory capacity reduction of about 17%.

As is well known, in a Viterbi decoder, the path memory occupies about 50% of the entire circuit, and reducing the size of the path memory itself makes it possible to significantly reduce the overall circuit size. By reducing the path memory, the delay between input and output can be reduced by 11 bits.

[Brief Description of the Drawings] Fig. 1 is an explanatory diagram showing the relationship between a path memory and an addition comparator for explaining the path memory input method according to the present invention, and Fig. 2 is a Viterbi decoding to which the present invention is applied. FIG. 3 is an explanatory diagram showing the conventional path memory input method. 12... Addition comparator 14... Path memory 16... Metric memory

Claims (1)

[Scope of Claims] Encoded and transmitted input data is added and compared and sequentially stored in a metric memory, and the most probable path is stored in the path memory for each node stage according to the content of the addition and comparison. In a Viterbi decoder that repeats the following steps, the path selection in the path memory is performed using the selector data of the addition comparator, and the output data of the addition comparator can be used as is as path data in the path memory. A path memory input in a Viterbi decoder characterized in that the path memory length is reduced by storing the output data of a direct addition comparator in K bits (K is the constraint length of convolutional encoding) as the initial setting of the path memory. Method.