JPH02196524A - Viterbi decoding system - Google Patents

Abstract

PURPOSE:To attain a high speed processing and to miniaturize a circuit scale by using simple majority decision logic to select the content of a decoding path memory. CONSTITUTION:The optimum value output of a path memory 14 in a Viterbi decoding is decided not by an accumulated measured value of a metric memory but by the majority decision of a majority decision circuit 18 from the output of the path memory 14 itself. That is, in the case of applying decoding in a required multi-stage, the output stage bits of path memories are identical in most case and when the bits are outputted as they are, it is not required to select plural path memories intentionally from the maximum value of the accumulated measuring of the metric memory. Thus, the maximum value retrieval processing in the Viterbi decoding is facilitated and the circuit scale is miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Viterbi decoding system, and particularly to an improvement in an output value determining system when outputting a final decoding result.

[Prior Art] Satellite communication mainly mediated by geostationary orbit satellites has been put into practical use as a variety of commercial communications, and its effectiveness as a medium compatible with fixed point broadcasting or mobile communication has been significantly expanded.

In recent years, digital technology has been introduced into this type of satellite communication, and digitally modulated signals are transmitted as data, and this is digitally demodulated in a receiving section.

In such digital satellite communications, as is well known, satellite lines have different characteristics in terms of propagation delay time and noise distribution than terrestrial data lines. It is necessary to adopt error control techniques based on

In other words, in a satellite link, the noise added to the transmission path can be considered to be various types of Gaussian noise, and if the transmission speed is low enough to ignore code amount interference, the noise between each code can be considered to be independent. Conceivable. Further, the satellite link can be expressed as a discrete, memoryless, binary symmetric communication path.

Therefore, various error control techniques are used in satellite communications while taking advantage of these characteristics.

Convolutional coding is a well-known conventional error control method, in which the information bits that are transmitted are transmitted in long blocks rather than in long blocks.
This encoding scheme is particularly suitable when information is input to the encoder continuously, so that sequences of information symbols are automatically encoded. That is, the information symbols are successively shifted through K (constraint length) stages of shift registers, with one shift register per shift.
encoded symbols are generated and transmitted. This single coded symbol is generated by parity checking, ie, by ORing the contents of several stages of the shift register. The length K of the shift register is called the code constraint length, and the coding rate is R-1/v. Generally, it is known that the error rate of randomly selected convolutional codes decreases exponentially as the constraint length increases.

On the other hand, the Viterbi decoding method is used as an algorithm for decoding the above-mentioned convolutional code.

According to the Viterbi decoding algorithm, the two buses leading to a given node are examined, the path that is most likely to have been used by the encoder is selected, and this most likely bus (survival bus) is saved and is thrown away. This procedure is then repeated for all states at each grid level.

Figure 2 shows a schematic configuration of the conventional Viterbi decoding system, in which input signals P and Q taken in from a satellite line are shown.
is converted into a signal by the input interface 10, subjected to Viterbi decoding by the addition comparator 12, and then stored in the path memory 14.

In the illustrated prior art device, summing comparator 12 includes a plurality of metric memories 16 .

In the summing comparator 12, the cumulative metrics of the two paths connected at each node are compared, only the path with the largest metric is saved, the other buses are discarded, and this procedure is repeated to determine all remaining buses. be done.

The remaining buses are sequentially stored in the bus memory 14.

As described above, in Viterbi decoding, the decoding operation is always processed by forward addition comparison without going backwards.
A simple operation is repeated in which the metrics of six branches are determined for each stage of decoding, the cumulative metric is obtained, and an appropriate path is determined by choosing between the two.

However, of course, since the above operations are performed for each state, the complexity of the decoder is proportional to the number of states and has the characteristic of increasing exponentially with the constraint length of the code. Therefore, this drawback requires a huge amount of memory (2:1×L (L is the number of information bits)) bits of residual bus memory to store the information of all the buses.

In FIG. 2, the final output is the maximum cumulative count (ma
The contents 100 of the bus memory that became x) are output.

[Problems to be Solved by the Invention] As described above, the Viterbi decoding method has the advantage of easy encoding and operation, but on the other hand, it requires a huge amount of memory and is generally easy to implement for general purpose. In the serial method using memory, the timing design is complicated and the operating speed is 1/2 '-' of the parallel method.
There is also a drawback that the maximum value search process for obtaining the maximum output 100 of the cumulative measured value is complicated, and the processing time and circuit configuration for this purpose are not easy.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an improved Viterbi decoding method that can easily perform maximum value search processing in Viterbi decoding and reduce the circuit scale. It is in.

[Means for Solving the Problems] In order to achieve the above object, the present invention determines the optimal value output of the bus memory in Viterbi decoding from the output of the bus memory itself, without determining the optimal value output of the bus memory in Viterbi decoding from the cumulative metric value of the metric memory as in the past. It is characterized in that a majority circuit outputs the output of the majority vote as decoded data.

[Operation] Therefore, according to the present invention, whereas conventionally the cumulative metric maximum value was found from the contents of the metric memory and the corresponding contents of the bus memory were output, the output of the bus memory itself is determined by majority vote. This process is made possible by an extremely simple operation of making a determination.

That is, the present invention focuses on the fact that in the Viterbi decoding method, the output bits of multiple bus memories go through multi-stage binary selection, and the final output bits have almost the same value, and the necessary multi-stage decoding operation If you do this, in most cases the output stage bits of the bus memories will have the same value, and if you output this as is, there is no need to go out of your way to select multiple bus memories from the cumulative maximum value of the metric memory. This was noticed.

Even if an error were to occur in the final output bits of the bus memory, most of the output bits of the bus memory would have correct contents without any errors, and therefore, this would be output to a large number of bus memories by the majority circuit. If content with matching bits is output, it is possible to achieve a decoding operation with a sufficiently low error rate.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 1 shows a schematic configuration of the Viterbi decoding system according to the present invention, and the same components as those in FIG.

A feature of the present invention is that a majority circuit 18 is provided at the output stage of the bus memory 14, the final output bit of the bus memory is selected by this majority circuit 18, and this majority value is sequentially output. It is characterized by

As in the past, the addition comparator 12 applies a predetermined cumulative addition to the data supplied from the input interface 10, sequentially stores the contents in the metric memory, and also stores the contents in the separately provided bus memory 14 from the contents. Update the contents sequentially.

Therefore, the probability of the contents of the bus memory 14 increases as the decoding operation progresses through multiple stages, and whereas the contents of each bus memory 14 were random at the previous stage,
Error-free and highly accurate data as it approaches the final stage.
For example, it converges to either "UO" or "1".

The present invention focuses on such data convergence, and selects an amount of bus memory output bits corresponding to the maximum accumulated metric value of the conventional metric memory with regard to which of the many bus memories 14 is to be used as the decoded output. Instead, the output data is the one with more "0" or "1" among all the bits of the output value of the bus memory 14. Therefore, according to the present invention, the majority circuit 18 simply uses the bus memory 14 as the output data. Output processing can be performed by an extremely simple operation of monitoring only the final output bit of the memory 14 and outputting a large number of data at this time as decoded data.

The majority voting circuit 18 can be realized by a combination of ordinary logic circuits, and of course it is also possible to use other analog circuits.

[Effects of the Invention] As explained above, according to the present invention, when selecting the contents of the decoding bus memory, it is possible to select the contents of the decoding bus memory by simply using simple majority logic, and the cumulative measurement of the metric memory as in the conventional method can be achieved. Since there is no need for a maximum value search to generate decoded output data regardless of the maximum value, it is possible to speed up the processing and reduce the circuit scale.

In fact, according to the present invention, it is possible to achieve a capacity of 150 Kbps in the case of the Viterbi decoding system in a one-board type, and a capacity of more than 10 Mbps in the LSI type, and the error correction ability can also be improved by the majority voting process. Almost no deterioration occurred.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a preferred embodiment of the Viterbi decoding system according to the present invention, and FIG. 2 is a schematic diagram of a conventional Viterbi decoding system. 12... Addition comparator 14... Bus memory 16... Metric memory 18... Majority circuit

Claims (1)

[Scope of Claims] Encoded and transmitted input data is added and compared and sequentially stored in a metric memory, and the most probable path is stored in the path memory for each node stage according to the content of the addition and comparison. A Viterbi decoding method characterized in that, in a Viterbi decoder that repeats the following steps, all output bits of a path memory are judged by a majority vote, and the contents of the output bits having the majority value are output.