KR100336246B1 - Integrated circuit with digital processor and co-processor - Google Patents

Abstract

A signal processor (eg, 11) is disclosed having an embedded Viterbi co-processor (eg, 15) that operates in parallel with the signal processor (eg, 11).

Description

Integrated circuit with digital processor and co-processor

Reference to related application

This application is related to the following concurrently pending applications, each of which is hereby incorporated by reference.

D. Blaker, M., Nov. 16, 1993, entitled Application No. 08 / 153,334, "Efficient Use of Current / Next State Registers." Diamondstein, G. Ellard, M. Movin, H. Sam and M. Filed by Thierbach et al. Blaker 3-2-3-3-4-10 at our headquarters number;

Application No. 08 / 152,531, filed November 16, 1993, entitled “Variable Length Tracebacks.” Blake, G. Elard, and M. Filed by Movin et al. Blaker 4-4-4 at our headquarters;

No. 08 / 153,333, filed Nov. 16, 1993, entitled "Power and Time Saving Initialization Traceback." Blake, G. Elard, and M. Filed by Movin et al. Blaker 6-6-6 at our headquarters;

No. 08 / 152,805, Nov. 16, 1993, entitled "Digital Receiver with Minimum Cost Index Register." Blake, G. Ellard, M. Movin and H. Filed by Sam et al. Blaker 2-2-2-3 at our headquarters;

No. 08 / 153,405, Nov. 16, 1993, entitled "Viterbi Decoder and Digital Processor with Shared Memory." Diamondstein, H. Sam and M. Filed by Thierbach et al. Blaker 5-5-5-9 at our headquarters;

Technical field

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to digital signal processors, and more particularly to digital signal processors that perform Viterbi processing.

Background of the Invention

Mobile communication devices, such as mobile digital cellular telephones, often use digital signal processors to process and filter digital signals transmitted and received. Often, a separate chip is provided to implement Viterbi processing for correcting errors in incoming signals. Alternatively, Viterbi processing is encoded in software in the digital signal processor.

Viterbi processing is a maximum likelihood decoding process that provides forward error correction. Viterbi processing is used to decode a sequence of encoded signals, such as a bit stream. The bit stream may represent encoded information in communication system transmissions over various media with respective sets of bits representing symbol instants. In the decoding process, the Viterbi processor operates back to one bit sequence of possible bit sequences at each symbol instant to determine which bit sequence is most likely transmitted. Possible transitions from the bit state at one symbol moment to the bit state at the next subsequent symbol moment are limited. Each possible transition from one state to the next can each be shown graphically and defined as a branch. The sequence of interconnected branches is defined as a path. Each state may transition to a limited number of next states upon receiving the next bit in the bit stream. Some paths are maintained during the decoding process, while others are not. By eliminating unacceptable transitions, an efficient operation can be made in determining which paths are most likely to be maintained. Viterbi processing typically defines and calculates a branch metric associated with each branch and uses this branch metric to determine which paths are to be maintained and which paths are not to be maintained.

Typically, Viterbi processing is implemented on a chip separate from the digital signal processing chip (or, as mentioned above, may be implemented in digital signal processor software). The received signals go first to a Viterbi processor for decoding, while the digital signal processor does not work. The decoded signals then go to a digital signal processor for further processing.

As mobile communication devices proliferate, there remains a need for faster and more efficient processing of received signals.

Summary of the Invention

Efficient processing of signals is accomplished by the present invention, which includes a digital processor that performs a signal processing function and an embedded co-processor that implements a Viterbi decoding function, wherein the digital processor includes a signal. Perform processing functions simultaneously.

details

The digital signal processor (DSP) is indicated by reference numeral 11. Master control of the digital signal processor is given by the control unit 13. An error correction co-processor (ECCP) 15 is inserted into the digital signal processor 11. The ECCP 15 operates under the direction of its own internal control unit 17. A single command from the DSP control unit 13 causes the control unit 17 to instruct the ECCP 15 to perform a complete Viterbi decoding operation. Since Viterbi processing is embedded in the ECCP control unit 17, considerable DSP code compression is achieved.

The DSP control unit 13 communicates with the ECCP 15 through three interface registers. The address register ear 19 is utilized to indirectly address the internal memory mapped register of the ECCP. The data register edr 21 works in cooperation with the address register 19 to read indirectly from or write to the internal memory mapped register of the ECCP. After each access, the contents of the address register 19 are increased by one. Instructions to the ECCP 15 are given via the instruction register eir 23. When the appropriate code is given to the instruction register 23, the ECCP 15 will do any of the following. That is, it is well known that iii) MLSE (maximum probability sequence estimation), ii) convolutional decoding, iii) simple traceback operation, viterbi processing can be used to provide both MLSE or convolutional decoding.

Registers 100 are given in ECCP 15. Registers 100 store composite channel estimates, generation polynomials, composite received signals, input signals for convolutional decoding, and decoded symbols. Each of these registers is accessed by writing an address to ear register 19 and writing or reading to edr register 21. The command instructing the ECCP 15 to be enabled is written to the eir register 23.

If MLSE operation is desired, control register ECON 25 in control unit 17 receives via registers 19 and 21 the number of taps required for MLSE operation. However, if a command for convolutional coding is given through register 23, control register 25 may be configured for various constraint lengths of 2 to 7 and code rates of 1/1 to 1/6.

The ECCP 15 generally operates independently of and in parallel with the rest of the rest of the DSP 11. Thus, for example, at the start of a processing sequence, the ECCP 15 may be inactive. On the other hand, the rest of the DSP 11 receives or transmits signals or performs other operations. The other part of the DSP 11 programs the operating modes of the ECCP 15.

Next, while the DSP core 13 instructs the ECCP 15 to start Viterbi processing, the rest of the DSP 11 receives or transmits a new signal from the voice band or baseband codec, and the voice processing. The algorithm is executed, channel adaptation is performed, and other processing such as encryption / decryption or interleaving / de-interleaving is continued. In the meantime, the ECCP 15 receives instructions from the core processor 13 to perform MLSE processing or convolutional decoding operations.

When the ECCP 15 is busy performing Viterbi processing, the EBUSY signal 29 is supplied to the core processor unit 13.

When the ECCP 15 finishes performing its operation, the ECCP 15 supplies the EREADY signal 27 to the core processor 13. The EREADY signal indicates to the core processor 13 that the information supplied to the ECCP 15 is Viterbi processed or convolutionally decoded for the MLSE. In some circumstances, it is desirable to perform MLSE on the received signal first and then perform convolutional decoding. As such, the generated bit stream is supplied to the ECCP 15 for MLSE. After the MLSE is completed, the EREADY signal 27 is supplied to the control unit. The MLSE processed signals are then decoded, deinterleaved, and rearranged by the rest of the DSP 11 and input back to the ECCP 15 with instructions via register 23, where the MLSE processed signals are subjected to convolutional decoding. Viterbi is processed.

In other environments, MLSE may not be required and only convolutional decoding may be performed. At any rate, after the ECCP is terminated, it supplies an EREADY signal and the Viterbi decoded bit stream can be used for the rest of the DSP 11 for further processing. Such further processing may include data presentation or speech decompression in the appropriate format. The parallelization of this operation between the ECCP and other parts of the DSP 11 provides very timely and efficient processing of the received signal, which has not been realized until provision in the prior art.

The output of the Viterbi operation may be either a hard output or a soft output. The hard output represents a binary decision (true / false, or 0-1 or +1, -1). The soft output is a hard output related to a confidence measure. The core portion 13 instructs whether the ECCP 15 will provide a hard output or a soft output. Various types of soft decision outputs known to those skilled in the art may be provided.

2 is a block diagram illustrating the parallel operation of the ECCP 15 and other parts of the DSP 11 in more detail. At the start of the decoding operation, as indicated by block 101, the EBUSY signal is false and the ECCP 15 is turned off and ready to be loaded. Block 103 indicates that the ECCP 15 is programmed through the register 23 by the core processor 13. Among the information supplied to the ECCP 15 are Viterbi traceback and limit lengths, and the generated polynomial. If MLSE operation is desired, the number of channel taps is also given.

Next, the input signal is loaded into the ECCP (block 105). When the ECCP 15 receives the first update command (block 103), the value of the EBUSY flag is high and the ECCP is turned on to start a complete Viterbi operation. The ECCP 15 performs update calculation in accordance with the provided convolution command or MLSE (block 109). In general, updating involves calculating a branch metric for each possible branch, adding the branch metric to a cumulative value related to the state of the branch generating stage, comparing the cumulative value for each possible branch termination in the state, and And selecting a minimum cumulative value associated with the branch end. The symbol is then decoded to correspond to the path memory (in terms of maximum probability).

Next, as indicated at block 111, the first symbol is decoded. However, since insufficient symbols have been received to perform proper traceback, the first decoded symbol is invalid and thus discarded. Next, as shown in blocks 113, 115, and 117, the amount of input symbols equal to the traceback length was sequentially loaded into the DSP, the MLSE or convolution instruction was updated, and the traceback (because the number of reloaded symbols is still insufficient). The number of invalid decoding symbols equal in length and TL was obtained. (Of course, a smaller traceback length can be used for effective symbol decoding for some channel adaptation algorithms, if necessary. In theory, the best decoded symbol is obtained when the traceback length TL is longer). If the traceback length is indicated by the symbol TL, the first TL signals are invalid and discarded.

Blocks 119, 121, and 123 describe valid decoding of the first symbol, and after symbol number TL + 1 is loaded, MLSE / convolution update is performed and the first valid symbol is decoded. The remaining input symbols are then loaded up to symbol number n, and the same amount as n TL valid decoded symbols is obtained, as indicated by blocks 125, 127, 129 (n is the total number of input symbols). At this point in the processing, all input signals were provided to the ECCP. Complete tracebacks providing n valid decoded symbols may be performed as shown in blocks 131, 133, 135, 137. Following each traceback command, one valid decoded symbol is obtained. The traceback instruction is executed TL times to get all decoded symbols captured in the traceback memory.

As shown in block 137, after n valid decoded symbols are obtained, the EBUSY flag goes low, the ECCP is turned off, and all valid decoded symbols are sent to another portion of the digital signal processor for further processing.

1 is a block diagram illustrating an embodiment of the present invention.

2 is a block diagram illustrating a processing procedure according to the present invention.

♣ Explanation of symbols for main part of drawing ♣

11 digital signal processor 15 error correction co-processor (ECCP)

17 control unit

Claims (12)

In an integrated circuit: A digital processor (eg, 11) for performing a signal processing function; An embedded co-processor (eg, 15) that implements a Viterbi decoding function, wherein the digital processor (eg, 11) while the co-processor (eg, 15) performs the Viterbi decoding function. A co-processor that simultaneously performs a signal processing function; An address register for addressing at least one of a plurality of internal memory mapped registers of the co-processor; Co-pending a data register with the address register to read from and write to the at least one of the plurality of internal memory mapped registers. Include, The co-processor operates under control of the digital processor, initiates operation upon receipt of a command from the digital processor, and provides a signal to the digital processor when the co-processor terminates. The integrated circuit of claim 1, wherein the co-processor (eg, 15) is programmed by the digital processor (eg, 11) to perform maximum likelihood sequence estimation or convolutional decoding. 3. The integrated circuit of claim 2, wherein the digital processor (e.g., 11) provides the number of channel taps to the co-processor when maximum probability sequence estimation is performed. 3. The integrated circuit of claim 2, wherein the digital processor (e.g., 11) provides a Viterbi traceback length, a limit length, and a generation polynomial to the co-processor (e.g., 15) when convolutional decoding is performed. 2. The digital processor of claim 1, wherein the digital processor (e.g., 11) can instruct the co-processor (e.g., 15) to perform a maximum probability signal estimation for the first bit stream, thereby And then perform convolutional decoding on the second bit stream, thereby generating a third bit stream. The method of claim 1, a) the digital processor (eg, 11) programs the co-processor (eg, 103); b) the digital processor loads a first symbol into the co-processor (eg, 105); c) the co-processor performs a Viterbi update operation on the symbol, thereby obtaining a decoded symbol (eg, 111); d) steps b) and c) are repeated TL-1 times while the digital processor performs other signal processing functions (eg, 113, 115, 117); e) the digital processor loads a TL + 1 symbol into the co-processor (eg, 119); f) the co-processor performs a Viterbi traceback operation on the TL + 1 symbols, thereby obtaining a valid decoded symbol (eg, 123); g) the digital processor loads the last n th symbol (eg, 125); Whereby the co-processor utilizes the n symbols to perform a Viterbi traceback operation with a traceback length TL, thereby obtaining n valid decoded symbols (e.g., 137). 7. The digital processor of claim 6, wherein the digital processor (e.g., 11) is adapted for channel adaptation, encryption, decryption, interleaving or de-interleaving voice while the co-processor performs the Viterbi process. An integrated circuit that performs a function selected from the group consisting of processing and input / output operations. The method of claim 1, wherein the digital processor (eg, 11) provides a single instruction to the co-processor (eg, 15), wherein the single instruction causes the co-processor (eg, 15) to: Perform calculations of the appropriate branch metric for all possible state transitions to all states; Perform all corresponding processes of add-compare-select of the Viterbi algorithm; Perform a complete traceback decoding process; And generate decoded symbols at the end of the traceback operation. 2. The integrated circuit of claim 1, wherein the digital processor (e.g., 11) provides a code rate to the co-processor (e.g., 15). 2. The integrated circuit of claim 1, wherein the digital processor (e.g., 11) provides the branch metric calculation type to the co-processor (e.g., 15). 2. The integrated circuit of claim 1, wherein the digital processor (e.g., 11) instructs the co-processor (e.g., 15) whether to provide soft or hard decision output. The integrated circuit of claim 1, wherein the digital processor (eg, 11) provides a limited length to the co-processor (eg, 15).