KR20040065841A - Operation method for traceback of viterbi decoder - Google Patents

Abstract

PURPOSE: A method for calculating the traceback of a Viterbi decoder is provided to save the capacity of the memory in comparison with a conventional method without performance deterioration. CONSTITUTION: A method for calculating the traceback of a Viterbi decoder includes the steps of: a first step of constructing a traceback block by a predetermined number of memories with a capacity having a half of the conventional unit memory in the Viterbi decoder; and a second step of performing the traceback by two memories simultaneously when the Viterbi decoding is performed by using the memories.

Description

OPERATION METHOD FOR TRACEBACK OF VITERBI DECODER}

TECHNICAL FIELD The present invention relates to a technique for efficiently performing a traceback of a Viterbi decoder. In particular, the present invention relates to a traceback memory using a path metric memory which is kept empty for a certain delay by adding a few control signals. The present invention relates to a traceback calculation method of a Viterbi decoder to reduce memory capacity.

Error Correcting Coding (EEC) is used to correct an error that occurs when transmitting data in a digital communication system. The error correcting encoding is a block code that encodes and decodes data in block units, and a convolutional code that performs encoding by comparing old data with current data using a memory of a predetermined capacity. Are classified as).

The convolution code generates a codeword message of an n-symbol block in the same time unit for an input message of a k-bit block. The ratio R of k / n is called code rate. For example, R = 1/2 and R = 1/3 are mainly used in wideband CDMA. In general, an encoding apparatus may be implemented using a shift register, a modulo-2 adder, and a multiplexing apparatus. The convolutional code can be represented by three integers n, k, and K. The integer K is called the constraint length, and the stage of the input message of the k-bit block in the shift register of the encoding apparatus. Indicates a number. Currently, the constraint length is used up to K = 9, and more than K> 9 is not actually used. In practice, a structure in which K = 9 is used in wideband CDMA. The Viterbi algorithm is one of the most used methods for decoding such convolutional codes.

The Viterbi algorithm finds the shortest path through the trellis given an input message, and each node corresponds to a given discrete time stste. A line connecting a trellis node is called a branch, which corresponds to a transition from one state to another. Branches that connect to nodes in Trellis are assigned to metrics, which are It is given by the negative log likelihood function, approximated by r, where r is the signal representing the measured output and v is the signal representing the actual output for the potential between states. By comparing the branch metric calculated in each stage and the path metric of the previous stage, the smaller of them determines the next route metric value. In order to perform the decoding operation using the calculated route metric, the route metric for the number of stages defined as truncation depth, L is required, and this value is generally 5 times or more of K. . When the number of stages advances by L, the input message is decoded and outputted. There are two types of decoding methods, a register exchange method and a traceback method.

In the structure using the Viterbi algorithm, as shown in FIG. 1, the relationship between the current state and the next state has a butterfly structure such as a butterfly shape. It adds the new branch metric value (BM) and the accumulated path metric value (PM) at each transition and compares them for each state, and adds an addition comparison selection that outputs the survival metric value and the survival path with the optimal path metric value (Add -Compare-Selection). The survival path selected by the addition comparison selection device is stored so that the decoding starts when the stage is usually 5 times larger than K. To trace back a survival path, each state ( ) Should store data as much as the depth of truncation (L). Therefore, the area required for storage is approximately As the value of K increases. When the value of K is small and the value of the path metric is small, the register exchange method is simple to control and is easy to implement. However, when the K is large and the value of the path metric is large, the area of the register is too large. There is a drawback in power consumption, so it is advantageous to use a traceback method that uses memory.

In general, when using the traceback method, as shown in FIG. 2, four memories MEM0-MEM3 are required. In order to obtain the decoded data, it is necessary to trace back the minimum truncation depth (L), so the first L input data is written to the first memory (MEM0). Thereafter, the L data are written to the second memory MEM1 and the data input to the first memory MEM0 is traced back. Then L writes to the third memory (MEM2) and simultaneously traces back the data input to the second memory (MEM1), where the first memory (MEM0) is the traceback of the second memory (MEM1) is completed It will not run until it is idle. While the next L data are written to the fourth memory MEM3, decoding is started from the survival path converged through traceback in the second memory MEM1 for the first memory MEM0.

Since the decoded data proceeds in the reverse order of the input sequence, once the data is stored in the last input first output (LIFO) and the data in the first memory MEM0 are all decoded, the decoded data is decoded in the last-in-first-out (LIFO). Print one by one. While the first memory MEM0 and the fourth memory MEM3 operate as described above, the third memory MEM2 performs a traceback, and the second memory MEM1 traces the third memory MEM2. Wait for the back to run. 3 shows a process of storing and outputting the decoded data in the last-in, first-out (LIFO). Since the data of L is decoded again while the data stored in the last-in-first-out (LIFO) is output, one more last-in-first-out (LIFO) is required to store it. Therefore, in order to decode and output the first L input messages inputted to the decoder (DEC), a total delay of 4L is required.

When implementing a Viterbi decoder, the storage medium occupies about 60% of the total capacity, so reducing this capacity greatly affects the area of the entire logic.

However, in the Viterbi decoder according to the prior art, due to the structural features of the traceback memory, a large amount of memory is used unnecessarily, and thus, the area of the entire logic is increased and the cost is increased.

Accordingly, an object of the present invention is to provide a traceback calculation method of a Viterbi decoder which reduces the memory capacity used for traceback by adding a little control signal and using a path metric memory that remains empty for a predetermined delay time. have.

1 is a butterfly structure diagram of a Viterbi decoder having a 64-stage.

2 is a traceback memory format diagram of a Viterbi decoder according to the prior art.

3 is an explanatory diagram showing a last-in-first-out operation of a general Viterbi decoder.

4 is a traceback memory format diagram of a Viterbi decoder according to the present invention;

5 is a format diagram of another traceback memory of a Viterbi decoder according to the present invention;

*** Description of the symbols for the main parts of the drawings ***

DEC: Decoder LIFO: Last-In First-Out

The traceback calculation method of the Viterbi decoder according to the present invention includes a predetermined number having a half capacity of a typical unit memory capacity (eg, in order to perform Viterbi decoding in the order of data writing, traceback, standby state, and decoding). A first step of building a traceback block into six memories; When performing Viterbi decoding using the memory, a second process of performing traceback to two memories at the same time is included. Referring to FIGS. 4 and 5 to which the traceback calculation method of the present invention is attached. When described in detail as follows.

In Viterbi decoder, the value stored in memory for traceback is determined when the survival metric is determined by the Add-compare-Selection device. Data represented by 1 bit using '1' to distinguish the state of the previous path.

In FIG. 1, the addition comparison selector compares the PM (n) + BM00 value with the PM (n + 1) + BM01 value and stores the smaller of them in the next path metric PM_N (n). At this time, the LSBs of values representing the state of the path metric, PM (n) and PM (n + 1) are '0' and '1', and when they are stored in the traceback memory, the path of the next path metric, PM_N (n) You can track the status.

If PM (n) + BM00 is smaller than PM (n) + BM00 and PM (n + 1) + BM01, this value is stored in the next path metric, PM_N (n), and '0' is stored in traceback memory. In the opposite case, a '1' is stored in the traceback memory. When tracing back the stored data, the previous path metric can be tracked by subtracting the MSB from the current state value and concatenating the LSB stored value in the traceback memory. This is because, based on the Viterbi butterfly structure, if the state LSB of the path metric is known, the state value at the time of backtracking can be estimated.

If you use the traceback memory in the conventional manner, the number of states ( ) Multiplied by the truncation depth (L) ( 4 memories are required. However, half the capacity ( Using six memories, the same traceback block can be implemented. For example, when using the traceback memory structure as shown in FIG. 4, the total capacity of the memory used for the traceback can be reduced by 1/4 of the conventional method.

In FIG. 4, an arrow shows a progress direction in which each of the memories MEM0-MEM5 is accessed. Instead of using half the memory, having two memory tracebacks (TB0) and (TB1) at the same time ensures a sufficient depth of truncation, so there is no difference in decoding performance. In the memory access direction indicated in FIG. 4, it can be seen that writing and decoding proceed in opposite directions. Once the data is decoded and stored in the last-in-first-out (LIFO), the space that already stores the decoded data remains unused during decryption, considering that the contents stored in the traceback memory are useless. Will be.

If data is written to the portion left unused in this way, the number of memories used for the traceback can be further reduced as shown in FIG. When data is written in the same direction as the decoding direction as shown in FIG. 5, decoding is completed and input data is written to the empty memory. In this case, since the access progress direction of the memory is not constant, a control signal indicating the start memory address is additionally required, and the memory structure used must be a dual port RAM.

When the memory address is written, it proceeds from 'L / 2-1' to '0' direction, and in other cases, proceeds from '0' to 'L / 2-1' direction (arrow direction in FIG. 4). In the case of using the trellis-back memory structure of FIG. 5, the advancing direction of the memory address varies according to a situation. Therefore, a signal for controlling this is required. It can be seen how the memory address progress direction varies depending on the situation in the arrow direction of FIG. 5.

The amount of traceback memory that decreases with increasing constraint length K is shown in Table 1 below. The larger K, the greater the gain in terms of memory capacity and power consumption.

As described in detail above, the present invention uses six half-capacity memories and uses a path metric memory that remains empty for a predetermined delay time when decrypted by the traceback method, thereby improving memory capacity without degrading performance. Compared to the above, it can save more than 1/4.

Claims (3)

A first step of constructing a traceback block with a predetermined number of memories having a half capacity of a typical unit memory capacity in a Viterbi decoder; And a second step of performing a traceback to two memories at the same time when performing Viterbi decoding by using the memories. 2. The method of claim 1, wherein the traceback block comprises six memories. The memory of claim 1 or 2, wherein the traceback block does not use a memory for writing data separately, and employs a method of writing data in a space that stores already decoded data during decoding. A traceback calculation method of a Viterbi decoder, characterized in that the number is further reduced.