JPH0262541A - Production of semiconductor product of semi-customized goods - Google Patents

Production of semiconductor product of semi-customized goods

Info

Publication number
JPH0262541A
JPH0262541A JP63213880A JP21388088A JPH0262541A JP H0262541 A JPH0262541 A JP H0262541A JP 63213880 A JP63213880 A JP 63213880A JP 21388088 A JP21388088 A JP 21388088A JP H0262541 A JPH0262541 A JP H0262541A
Authority
JP
Japan
Prior art keywords
reticle
wiring pattern
reticule
wiring
exposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63213880A
Other languages
Japanese (ja)
Other versions
JP2715462B2 (en
Inventor
Masahiro Yoneyama
正洋 米山
Mamoru Yamada
守 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21388088A priority Critical patent/JP2715462B2/en
Publication of JPH0262541A publication Critical patent/JPH0262541A/en
Application granted granted Critical
Publication of JP2715462B2 publication Critical patent/JP2715462B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To decrease stages for forming a reticule and to speed up operations by providing plural wiring patterns on the same reticule and blank parts at need thereon and exposing the wiring patterns and the periphery of a wafer. CONSTITUTION:The reticule 1 is segmented by light shielding zones 6 and the different patterns A to D are provided to the wiring pattern parts 2 to 5. When a customer requests the pattern A, the other parts are shielded of light and this pattern is exposed. The cost and man-hours of forming the reticule are reduced and the prepn. time for exposing is shortened by this constitution. Exposing to remove the resist in the peripheral part is executable with one sheet of the reticule 1a by using the reticule 1a formed with the transparent blank parts 7 in the part D and exposing the photoresist of the periphery of the wafer by using the blank parts 7.

Description

【発明の詳細な説明】 し産業上の利用分野コ 本発明は半導体装置の製造方法に関し、特に、同一の下
地パターンを有する基板を用いて配線工程のみを顧客の
要求に応じた特有の配線パターンで形成するセミカスタ
ム品の半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, only the wiring process is performed using a unique wiring pattern according to customer requirements using substrates having the same underlying pattern. The present invention relates to a method for manufacturing a semi-customized semiconductor device formed using a semiconductor device.

〔従来の技術] 従来、この種のセミカスタム品は配線工程において配線
パターンを形成する際に、顧客の要求に応じて、第3図
に示すようなレチクル1bを1枚づつ作成し、各レチク
ル1bを使用して露光作業を行うことにより製造してい
た。第3図に示すレチクル1bは遮光帯6に囲まれて配
線パターンA部2が設けられており、この配線パターン
A部2内にペレット境界8が遮光帯6に平行に相互に直
交するように形成されている。
[Prior Art] Conventionally, in this type of semi-custom product, when forming a wiring pattern in the wiring process, one reticle 1b as shown in FIG. It was manufactured by performing an exposure operation using 1b. The reticle 1b shown in FIG. 3 is provided with a wiring pattern A part 2 surrounded by a light-shielding band 6, and within this wiring pattern A part 2, pellet boundaries 8 are arranged parallel to the light-shielding band 6 and perpendicular to each other. It is formed.

また、ウェハ周辺部のフォトレジストを除去するための
周辺露光の際にも、配線パターンを有しない透明なレチ
クルを使用して露光し、配線パターンの露光作業とは別
の工程でフォトレジストを除去していた。
Also, during peripheral exposure to remove photoresist from the periphery of the wafer, a transparent reticle without wiring patterns is used for exposure, and the photoresist is removed in a separate process from the wiring pattern exposure process. Was.

[発明が解決しようとする課題] しかしながら、上述した従来のセミカスタム品の製造方
法においては、各顧客の要求に応じて個別的に作成した
レチクルを使用するので、レチクルを多数枚作成する必
要があり、レチクル作成のためにコスト及び工数が多く
かかるという欠点がある。また、ウェハ上にパターン形
成する際にもレチクルを1枚づつ使用するので、レチク
ルの洗浄、ゴミ検査及びアライメントの各作業を1枚づ
つ行う必要があり、また、レチクル交換時間も必要であ
るため、ウェハ上にパターン形成するまでの準備時間及
び工数が多くかかるという欠点もある。
[Problems to be Solved by the Invention] However, in the conventional manufacturing method for semi-custom products described above, reticles are individually created according to the requirements of each customer, so it is necessary to create a large number of reticles. However, the disadvantage is that it takes a lot of cost and man-hours to create a reticle. Furthermore, since one reticle is used when forming a pattern on a wafer, it is necessary to perform each reticle cleaning, dust inspection, and alignment one by one, and it also takes time to replace the reticle. However, it also has the disadvantage that it takes a lot of preparation time and man-hours to form a pattern on the wafer.

本発明はかかる問題点に鑑みてなされたものであって、
セミカスタム品の配線パターンを少ない工数で迅速に且
つ低コストで形成することができるセミカスタム品の半
導体装置の製造方法を提供することを目的とする。
The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device of a semi-custom product, which can quickly form a wiring pattern of a semi-custom product with a small number of man-hours and at low cost.

[課題を解決するための手段] 本発明に係るセミカスタム品の半導体装置の製造方法は
、複数種類の配線パターンが設けられたレチクルを使用
し、顧客の要求に応じて所望の配線パターンを選択して
露光すると共に、別の所望の配線パターンを露光する際
にはレチクルを交換することなく同一のレチクルの別の
配線パターンを使用して露光することを特徴とする。
[Means for Solving the Problems] A method for manufacturing a semi-customized semiconductor device according to the present invention uses a reticle provided with a plurality of types of wiring patterns, and selects a desired wiring pattern according to a customer's request. The present invention is characterized in that when another desired wiring pattern is exposed, another wiring pattern of the same reticle is used without exchanging the reticle.

なお、レチクルとしては、複数の配線パターンの外に、
レジスト除去のための周辺露光用の透明なブランク部も
併わぜで設けたものを使用してもよい。
In addition, as a reticle, in addition to multiple wiring patterns,
A transparent blank section for peripheral exposure for resist removal may also be provided.

[作用] 本発明においては、同一レチクル上に複数の配線パター
ンが設けられ、また必要に応じてブランク部が設けられ
たものを使用して配線パターン又はウェハ周辺部の露光
作業を行う。このため、異なる配線パターンを形成する
場合又は配線パターンの形成の後に周辺露光する場合も
、レチクルを交換することなく、同一のレチクルを使用
して露光作業をすることができる。従って、レチクル作
成コスト及び工程を削減することができると共に、露光
作業も迅速化される。
[Operation] In the present invention, a plurality of wiring patterns are provided on the same reticle, and a blank portion is provided as necessary to perform the exposure work of the wiring patterns or the periphery of the wafer. Therefore, even when forming a different wiring pattern or performing peripheral exposure after forming a wiring pattern, the same reticle can be used for exposure work without changing the reticle. Therefore, the reticle production cost and process can be reduced, and the exposure work can be speeded up.

[実施例] 次に、本発明の実施例について添付の図面を参照して説
明する。
[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の第1の実施例方法にて使用するレチク
ル1の平面図である。このレチクル1は4面付の場合の
ものであり、配線パターン部2゜3.4.5に夫々異な
る4個の配線パターンA。
FIG. 1 is a plan view of a reticle 1 used in the first embodiment method of the present invention. This reticle 1 has four sides, and has four different wiring patterns A in the wiring pattern portion 2°3, 4.5.

B、C,Dが形成されている。各配線パターン部2.3
,4.5は遮光帯6に囲まれている。この遮光帯6はウ
ェハ上で隣接ペレットに光が漏れないようにするための
ものである。
B, C, and D are formed. Each wiring pattern section 2.3
, 4.5 are surrounded by a light shielding zone 6. This light shielding band 6 is provided to prevent light from leaking to adjacent pellets on the wafer.

このように構成されたレチクル1を使用して配線パター
ンを形成する場きは、顧客の要求が配線パターンAのと
きは露光装置本体の遮光板を配線パター78部3、配線
パターンC部4及び配線パター79部5に光が当たらな
いようにセットし、配線パターンA部2を使用して配線
パターンA用のウェハの露光を行う。
When forming a wiring pattern using the reticle 1 configured in this way, if the customer's request is wiring pattern A, the light shielding plate of the exposure apparatus main body is attached to the wiring pattern 78 section 3, the wiring pattern C section 4, and the wiring pattern C section 4. The wiring pattern 79 section 5 is set so as not to be exposed to light, and the wafer for the wiring pattern A is exposed using the wiring pattern A section 2.

次に、別の配線パターンBを露光する場合は、配線パタ
ーンA部2、配線パターンC部4及び配線パター70部
5上を前記遮光板で覆い、配線パターンB用のウェハの
露光を行う。配線パターンC又は配線パターンD用のウ
ェハを露光する場合も同様の操作により行う。
Next, when exposing another wiring pattern B, the wiring pattern A section 2, the wiring pattern C section 4, and the wiring pattern 70 section 5 are covered with the light shielding plate, and the wafer for the wiring pattern B is exposed. A similar operation is performed when exposing a wafer for wiring pattern C or wiring pattern D.

二のように、同一レチクル1上に4個の配線パターンA
、B、C,Dを設けたから、1つのレチクルを使用して
4種類の配線パターンを形成することができ、レチクル
の作成コスト及び工数を削減できると共に、露光に先立
つ準備作業に要する時間を著しく短縮することができる
2, four wiring patterns A are placed on the same reticle 1.
, B, C, and D, four types of wiring patterns can be formed using one reticle, reducing reticle production costs and man-hours, and significantly reducing the time required for preparation work prior to exposure. Can be shortened.

なお、上記実施例のようにレチクルが4面付の場合以外
の複数の面付の場合も、上述のようにして同一レチクル
に複数の配線パターンを設けることができる。
Note that even in the case where the reticle has multiple surfaces other than the four-sided reticle as in the above embodiment, a plurality of wiring patterns can be provided on the same reticle as described above.

第2図はレチクルの変形例を示す平面図である。FIG. 2 is a plan view showing a modification of the reticle.

このレチクル1aは、第1図に示すレチクル1.の配線
パター79部5の替わりに、透明ブランク部7を設けた
ものである。
This reticle 1a is similar to reticle 1. shown in FIG. In place of the wiring pattern 79 section 5, a transparent blank section 7 is provided.

このレチクル1aを使用して配線パターンを形成する場
合は、ウェハ上に配線パターン部2,3゜4のいづれか
を使用して配線パターンを露光した後に、レチクル1a
のブランク部7を使用してウェハ周辺部のフォトレジス
トを露光する。このレチクル1aを筒用することにより
、ウェハ周辺部のフォトレジストの除去を目的とする周
辺露光をも1枚のレチクルで行うことができるため、レ
チクルの交換又はアライメントに要する時間を更に一層
短縮できるという利点がある。
When forming a wiring pattern using this reticle 1a, after exposing the wiring pattern on the wafer using either the wiring pattern section 2 or 3.
The blank section 7 is used to expose the photoresist at the periphery of the wafer. By using this reticle 1a as a tube, peripheral exposure for the purpose of removing photoresist around the wafer can be performed with a single reticle, which further reduces the time required for reticle replacement or alignment. There is an advantage.

[発明の効果] 以上説明したように本発明は、同一レチクル上に複数個
の配線パターン及び必要に応じてブランク部を設けたレ
チクルを使用し、同一レチクルを使用して複数の配線パ
ターンを露光したり、所謂周辺露光したりするので、顧
客の要求又は周辺露光の目的に応じて複数のレチクル又
は透明レチクルを作成するためのコスト及び工数を削減
できる。
[Effects of the Invention] As explained above, the present invention uses a reticle in which a plurality of wiring patterns are provided on the same reticle and a blank portion is provided as necessary, and a plurality of wiring patterns can be exposed using the same reticle. or so-called peripheral exposure, it is possible to reduce the cost and man-hours for creating a plurality of reticles or transparent reticles according to customer requirements or the purpose of peripheral exposure.

また、露光作業を行う際のレチクルの洗浄、ゴミ検査、
交換及びアライメントに要する時間を著しく短縮できる
という効果もある。
In addition, we also clean reticles during exposure work, inspect dust,
Another effect is that the time required for replacement and alignment can be significantly shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例方法にて使用するレチクルの平
面図、第2図はレチクルの変形例を示す平面図、第3図
は従来方法に使用するレチクルを示す平面図である。 1、la、lb;レチクル、2;配線パターンA部、3
;配線パター78部、4;配線パターンC部、5;配線
パター20部、6;遮光帯、7;ブランク部、8:ベレ
ット境界
FIG. 1 is a plan view of a reticle used in the embodiment method of the present invention, FIG. 2 is a plan view showing a modified example of the reticle, and FIG. 3 is a plan view showing a reticle used in the conventional method. 1, la, lb; reticle, 2; wiring pattern A section, 3
; Wiring pattern 78 parts, 4; Wiring pattern C part, 5; Wiring pattern 20 parts, 6; Shading zone, 7; Blank part, 8: Bullet boundary

Claims (1)

【特許請求の範囲】[Claims] (1)複数種類の配線パターンが設けられたレチクルを
使用し、顧客の要求に応じて所望の配線パターンを選択
して露光すると共に、別の所望の配線パターンを露光す
る際にはレチクルを交換することなく同一のレチクルの
別の配線パターンを使用して露光することを特徴とする
セミカスタム品の半導体装置の製造方法。
(1) Using a reticle with multiple types of wiring patterns, select and expose the desired wiring pattern according to the customer's request, and change the reticle when exposing another desired wiring pattern. 1. A method for manufacturing a semiconductor device of a semi-custom product, characterized in that exposure is performed using different wiring patterns on the same reticle without any additional wiring.
JP21388088A 1988-08-29 1988-08-29 Reticle and method of manufacturing semiconductor device using the same Expired - Fee Related JP2715462B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21388088A JP2715462B2 (en) 1988-08-29 1988-08-29 Reticle and method of manufacturing semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21388088A JP2715462B2 (en) 1988-08-29 1988-08-29 Reticle and method of manufacturing semiconductor device using the same

Publications (2)

Publication Number Publication Date
JPH0262541A true JPH0262541A (en) 1990-03-02
JP2715462B2 JP2715462B2 (en) 1998-02-18

Family

ID=16646544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21388088A Expired - Fee Related JP2715462B2 (en) 1988-08-29 1988-08-29 Reticle and method of manufacturing semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP2715462B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058935U (en) * 1991-07-12 1993-02-05 シチズン時計株式会社 Semiconductor device reticle
US5919605A (en) * 1995-03-30 1999-07-06 Nec Corporation Semiconductor substrate exposure method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55129333A (en) * 1979-03-28 1980-10-07 Hitachi Ltd Scale-down projection aligner and mask used for this
JPS55132039A (en) * 1979-04-02 1980-10-14 Mitsubishi Electric Corp Forming method for repeated figure
JPS63211622A (en) * 1987-02-17 1988-09-02 Yokogawa Hewlett Packard Ltd Multilevel-reticle and pattern transfer method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55129333A (en) * 1979-03-28 1980-10-07 Hitachi Ltd Scale-down projection aligner and mask used for this
JPS55132039A (en) * 1979-04-02 1980-10-14 Mitsubishi Electric Corp Forming method for repeated figure
JPS63211622A (en) * 1987-02-17 1988-09-02 Yokogawa Hewlett Packard Ltd Multilevel-reticle and pattern transfer method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058935U (en) * 1991-07-12 1993-02-05 シチズン時計株式会社 Semiconductor device reticle
US5919605A (en) * 1995-03-30 1999-07-06 Nec Corporation Semiconductor substrate exposure method

Also Published As

Publication number Publication date
JP2715462B2 (en) 1998-02-18

Similar Documents

Publication Publication Date Title
JP3094439B2 (en) Exposure method
JPH09134870A (en) Method and device for forming pattern
JPH0262541A (en) Production of semiconductor product of semi-customized goods
KR20050003256A (en) Liquid crystal panel arrangement formation and exposing method of Liquid crystal panel
KR100225761B1 (en) Method for designing a reticle mask
JPS60109228A (en) Projection exposing device
JPH07117744B2 (en) Dicing line formation method
JPH01234850A (en) Photomask for semiconductor integrated circuit
JP2586144B2 (en) Method for manufacturing semiconductor device
JPH0545944B2 (en)
JP4226316B2 (en) Manufacturing method of semiconductor device
JPS60221757A (en) Mask for exposure
JPH04304453A (en) Reticle and exposing method
US5871889A (en) Method for elimination of alignment field gap
JPH0812416B2 (en) mask
JPH02127641A (en) Reticle for semiconductor integrated circuit
JPH0414812A (en) Formation method of pattern
JPH03191348A (en) Reticle for reduction stepper
JPS634216Y2 (en)
JP2545431B2 (en) Lithography reticle and reticle pattern transfer method
JP2878551B2 (en) Exposure method
JPH036649B2 (en)
JPS594123A (en) Method for exposure
JPS61117544A (en) Photomask
JPH10288835A (en) Reticle

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees