JPH0258851A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device having a flattened surface at a comparatively low temperature and in a simple process by a method wherein a solvent which contains fine particles having a sufficiently small particle diameter to recessed parts, does not have an adhesion to protrusions and has an adhesion to the recessed parts is selected as a solvent in a suspension, the suspension is applied on the whole surface and the solvent is evaporated. CONSTITUTION:A solvent which does not have an adhesion to protrusions 30 and has an adhesion to recessed parts 31 is selected as a solvent in a suspension. Thereby, the suspension never applies on the upper surfaces of the protrusions 30, but stays only in the recessed parts 31: even if a method such as high- temperature annealing, etchback or the like is not used, the surface can be favorably flattened. Moreover, compared to a conventional SOG method, which has no selectivity for the protrusions and the recessed parts, and to a method using a suspension in which glass fine powder particles are used, the surface can be favorably flattened.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is a method of flattening the surface by burying an insulating film in a groove between wirings formed on a substrate or in a groove for element isolation. The present invention relates to a method for manufacturing semiconductor integrated circuits.

2. Description of the Related Art In recent years, semiconductor integrated circuits have become highly integrated, and along with this, development of circuit miniaturization and multilayer wiring has been actively conducted. Therefore, in order to perform multilayer wiring, it is necessary to flatten the grooves between the wirings formed on the substrate. Further, for miniaturization, holes (trenches) are also formed to separate elements, and it is necessary to fill the holes evenly.

[Conventional technology]

As conventional planarization methods, there are, for example, four methods shown below. As an example, ■ 3 p 3 G (
Boron Phospho 5ilicate Gl
There is a method of depositing an ass) film, melting it by high-temperature annealing at about 900° C. to flatten surface irregularities, and then forming, for example, aluminum wiring by vapor deposition sputtering or the like.

Another example is a method in which liquid glass is applied to the surface using 5OG (spin-on glass), the liquid glass is collected in the recesses, and the liquid is evaporated by drying to flatten the surface.

As another example, as shown in FIG. 5(A), an insulating film 1 is formed by the CVD method on the uneven surface, and an SOG film 2 is further formed on the surface, and then as shown in FIG. 5(B). CVD insulation g11 and 5OGI by etching as shown
I! There is a so-called etch-back method in which 2 is removed and planarized.

As another example, there is a method (2) in which a suspension of fine powder particles of an insulating material mixed in a solvent is applied to an uneven surface to flatten the surface. This one is, for example, published in Japanese Unexamined Patent Publication No. 58-1894.
As disclosed in Publication No. 3 (title of the invention ``Method for manufacturing a flattened integrated circuit structure''), glass adhered to the surface of the structure is made to flow and embedded in irregular parts of the surface, Method for flattening the surface, also disclosed in Japanese Patent Application Laid-Open No. 1408-1983
As disclosed in Publication No. 84 (title of invention "Method for manufacturing semiconductor device"), silica (Sf
This is a method in which a suspension of powder is applied to flatten the surface.

[Problem to be solved by the invention]

Since the temperature at which the BPSG film softens is generally high, the method shown in (2) above will unnecessarily diffuse source and drain impurities in the substrate in highly integrated circuits of the future. This poses a problem that is disadvantageous for high integration and miniaturization. In addition, even if the BPSG film is softened, a high annealing temperature or a high I of 11 degrees is required for the BPSG film of boron and phosphorus in order to obtain a good surface flatness. If planarization is attempted at a lower annealing temperature, the surface of the film tends to become rough. Also,
BPSG requires an annealing temperature of 700°C or higher to make it flat even if the boron and phosphorus concentrations are high.
In particular, it cannot be used as a planarization method after depositing a low-melting point substance such as aluminum, and there is a problem that the scope of use is narrow.

In addition, the method shown in (1) above has the problem that the liquid glass is also applied to the convex portions that are the wiring portions, so it only reduces the difference in unevenness, and the surface cannot be flattened well. .

In addition, the method shown in (2) above has the problem that the process is complicated and the cost is high.Generally, the etching rate is different from that of the CVD insulating film 1 and the SOG film because the film quality differs slightly for each wafer. There was a problem that the surface did not match the film 2, and as a result, grooves were formed on the surface, making it impossible to flatten the surface well.

In addition, in the method shown in (1) above, an insulating film is formed by applying a suspension to both the concave and convex surfaces, and in order to flatten the surface, it is necessary to apply a suspension to both the concave and convex surfaces, as shown in Figure 6, for example. There was a problem that it was necessary to form a thick insulating film 3, and the surface could not be flattened well.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can achieve good surface planarization at relatively low temperatures and through simple steps.

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the method of the invention. In the figure, 30 is a convex portion and 31 is a concave portion. Reference numeral 34 denotes a suspension, which contains fine particles 32 having a sufficiently small particle size relative to the concave portions 31, has no adhesion to the substance constituting the convex portions 30, and is
A solvent 33 is selected that has adhesion to. The present invention includes a step of applying this suspension 34 to the entire surface where the convex portions 30 and recesses 31 are located, and a step of evaporating the solvent 33 of the applied suspension 34.

[Effect]

In the present invention, the solvent for the suspension is selected to be one that does not adhere to the convex portions 30 but has adhesive properties to the concave portions 31. As a result, the suspension does not rest on the upper surface of the convex portion 30, but accumulates only in the concave portion 31, and the surface can be flattened well without using methods such as high-temperature annealing or etch-back as in conventional examples. Furthermore, the surface can be flattened better than the conventional method using SOG, which does not have selectivity for convex portions and concave portions, or the method using a suspension using fine glass powder particles.

〔Example〕

FIG. 2 shows a manufacturing process diagram of a first embodiment of the method of the present invention.

In FIG. 2(A), silicon oxide l1lJ11 is formed on the surface of a silicon substrate 10, and a polysilicon layer I! (g! Thickness e.g. 5 (101~1~1μl
1l) Form 12 into butter.

Next, the grooves (concave portions) 13 between the wirings (convex portions) 12 are filled with an insulating layer 14 .

Here, a method for forming the insulating layer 14 will be explained.

For example, the average particle diameter 70η-+(1!!1 part 13 width (several 1
0001.1), which is sufficiently small compared to 0001.1), is mixed with a solvent of pure water, for example.
Make a suspension. In this case, the solvent has water-breaking properties for the material (polysilicon) constituting the wiring 12, which is the convex portion,
In addition, a material that has adhesion to the material constituting the recess 13 (silicon oxide) is selected. As described above, the present invention is characterized in that the solvent for the suspension used in forming the insulating layer 14 for filling the grooves is selected to have water-breaking properties in the convex portions and adhesive properties in the concave portions. be.

Since the solvent for the suspension is selected to have water-breaking properties for the convex portions 12, the suspension does not rest on the upper surface of the convex portions 12, but accumulates only in the concave portions 13.

Next, when the solvent is dried and evaporated, silicon oxide fine particles are deposited in the recesses 13, and the surface is well flattened. In this case, drying causes the surface of the insulating layer 14 to
It may be slightly lower than the surface of the surface, but in that case, just apply a small amount of the suspension again and let it dry.

Next, as shown in FIG. 2(B), a silicon oxide film (or PSG
(It may be a film) 15 is formed. In this case, Fig. 2 (A
Since the surface can be flattened well in the process shown in ), it is possible to form a dense and flat silicon oxide film 15 that has good insulation from the upper layer wiring formed in the subsequent process.

As described above, according to this embodiment, since it can be manufactured at a lower temperature than the conventional example (2) described above, impurities in the source and drain in the substrate are not unnecessarily diffused, and the surface is not roughened. In addition, the surface can be better flattened than the conventional examples (■) and (2) described above, and furthermore, unlike the conventional example (■) described above, the surface is not flattened by etch-back, so from this point of view as well, the surface can be flattened better. It can be flattened with fewer steps than the conventional method ■! I can do 1lT1.

FIG. 3 shows a manufacturing process diagram of a second embodiment of the method of the present invention.

The process is the same as the first embodiment shown in FIG. 2 until the wiring 12 shown in FIG. 3(A) is formed. Next, a silicon oxide film 11a is formed on this surface as shown in FIG. 3(B).

In this case, silicon oxide ll111 is also applied to the side wall of the convex portion 12.
The thickness of the silicon oxide film 11a in the recess 13 is slightly thicker than that in the step shown in FIG. 3(A). Next, in the same figure (C),
The silicon oxide film attached to the upper surface of the convex portion 12 is removed by anisotropic etching (RIE). This anisotropic etching results in silicon oxide It! in the recess 13. 11a is also slightly removed, which is almost the same as in the step shown in FIG. 3(A).

Next, in FIG. 2D, a suspension 16a similar to that of the first embodiment described above is applied and filled into the recess 13. At this time,
Since the silicon oxide 1111a is also attached to the side wall of the convex portion 12, the suspension 16a adheres well not only to the bottom surface of the concave portion but also to the side wall of the convex portion 12, and -h, to the top surface of the convex portion 12. Since there is no silicon oxide film 11a, it does not adhere due to water-breaking properties.

In this manner, the suspension 16a can be brought into close contact with both the bottom surface of the recess and the side wall of the convex portion, which is particularly suitable for fine patterns in which the diameter of the recess 13 is extremely small. Next, in FIG. 5E, when the solvent is dried and evaporated, silicon oxide fine particles are deposited in the recesses 13 to form an insulation 1fW16, and the surface is well flattened.

FIG. 4 shows a manufacturing process diagram of a third embodiment of the method of the present invention.

This is applied to trench isolation controllers. In FIG. 4(A), a trench 18 is formed in the silicon substrate 17, and then, in FIG. 4(B), a silicon oxide film 19 is formed on the entire surface. Here, trench 1
When a resist film (not shown) is embedded in 8a and anisotropic etching is performed and the resist film is removed, the same figure (C
), the silicon oxide film 19a remains only in the trench 18.

Next, when a suspension of silicon oxide fine particles and a solvent is applied to this surface, trenches 18a are formed as shown in FIG.
The suspension is embedded only in the In this case, a solvent is selected that has water breaking properties for the silicon substrate 17 and adhesive properties for the silicon oxide film 19a in the trench 18. Subsequently, the solvent of the suspension is evaporated by drying,
An insulator 20 of silicon oxide fine particles is embedded in the trench 18a, and no insulator is formed on the silicon substrate 17.
The surface is well flattened. In this way, even in a trench isolation structure with a small diameter, the surface can be satisfactorily flattened.

Although pure water was used as the solvent for the suspension in the above example, the solvent is not limited to this, and a solvent that does not adhere to convex portions but adheres to concave portions may also be used. Just choose.

[Effects of the Invention] As explained above, according to the present invention, the surface can be satisfactorily flattened at a relatively low temperature and through a simple process.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the method of the present invention, Figure 2 is a diagram of the manufacturing process of the first embodiment of the method of the invention, Figure 3 is a diagram of the manufacturing process of the second embodiment of the method of the invention, and Figure 4 is a diagram of the present invention. FIG. 5 is a manufacturing process diagram of a third embodiment of the inventive method, FIG. 5 is a manufacturing process diagram of an example of the conventional method, and FIG. 6 is a configuration diagram illustrating another example of the conventional method. 14, 16, and 20 are insulating layers, 18.18a are trenches, 30 are convex portions, 31 are concave portions, 32 are fine particles, 33 are solvents, and 34 are suspension liquids. Patent applicant Fujitsu Ltd. In the diagram, 10.17 is a silicon substrate, 11.11a, 15.19.19a are silicon oxide films, 12 is a polysilicon wiring (convex part), 13 is a groove (concave part), * Figure 1, (A) Figure 5 if! 6! ! 1 Figure 3 Written amendment June 22, 1989 1. Indication of the case 1986 2. Name of the invention Method for manufacturing semiconductor devices 3. Person making the amendment Address related to the case 221 Name (552) Representative 4. Agent address: 211283, 5-7 Kojimachi, Chiyoda-ku, Tokyo 102

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which a surface having convex portions (30) and concave portions (31) is planarized includes fine particles (32) having a sufficiently small particle size relative to the concave portions (31). A suspension (34) containing a selected solvent (33) that does not have adhesion to the substance constituting the convex portion (30) and has adhesion to the concave portion (31);
A step of coating the entire surface with the convex portions (30) and concave portions (31), and a step of applying the solvent (33) of the applied suspension (34).
) evaporating a semiconductor device.