JPH0258827A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0258827A JPH0258827A JP21120388A JP21120388A JPH0258827A JP H0258827 A JPH0258827 A JP H0258827A JP 21120388 A JP21120388 A JP 21120388A JP 21120388 A JP21120388 A JP 21120388A JP H0258827 A JPH0258827 A JP H0258827A
- Authority
- JP
- Japan
- Prior art keywords
- wiring electrode
- electrode film
- regions
- dopant
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 33
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 abstract description 4
- 239000002019 doping agent Substances 0.000 abstract 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の配線電極の形成方法に関し、特
に高配線寿命を有する配線電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming a wiring electrode for a semiconductor device, and particularly to a wiring electrode having a long wiring life.
配線電極金属は、高温、高電流密度になるほど、いわゆ
るエレクトロ・マイグレーションによす配線寿命が低下
する。エレクトロ・マイグレーション耐性を高め、配線
を高寿命化させた構造として、配線電極金属に不純物を
添加させた構造が使用されている。著名な例としては、
第4図の如く不純物として銅を含んだアルミニウムを配
線電極被膜13に用いた例がある。The higher the temperature and current density of the wiring electrode metal, the shorter the wiring life due to so-called electromigration. A structure in which impurities are added to the wiring electrode metal is used to improve electromigration resistance and extend the life of the wiring. A famous example is
As shown in FIG. 4, there is an example in which aluminum containing copper as an impurity is used for the wiring electrode coating 13.
従来の不純物を含む配線電極の製造方法は、配線電極材
料に不純物が一様に含まれている配線電極金属を被着す
る方法、あるいは不純物を含まないか又は不純物を一様
に含んだ配線電極金属を被着したのち、不純物を全面に
添加する方法であった。このため、従来の方法で不純物
を添加した配線電極被膜にフォトレジストを施してパタ
ーン形成をする場合、プラズマによる異方性エツチング
では、不純物の割合によりエツチングが非常に困難にな
る。アルミニウムに銅を添加した場合、銅の添加量の増
加につれエレクトロ・マイグレーション耐性が大幅に向
上することが知られているが、高々数パーセントの銅の
添加により、異方性エツチングの際に銅が残りやすくな
り、銅の含まれる割合が異なる材料ごとにエツチングガ
ス、圧力などの条件を新たに求める必要があった。また
、液体による等方性エツチングでは、エツチング条件は
不純物量にあまり依存しないが、横方向のエツチングも
進行するため、あらかじめ配線幅を広く取らなければな
らないため微細加工に不向きであるという欠点があった
。Conventional methods for producing wiring electrodes containing impurities include a method of depositing a wiring electrode metal uniformly containing impurities on a wiring electrode material, or a method of manufacturing wiring electrodes that do not contain impurities or uniformly contain impurities. This method involved adding impurities to the entire surface after depositing the metal. For this reason, when forming a pattern by applying a photoresist to a wiring electrode film doped with impurities by the conventional method, etching becomes extremely difficult with anisotropic etching using plasma depending on the proportion of impurities. It is known that when copper is added to aluminum, the electromigration resistance is significantly improved as the amount of copper added increases. It was necessary to find new etching gas, pressure, and other conditions for each material with a different proportion of copper. In addition, in isotropic etching using a liquid, the etching conditions do not depend much on the amount of impurities, but since lateral etching also progresses, the wiring width must be widened in advance, making it unsuitable for microfabrication. Ta.
本発明では、配線電極被膜は不純物が添加された領域と
不純物が添加されていない領域とを設け、非添加領域を
エツチング除去する。In the present invention, the wiring electrode film is provided with an impurity-doped region and an impurity-free region, and the non-doped region is removed by etching.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の断面図であう。FIG. 1 is a sectional view of a first embodiment of the present invention.
第1図(a)は、配線電極被膜1上にフォトレジストを
施すことにより不純物導入マスク2を形成したのち不純
物3を例えばイオン注入により配線電極被膜1の配線電
極領域4のみに添加した図である。配線電極領域6以外
では不純物2は配線電極被膜1には添加されない。配線
電極被膜1は、必要に応じ電気的絶縁被膜5に部分的に
設けられた開口6を介して半導体基板7に接する。FIG. 1(a) is a diagram in which an impurity introduction mask 2 is formed by applying photoresist on the wiring electrode coating 1, and then impurities 3 are added only to the wiring electrode region 4 of the wiring electrode coating 1 by, for example, ion implantation. be. The impurity 2 is not added to the wiring electrode coating 1 except in the wiring electrode region 6. The wiring electrode coating 1 contacts the semiconductor substrate 7 via an opening 6 partially provided in the electrically insulating coating 5 as required.
第1図(b)は、第1図(a)の不純物導入マスク2を
除去したのち配線電極被膜上にエツチングマスク8を例
えばフォトレジストにより形成した図である。エツチン
グされる領域には不純物が含まれないため、従来の技術
で異方性エツチングできる。FIG. 1(b) shows an etching mask 8 made of, for example, photoresist, formed on the wiring electrode coating after removing the impurity introduction mask 2 of FIG. 1(a). Since the region to be etched does not contain impurities, it can be anisotropically etched using conventional techniques.
第1図(c)は、異方性エツチングを施し配線電極9を
形成したのち、アロイすることにより、配線電極全体に
不純物を拡散させた図である。アルミニウムに銅を添加
した場合では、450−500℃のアロイでよい。FIG. 1(c) is a diagram in which the wiring electrode 9 is formed by anisotropic etching and then impurities are diffused throughout the wiring electrode by alloying. When copper is added to aluminum, an alloy of 450-500°C may be used.
第2図は、本発明の第2の実施例の断面図である。この
図では、不純物3を第1の配線電極被膜10と第2の配
線電極被膜11ではさんでおり、不純物がアロイの雰囲
気と反応するのを防ぎ、更に、拡散距離が半分になるの
でアロイ時間を短くできる。この方法は、不純物を蒸着
あるいはスパッタリングして形成した場合に特に有効で
ある。FIG. 2 is a cross-sectional view of a second embodiment of the invention. In this figure, the impurity 3 is sandwiched between the first wiring electrode coating 10 and the second wiring electrode coating 11, which prevents the impurity from reacting with the atmosphere of the alloy.Furthermore, since the diffusion distance is halved, the alloying time is can be shortened. This method is particularly effective when impurities are formed by vapor deposition or sputtering.
第3図は、本発明の第3の実施例の断面図である。この
図では、配線電極9下に導電性を有する不純物拡散障壁
12を設けた場合である。この不純物拡散障壁は、銅な
どの重金属を配線電極被膜に添加した場合、重金属が半
導体基板に拡散して欠陥を生成し、リーク電流を発生す
るのを防ぐために用いる。このような不純物拡散障壁の
例としては、窒化チタンなどがある。窒化チタンは、銅
、アルミニウム、シリコンの相互拡散を500℃以上ま
で抑える。FIG. 3 is a sectional view of a third embodiment of the invention. In this figure, a conductive impurity diffusion barrier 12 is provided below the wiring electrode 9. This impurity diffusion barrier is used to prevent heavy metals such as copper from diffusing into the semiconductor substrate and creating defects and generating leakage current when heavy metals such as copper are added to the wiring electrode coating. An example of such an impurity diffusion barrier is titanium nitride. Titanium nitride suppresses interdiffusion of copper, aluminum, and silicon to temperatures above 500°C.
以上説明したように本発明は、配線電極被膜の配線領域
に選択的に不純物を添加することにより、エツチングさ
れる領域に不純物が含まれない構造にすることができ、
不純物の種類、濃度によらず配線電極金属単体の加工技
術が使えるという効果がある。As explained above, in the present invention, by selectively adding impurities to the wiring region of the wiring electrode coating, it is possible to create a structure in which impurities are not contained in the region to be etched.
This has the advantage that processing technology for a single wiring electrode metal can be used regardless of the type or concentration of impurities.
第1図(a)〜(c)は本発明の第1の実施例の断面図
、第2図は本発明の第2の実施例の断面図、第3図は本
発明の第3の実施例の断面図、第4図は従来の不純物を
全面に含む場合の断面図である。
l・・・・・・配線電極被膜、2・・・・・・不純物導
入マスク、3・・・・・・不純物、4・・・・・・配線
電極領域、5・・・・・・電気的絶縁被膜、6・・・・
・・開口、7・・・・・・半導体基板、8・・・・・・
エツチングマスク、9・・・・・・配線電極、10・・
・・・・第1の配線電極被膜、11・・・・・・第2の
配線電極被膜、12・・・・・・不純物拡散障壁、13
・・・・・・配線電極被膜。
(12ン
(b)
茅
!
図
茅
図
乎
回
井
ガ1(a) to (c) are cross-sectional views of a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a third embodiment of the present invention. A cross-sectional view of an example, FIG. 4 is a cross-sectional view of a conventional case where the entire surface contains impurities. 1... Wiring electrode film, 2... Impurity introduction mask, 3... Impurity, 4... Wiring electrode region, 5... Electricity Insulating coating, 6...
...Opening, 7...Semiconductor substrate, 8...
Etching mask, 9... Wiring electrode, 10...
...First wiring electrode film, 11... Second wiring electrode film, 12... Impurity diffusion barrier, 13
・・・・・・Wiring electrode coating. (12nd (b) Mo!
Claims (3)
電気的絶縁膜を有する半導体基板の一主面に被着された
配線電極被膜において、該配線電極被膜の配線領域に選
択的に不純物を添加し、該配線電極被膜の不純物の非添
加領域をエッチング除去することを特徴とする半導体装
置の製造方法。(1) In a wiring electrode coating deposited on one main surface of a semiconductor substrate having a predetermined pn junction and optionally an electrical insulating film on the surface, selectively 1. A method of manufacturing a semiconductor device, comprising adding an impurity to the wiring electrode film, and etching away a region of the wiring electrode film to which the impurity is not added.
着またはスパッタによることを特徴とする特許請求の範
囲第(1)項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), wherein the method for adding the impurity is ion implantation, vapor deposition, or sputtering.
を含むアルミニウムであり、上記不純物が銅であること
を特徴とする特許請求の範囲第(1)項記載の半導体装
置の製造方法。(3) The method for manufacturing a semiconductor device according to claim (1), wherein the wiring electrode film is aluminum or aluminum containing silicon, and the impurity is copper.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21120388A JPH0258827A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21120388A JPH0258827A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0258827A true JPH0258827A (en) | 1990-02-28 |
Family
ID=16602064
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21120388A Pending JPH0258827A (en) | 1988-08-24 | 1988-08-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0258827A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5254503A (en) * | 1992-06-02 | 1993-10-19 | International Business Machines Corporation | Process of making and using micro mask |
-
1988
- 1988-08-24 JP JP21120388A patent/JPH0258827A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5254503A (en) * | 1992-06-02 | 1993-10-19 | International Business Machines Corporation | Process of making and using micro mask |
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