JPH0258374A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a capacity element having large capacity with a small region so as to advance high integration of DRAM by making a lower electrode in the shape of a pot which has a bottom plate part above the specified part of a semiconductor region and a side plate part standing up from the whole circumference of the bottom plate part. CONSTITUTION:Being overlaid on the side face of a side wall, the upper face of an insulating film 10, and the side face (step part) and the upper face of an insulating film 14 for step formation, a lower electrode 11 is connected to the surface of an n<+>-type semiconductor region 8. For the lower electrode 11, since the part above the n<+>-type semiconductor region 8 becomes recessed, if the bottom plate part of the part where it is overlaid on the surface of the n<+>-type semiconductor region 8 is defined as 11A, it becomes the shape like a pot which has a side plate part 11B standing up at the whole circumference. As the lower electrode 11 has such a side plate part 11B as is standing up not only in the direction that a data line is extending but also in the direction that a word line WL is extending, even if the region where it occupies in the main face of a semiconductor substrate 1 is small, it becomes large area. Accordingly, a capacity element with large capacity can be constituted between an upper electrode 13 and this lower electrode 11.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to a DRA
M (Dynamic Random Access
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having the following: (Mea+ory).

[Conventional technology]

A DRAM memory cell has a selection MISFET and a source for selecting the memory cell.

It is composed of an information storage capacitive element (hereinafter referred to as a capacitive element) connected in series to one of the drains. The gate electrode of the selection MISFET is connected to a word line extending in the row direction, and the operation of the selection MISFET is controlled by this word line.

Incidentally, with the miniaturization of DRAMs, the size of the capacitive element tends to be reduced, and securing a capacitance value has become an important issue.

Therefore, the lower ffi electrodes are placed on the semiconductor substrate in order from the bottom.

There is a technique in which a capacitive element is constructed by stacking a dielectric film and an upper electrode. This capacitive element is called a stacked capacitor. The lower electrode is connected to one semiconductor region of the one selection MISFET, and is provided so as to cover each of the word lines on both sides of the semiconductor region in the direction in which the data line extends. A silicon oxide film is provided on the side and top surfaces of the word line to insulate it from the lower electrode. When a capacitive element is configured in this way.

Since a portion of the lower electrode is directed upward according to the silicon oxide film on the side surface of the word line, a large area of the lower electrode can be obtained in a small area. Since the cross-sectional shape of the upper electrode also has the same shape as the lower electrode through the dielectric film, a capacitive element with a large capacity can be obtained. In addition,
The technology related to stacked capacitors is disclosed in Japanese Patent Application Laid-Open No. 61-1
It is described in No. 83952.

(Problems to be Solved by the Invention) As a result of studying the stacked capacitor, the inventor found the following problem.

Since the lower electrode of the stacked capacitor is directed upward by the silicon oxide film on the side of the word line in the direction in which the data line extends, the lower electrode can have a large area in a small area.

However, in the direction in which the word line extends, there is no step that would direct the peripheral portion of the lower electrode upward, so that the word line is flat. For this reason.

As the miniaturization of memory cells progresses further, the area of the lower electrode becomes extremely small, posing a problem that it becomes impossible to obtain the capacity necessary to retain information.

An object of the present invention is to provide a technique that can improve the degree of integration of DRAM and improve the information retention characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory cell is formed by a lower electrode connected to the surface of a predetermined portion of the semiconductor region, which is the source and drain of the selection MI 5FET, and an upper electrode provided on the lower electrode via a dielectric film. In a semiconductor integrated circuit device configured with a capacitive element, the lower electrode has a pot shape, and has a bottom plate portion above a predetermined portion of the semiconductor region, and a side plate portion rising from the entire circumference of the bottom plate portion. It is something that exists.

[Effect]

According to the above-described means, since the side plate portion is provided over the entire edge of the lower electrode, it is possible to obtain a lower electrode with a large area in a small area. Since the upper electrode has the same shape as the lower electrode through the dielectric film, a capacitive element with a large capacity can be obtained in a small area. Thereby, it is possible to achieve high integration of the DRAM, and it is also possible to improve the information retention characteristics.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a DRAM memory cell according to an embodiment of the present invention, and FIG. 2 is a plan view of the DRAM memory cell shown in FIG. 1 with the data line and the upper electrode of the capacitive element removed. Plan View FIG. 3 is a plan view showing an enlarged part of the memory cell shown in FIG. 2.

FIG. 4 is a sectional view taken along the TV-IV cutting line in FIG. 1; FIG. 5 is a cross-sectional view taken along the line ■--■ in FIG. 1.

FIG. 6 is an enlarged perspective view of a portion of the memory cell shown in FIGS. 1 to 5 where a lower electrode is provided.

FIG. 7 is an enlarged perspective view of the lower electrode provided in the portion shown in FIG. 6 where the lower electrode is provided.

First, the schematic structure of a memory cell will be explained using FIGS. 1, 2, and 4.

In FIGS. 1, 2, and 4, 1 is a semiconductor substrate made of p-type single crystal silicon, 2 is a field insulating film made of silicon oxide film, and 3 is a p-type channel stopper region. The memory cell selection MISFET is provided to relieve the electric field in the gate insulating film 4 made of a thin silicon oxide film, the gate electrode 5 made of, for example, a Go-type polycrystalline silicon film, and the channel region of the source and drain. an n-type semiconductor region 6; and an n°-type semiconductor region 7 forming a portion of the substrate at the bottom of the capacitive element other than the n-type semiconductor region 6.
and the n-type semiconductor region 6 at the connection portion of the data line to the substrate.
The n-type semiconductor region 8 forms the other part. The gate electrode 5 also forms a word line WL, and sidewall spacers 9 made of a silicon oxide film are provided on both sides thereof. Furthermore, an insulating film 10 made of a silicon oxide film is provided on the word line WL. on the other hand.

The capacitive element of the memory cell includes a lower electrode 11 made of, for example, an n-type polycrystalline silicon film, a dielectric film 12 provided on the surface of the lower electrode 11, and a dielectric film 12 made of, for example, n-type polycrystalline silicon. A lower electrode 11 composed of an upper electrode 13 made of a film and a lower electrode 11 is connected to the surface of the n° type semiconductor region 8 (ie, a predetermined portion).

Reference numeral 13A denotes an opening where the upper electrode 13 is partially removed at a portion where the data line 17 is connected to the n-type semiconductor region 7. The upper electrode 13 is attached to the surface of the dielectric film 12 and is provided over almost the entire memory cell array region of the semiconductor substrate 1 .

Next, the shape of the lower electrode 11 will be specifically explained.

First is the side wall spacer 9, which is the third
As shown in the figure, it is provided along the side surface of the word line WL. In addition, in FIG. 3, the sidewall spacer 9 is shown as a mesh, and as shown in FIGS. 2, 3, and 6, there are two A step-forming insulating film 14 made of, for example, a silicon oxide film is buried between the words vAWL. However, 1
The step forming insulating film 14 is selectively removed above the n° type semiconductor region 8 to expose the n° type semiconductor region 8. In addition, in FIGS. 2 and 3, the step forming insulating film 14 is shown with a large number of black dots (.). The thickness of the insulating film 14 for forming a step on the field insulating film 2 is about the same as the thickness of the word line WL and the insulating film 10 on it, so it is the same as the insulating film for forming one step. There is no step difference between the film 14 and the insulating film 10. However, as shown in FIG.
A step is formed between the semiconductor region 8 and the °-type semiconductor region 8 . Then, when the lower electrode 11 is connected to the surface of the n-type semiconductor region 8 by being attached to the side surface of the side wall 9, the side surface (step portion) and the upper surface of the insulating film 14 for forming one step on the upper surface of the insulating film 10, The shape of the lower electrode 11 is as shown in FIG. That is, since the lower electrode 11 has a depressed portion above the -n' type semiconductor region 8, the bottom plate portion of the portion adhering to the surface of the n'' type semiconductor region 8 is designated as IIA.

It has a pot-like shape with a side plate portion 11B standing upright around its entire circumference. In this way, the lower electrode 11 connects the data line 1
The side plate portion 11B stands up not only in the direction in which the word line WL extends, but also in the direction in which the word line WL extends.
Therefore, even if the area occupied on the main surface of the semiconductor substrate 1 is small, the lower electrode 11 has a large area. On the other hand, since the upper electrode 13 only has the thin dielectric film 12 interposed between it and the lower electrode 11, the upper electrode 13 has a similar shape with a substantially constant distance between it and the lower electrode 11. There is.

Therefore, a capacitive element with a large capacitance can be formed between the portion of the upper electrode 13 above the lower electrode 11 and this lower electrode 11.

An interlayer insulating film 15 is provided on the upper electrode 13 to insulate it from the data line 17. Reference numeral 16 denotes a connection hole for connecting the data line 17 to the n-type semiconductor region 7.

The step formation insulating film 14 is formed by forming a thick silicon oxide film by, for example, CVD, covering the sidewall spacer 9 and the insulating film 10 until the upper surface becomes almost flat, and then forming the silicon oxide film as shown in FIGS. 2 and 3. It is formed by selectively etching unnecessary parts other than those shown. In order to avoid etching the sidewall spacers 9 during the etching, first, the word where the step formation insulating film 14 is not provided between them, the central portion between the IWL and the word line WL, and the n-type semiconductor region are etched. The center portion of 8 is etched in a narrow width using an anisotropic etching method using a resist film.

This etching is performed until the surfaces of n° type semiconductor region 7 and n° type semiconductor region 8 are exposed. Next, with the resist film left as it is, etching is performed with oxygen (02) included in the etching gas. If oxygen is present in the etching gas, the surface of the resist film will be ashed and the side surfaces of the opening will gradually recede.
The opening part can be made into a tapered shape. Therefore, etching of the sidewall spacer 9 can be suppressed as much as possible, and unnecessary step-forming insulating film 14 can be removed.

Note that the insulating film 14 for forming a step may be formed by the following method. First, the sidewall spacer 9 made of a silicon oxide film is formed so that the sidewall width is smaller than the standard value. The insulating film 14 is formed by, for example, CVD.
Then, a silicon oxide film is formed with good coverage so as to cover the sidewall spacers 9 and the insulating film 10. Figures 2 and 3
A resist mask is provided on the portion of the step-forming insulating film 14 shown in the figure and anisotropic etching is performed. By anisotropically etching the resist mask, the step forming insulating film 14 is removed above the n° type semiconductor region 8. At that time, the sidewall width increases and approaches the target value. In this case, since the insulating film 14 for forming a step on the field insulating film 2 is formed with good coverage with respect to the underlying layer, the insulating film 14 for forming one step and the insulating film 10 are formed on the field insulating film 2 with good coverage as shown in FIG. The difference in level between them is maintained.

Further, the step forming insulating film 14 may be formed of a material 1, for example, a nitride film, which is different from the field insulating film 2 serving as the base and the insulating films forming the sidewall spacers 9 and the like.

The gate electrode 5 (word line WL) is made of a high melting point metal (M
o, Ti, Ta, W) films and high melting point metal silicide films (M
o 512 + T I S x x r W S
iz). Further, the gate electrode 5 is n
It may be constructed of a two-layer film in which the high melting point metal film or the high melting point metal silicide film is laminated on the °-type polycrystalline silicon film. The n-type semiconductor region 6 and the n°-type semiconductor region 7 are
It is formed by introducing type impurities by ion implantation. The n-type semiconductor region 8 is formed by diffusing the n-type impurity in the lower electrode 11 into the semiconductor substrate 1. The dielectric film 12 is basically formed by forming a silicon nitride film on the lower electrode 11 by, for example, CVD, and oxidizing the surface of this film at high pressure. However, in reality, a silicon oxide film is formed on the surface of the lower electrode 11 by natural oxidation before the silicon nitride film is formed. 6M is a three-layer film made of stacked silicon films.
The interlayer insulating film 15 is a silicon oxide film.

Silicon oxide film capable of glass flow (B P S G
) consists of a two-layer film of 11M. Data line '17
It consists of a three-layer film in which a barrier metal film, an aluminum film, and a protective film are laminated from the bottom. The barrier metal film and the protective film are made of metal silicide (MoSi, WSxz
) consists of a membrane. The aluminum film between them is
Elements (Cu, Pb, Ti, etc.) are added to prevent aluminum spikes.

Note that, as shown in FIG. 8, the step-forming insulating film 14 is made as thick as possible to form a large lower electrode 1 of the side plate portion 11B.
1 may be formed.

As explained above, the source of MISFET for 1 selection,
A lower electrode 11 connected to the surface of a predetermined portion (semiconductor region 8) of the semiconductor regions 7 and 8 which is a drain, and an upper electrode 13 provided on the lower electrode 11 with a dielectric film 12 interposed therebetween. In a semiconductor integrated circuit device in which a capacitive element of a memory cell is configured.

Since the lower electrode 11 has a pot shape having a bottom plate portion 11A above the semiconductor region 8 (predetermined portion) and a side cutout portion 11B rising from the entire circumference of the bottom plate portion 11A,
Since the side plate portion 11B is present over the entire edge of the lower electrode 11, it is possible to obtain the lower electrode 11 with a large area. Since the upper electrode 13 has the same shape with the dielectric film 12 interposed therebetween in the portion above the lower electrode 11, a capacitive element with a large capacitance can be obtained in a small area. This results in
The DRAM can be highly integrated, and the information retention characteristics can be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The entire edge of the bottom electrode is directed upward, and the top electrode has a similar shape above the bottom electrode through a dielectric film, making it possible to obtain a capacitive element with large capacity in a small area. . Thereby, it is possible to achieve high integration of the DRAM, and it is also possible to improve the information retention characteristics.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a DRAM memory cell according to an embodiment of the present invention, and FIG. 2 is a diagram showing the DRAM memory cell shown in FIG. 1 with the data line and the upper electrode of the capacitive element removed. 3 is an enlarged plan view of a part of the memory cell shown in FIG. 2, FIG. 4 is a sectional view taken along the mV-IV cutting line in FIG. 1, and FIG. 5 is a plan view showing a part of the memory cell shown in FIG. , a cross-sectional view taken along the section line ■-■ in FIG. FIG. 6 is an enlarged perspective view of a portion of the memory cell shown in FIGS. 1 to 5 in which a capacitive element is provided, and FIG. 7 is a portion in which a capacitive element shown in FIG. 6 is provided. FIGS. 8 and 9 are enlarged perspective views showing the lower electrode provided in the main part of a semiconductor integrated circuit device that is different from the embodiment of the present invention shown in FIGS. 1 to 7. FIG. In the figure, 5... gate electrode, 6... n-type semiconductor region,
7.8... n° type semiconductor region, 9... side wall spacer, 10... insulating film, 11... lower electrode,
IIA...Bottom plate part, IIB...Side plate part, 12...
Dielectric film, 13... Upper electrode, 14... Insulating film for step formation. Figure 1 Figure 3 Figure 8

Claims (1)

[Claims] 1. A lower electrode connected to the surface of a predetermined portion of the semiconductor region, which is the source and drain of the selection MISFET, and an upper electrode provided on the lower electrode with a dielectric film interposed in the memory cell. In a semiconductor integrated circuit device including a capacitive element, the lower electrode has a pot-like shape having a bottom plate portion above a predetermined portion of the semiconductor region and a side plate portion rising from the entire periphery of the bottom plate portion. A semiconductor integrated circuit device characterized by: