JPH0257012A - Synchronous driver circuit - Google Patents

Abstract

PURPOSE:To prevent a through current from flowing at the time of transition by turning on one of two MOS transistors in an external side after the turning-on or off condition of second and third MOS transistors in an internal side is determined. CONSTITUTION:When a synchronizing signal phi is transited to a high logical level VDD, among MOS transistors 1-4, only the MOS transistor 2 is turned on. Then, the logical level of an output signal OUT is not changed. Next, when the synchronizing signal phi is transited to a low logical level GND, the MOS transistor 1 is newly turned on and the output signal OUT is transited to the high logical level VDD. After that, when the synchronizing signal phi is transited to the high logical level VDD again, only the MOS transistor 3 is turned on and the logical level of the output signal OUT is not changed. Then, when the synchronizing signal phi is transited to the low logical level GND, the MOS transistor 4 is newly turned on and the output signal OUT is transited to the low logical level GND. Thus, since one of the MOS transistors 1-4, at least, is always turned off, there is no through current I2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous driver circuit in a digital integrated circuit having a CMOS transistor configuration, such as a bus driver.

[Conventional technology]

FIG. 4 is a diagram showing a conventional driver circuit having a C, MO5 configuration, as published in, for example, page 68 of "Introduction to rVLSI Design" published by Kyoritsu Shuppan Co., Ltd., December 1, 1981. In this figure, 2 is a P-channel type MOS transistor;
3 is an N-channel type MOS transistor, which has a small ON resistance and a large drive ability. Reference numeral 5 denotes an impeller having a CMOS configuration, which inverts and amplifies the input signal a.

50 is a high logic level power supply VDD, 51 is a low logic level GND power supply (ground), 52 is a P-channel type MOS transistor, and 53 is an N-channel type MOS transistor.

Next, the operation will be explained.

The power waveforms of the input signal a, the output signal S of the inverter 5, the output signal OUT, and the output load capacity when a capacitive load is connected between the output of the driver circuit and the ground 51 when the transition is shown in FIG. Charging current 11 of the charging tank and Mo3I
- shows the through current I2 passing through the transistor 2°3 and the current waveform of the power supply current IDD of the power supply 50;

With the rising transition of the input signal a, the output signal 1 of the inverter 5 changes from the high logic level VDD to the low logic level GN.
Transition to D. Then, the output signal OUT transitions from the low logic level GND to the high logic level VDD. Next, as the input signal a falls, the output signal of the inverter 5 changes from the low logic level GND to the high logic level VDD. Then, the output signal OUT is at a high logic level V
DD to low logic level GND. At the time of this transition of the output signal OUT, a through current I2 flows.

[Problem to be solved by the invention]

Since the conventional driver circuit is configured as described above, P-channel and N-channel type MOS transistors 2 and 3
There is a period when both are ON at the same time. In other words, the potential of the output signal of the inverter 5 is
-Threshold voltage of transistor 3 from VthN to VDD+P
Channel type MO3I-Threshold voltage v of transistor 2
This is the period that exists between thp. The same holds true when the input signal a falls, and a large through current I2 flows between times T1 and T2 in FIG. Therefore, in a microprocessor that uses a large number of driver circuits as described above, a large number of driver circuits transition simultaneously in synchronization with the clock, so a large current flows at times, increasing power consumption and reducing the A1 wiring. There have been problems with migration and generation of noise voltages, which can cause malfunctions of digital integrated circuits.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a driver circuit that does not cause a through current to flow during transition of a MOS transistor having a large drive ability.

[Means to solve the problem]

The synchronous drive circuit according to the present invention includes first and second P-channel type MCl5I-transistors connected in series between a first power source and a second power source, and third and fourth N-channel type MCl5I-transistors. A first MOS transistor that turns on one of the second MOS transistor and the third Mo3) transistor in response to an input signal synchronized with the synchronization signal.
, and this first logic gate allows a second M
After the OS+/Runcistor is turned on, the first Mo3I
- Consists of a second logic gate that turns on the transistor, and a third logic gate that turns on the fourth Mo5I transistor after the third MOS transistor is turned on by the first logic gate. It is.

[Effect]

In this invention, the first to fourth Mo3I-runsistors are arranged in the first to fourth Mo3I-run cistors. Second. Driven by the third logic gate, turning on the inner second and third MOS transistors
Or after determining the OFF state, the outer two Mo3I
-One of the transistors turns on.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 is a circuit diagram showing an embodiment of a synchronous driver circuit according to the present invention. In FIG. 1, the same reference numerals as in FIG.
The resistance is small and the drive capacity is high. 5 is two synchronizing signals φ, 0 which inverts the input signal a synchronized with φ
This is an inverter with MO3 configuration. 6.7 is 0M each
It is a NAND, NOR gate with O3 configuration, and the input signal a
and the two synchronization signals φ, φ are manually input into the P-channel type M.
The OS transistor 1 and the N-channel Mo3I-transistor 4 are each driven. Further, 8.9.10 is an inverter, 11° 14 is a P-channel type MOS transistor, 12° 13 is an N-channel type MOS transistor, and P-channel type MO3I- transistor 11 and N-channel type MOS +- transistor 12 are connected. and two sets of transfer gates 3 composed of a P-channel MOS transistor 14 and an N-channel MOS transistor 13.
00.400 and inverters 8, 9 and 10 constitute a latch circuit. This latch circuit supplies the input signal a of the synchronous driver circuit 100, and also shares the synchronous signal φ with the synchronous driver circuit 100, and generates another synchronous signal φ obtained by inverting this synchronous signal φ with the inverter 8. supply.

FIG. 2 shows the input signal IN of the latch circuit in response to the input signal a of the synchronous driver circuit 100 in which the input signal IN of the latch circuit in FIG.
, two synchronous signals φ, φ, and a synchronous tri-eight circuit 10
0 input signal a and the output signal of inverter 5, NA
Output load when a capacitive load is connected between the output signal C of the ND gate 6, the output signal d of the NOR gate 7, the voltage waveform of the output signal OUT, and the output of the synchronous driver circuit 100 and the ground 51. Charging current for charging capacity■1
, the through current I2 passing through the MOS transistors 1 and 2°3.4, and the current waveform of the power supply current IDD of the power supply 50.

When the synchronization signal φ transits to the high logic level VDD, the other synchronization signal T becomes the low logic level GND by the inverter 8, and the transfer gate 400 is turned off. At this time, it is assumed that the input signal IN of the latch circuit is at a high logic level VDD. Then, the two stages of inverters 9 and 1 connected in series serve as the input signal a of the synchronous driver circuit 100.
0 output signal of high inverter 9.10 causes high logic level VD[l. Then, the output signal of the inverter 5 becomes the low logic level GND. Also,
The output signal C of the NAND gate 6 is connected to another synchronization signal A,
Since the input signal a is NANDed, the output signal d of the NOR gate 7 is at a high logic level VDD, and the output signal d of the NOR gate 7 is NORed with the synchronizing signal φ and the input signal a, so it is at a low logic level GND. At this time, only MOS transistor 2 among MOS transistors 1.2.3.4 is turned on, and the logic level of output signal OUT remains unchanged.

Next, when the synchronization signal φ transitions to the low logic level GND,
The other synchronization signal 1 is set to high logic level VD by inverter 8.
D, the transfer gate 300 becomes ○FFL, and the transfer gate 400 turns ON. At this time, the output signals of the inverters 9 and 10 connected in series in two stages are positively fed back to the input of the inverter 9 through the transfer gate 400, so that the logic level of the input signal a of the synchronous driver circuit 100 is set to a high logic level. The level remains at VDD. However, the output signal C of the NAND gate 6 is different from the other synchronization signal φ
and NAND of the input signal a of the synchronous driver circuit 100
Since it takes , it transitions to the low logic level GND. On the other hand, NO
The output signal d of the R gate 7 remains at the low logic level GND because it performs a NOR operation with the synchronization signal φ and the input signal a of the synchronous driver circuit 100. Then, in addition to MOS transistor 2 among MOS transistors 1, 2, 3, 4, MO3I-transistor 1 turns on, and the output signal OUT
transitions to high logic level VDD.

Next, when the synchronization signal φ transits to the high logic level VDD again, the input signal IN of the latch circuit changes to the low logic level GND.
Suppose it was. Then, the other synchronization signal 1 is set to the low logic level GND by the inverter 8, and the transfer gate 300 is turned ONL and the transfer gate 400 is turned OFF.
Therefore, the output signal of the two stages of serially connected inverters 9.10, which is the input signal a of the synchronous driver circuit 100, becomes the low logic level GND by the inverter 9.10. Then, the output signal of inverter 5 becomes
This results in a high logic level VDD. Further, the output signal C of the NAND gate 6 is a high logic level VDD because it is NANDed with another synchronization signal T and the input signal a of the synchronous driver circuit 100, and the output signal d of the NOR gate 7 is
Since the synchronous signal φ is NORed with the input signal a of the synchronous driver circuit 1oO, it is at a low logic level GND. That is, since only MOS transistor 3 among MOS transistors 1.2.3.4 is turned on, the logic level of output signal OUT remains unchanged.

Next, when the synchronization signal φ transitions to the low logic level GND,
The other synchronization signal i is set to high logic level VD by inverter 8.
D, the transfer gate 300 is turned off and the transfer gate 400 is turned on. Then, the output signals of the two stages of inverters 9 and 10 connected in series are positively fed back to the input of the inverter 9 through the transfer cable 1-400.
0') The logic level remains at VDD (Mr. Lee's theory). Moreover, the output signal C of the NAN D gate 6 is
Since the other synchronous signal φ and the input signal a of the synchronous driver circuit 100 are NANDed, it remains at the high logic level VDD, and the output signal d of the NOR gate 7 is the synchronous signal φ and the synchronous driver circuit 10Q. By performing a NOR operation with the input signal a of the output signal a, the output signal transitions to a high logic level VDD. Then M.O.
Among the S transistors 1, 2, 3, and 4, 4 is newly turned ON in addition to MOS1-transistor 3, and the output signal OUT transitions to the low logic level GND.

In this way, in the synchronous dry circuit of this invention, M
If at least one of the OS
．． 2.3.4 There is no through current I2 flowing through the second
In the figure, the power supply current IDC of the power supply 50 flowing at the rising edge transition time T1 of the output signal OUT is equal to the charging current ■1.

In addition, in order to change the output signal OUT more quickly after the input signal a of the circuit 1000 changes to the synchronous type try by latching the input signal IN of the latch circuit, as shown in FIG.
a) As shown in FIG. 3(b), a second driver circuit 200 having a smaller drive capacity than the synchronous driver circuit 100 may be provided in parallel. An inverter constructed by connecting an even number of inverters 15 in series may be used.

Also, using the output of the NAND gate 6 as a human power, an output signal is obtained to the gate of the P-channel MOS transistor 1.
An even number of inverters connected in series is connected to NAND cables 1 and 6.
In addition, the output of the NOR gate 7 can be used manually to obtain an output signal to the 14-channel MOS l-run raster 40 gates. It may be inserted between the gates 1-7 and the N-channel MOS transistor 4.

Furthermore, the inverter 5 may be replaced by an odd number of inverters connected in series.

(Effects of the Invention) As explained above, the present invention provides first and second P-channel type power supplies connected in series between a first power source and a second power source.
MOS transistor, third and fourth N-channel type MOS transistors, and a second MOS transistor and a third MOS transistor in response to an input signal synchronized with a synchronization signal.
A first logic gate that turns on one of the OSl-transistors, and a second logic gate that turns on the first MOSl-transistor after the second MOSl-transistor is turned on by this first logic gate. ) and a third logic gate that turns on the fourth MOS transistor after the third MOS transistor is turned on by the first logic gate, so it is possible to use a large MOS transistor for driving.
- There is no through current during transistor transition, which reduces power consumption, and also eliminates migration of Afl wiring and generation of noise, which can cause malfunctions.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a synchronous driver circuit according to the present invention, FIG. 2 is a diagram showing voltage waveforms and current waveforms at various parts of the embodiment of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a conventional driver circuit, and FIG. 5 is a diagram showing voltage waveforms and current waveforms at various parts of the conventional example shown in FIG. In the figure, 1, 2. 3. 4. 11. 12° + 3.14
．． 19.20 is MOS)-transistor, 5 B, 9.
10.15 is an inverter, 6 is a NAND gate, 7 is an N
OR gate, 50 is a power supply, 51 is a ground, 100 is a synchronous triver circuit, 200 is a second triver circuit, 300.
400 is a transfer gate. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 other people) Figure 200, Number F of Triba Team of Arithmetic 2] 5 Inverter Figure Figure

Claims (1)

[Claims] P-channel type first and second MOS transistors connected in series between the first power supply and the second power supply, third and fourth N-channel type MOS transistors, and an input synchronized with a synchronization signal. Upon receiving the signal, one of the second MOS transistor and the third MOS transistor is turned on.
a first logic gate that turns on the first MOS transistor after the second MOS transistor is turned on by the first logic gate, and a second logic gate that turns on the first MOS transistor; The third MOS
A synchronous driver circuit comprising a third logic gate that turns on the fourth MOS transistor after the transistor is turned on.