JP3249381B2 - Synchronous logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock synchronous precharge logic circuit in a CMOS integrated circuit, and more particularly to noise prevention of a precharge logic circuit.

[0002]

FIG. 13 shows a conventional clock synchronous NAN.
3 shows a D circuit. A P-channel MOS transistor (hereinafter referred to as PMOS) Tr11 and N-channel MOS transistors (hereinafter referred to as NMOS) Tr12 and Tr13 are connected in series. The source of the PMOS Tr 11 is connected to the power supply, and the gate receives the clock signal CLK.
Nodes a, which are gate terminals of the NMOS Trs 12 and 13,
Signals A and B synchronized with the clock signal CLK are input to b, and the source of Tr13 is grounded. PMOSTr
The node c to which the NMOS transistor 11 and the NMOS Tr 12 are connected is connected to the input terminal of the inverter.

[0003] P-channel MOS transistor Tr11
Is in the conductive state, that is, during the precharge period, the node c is kept at the H level. When Tr11 is non-conductive, that is, during the sampling period, when both signals A and B are at H level, NMOS Tr12, Tr13
Conducts, and sets node c to L level. Thus, a clock synchronous NAND gate is formed.

[0004]

FIG. 14 is a time chart of the clock synchronous NAND circuit shown in FIG. When the operation is performed such that the input A changes from the L level to the H level and the input B remains at the L level when the transition from the precharge period to the sampling period occurs, the node c is normally at the H level as shown by the dotted line in FIG. Take the action that remains.

However, when the wirings of the signal A and the signal B are laid out close to each other over a long distance, for example,
The signal B is pulled up to the H level in response to the rise of the signal A due to the parasitic capacitance between the wirings of the signals A and B. This is called coupling noise. Further, the node b operates as shown by the solid line in FIG. With this operation, Tr13
Will operate, causing a malfunction such that the node c is lowered to the L level.

FIG. 15 shows a conventional workaround for such a problem. As shown in FIG. 15, a countermeasure is taken by connecting an even number of inverters in series to the gate of the PMOS Tr 11 to delay CLK itself. FIG. 16 shows a time chart when this measure is taken.

However, in this countermeasure method, FIG.
As can be seen from FIG.
A period in which the OS is also in a conductive state may occur. In this period, since a through current flows, there is a problem that power consumption increases. The present invention has been made in view of the above circumstances, and has as its object to provide a synchronous logic circuit that operates normally without malfunction even when coupling or switching noise occurs.

[0008]

A timing control circuit having a signal synchronized with a clock signal as an input and a MOS transistor having an output connected to a gate are provided between a power supply terminal of a logic circuit and a second power supply. Is added so that the source and drain are connected. By generating a signal in which the transistor is turned off during a period in which noise is generated by the timing control circuit, malfunction of the circuit is prevented.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a clock synchronous NAND gate. The same reference numerals are given to the same portions as those in FIG. In the following other embodiments, the same parts as those already described are denoted by the same reference numerals, and description thereof will be omitted. A timing control circuit 15 that receives a signal C synchronized with a clock signal as an input and an NMOS Tr1 whose output is supplied to a gate
4 is added so that the source / drain of Tr14 is connected between Tr13 and GND in the conventional circuit. The timing control circuit uses this NMOS during the period when noise occurs.
Tr14 generates a signal that turns off, thereby preventing malfunction. Specifically, a delay composed of a one-shot pulse generation circuit that receives a clock signal or a signal synchronized with the clock signal or an even-numbered inverter connected in series Circuit.

FIG. 2 shows another embodiment of the present invention. FIG.
In this embodiment, a one-shot pulse generation circuit 16 composed of, for example, a flip-flop circuit is used as a timing control circuit, and a clock signal CLK is used as an input thereof. A one-shot pulse is generated in synchronization with the rise of the clock signal, and the signal is input to Tr14. For this reason, even if Tr13 malfunctions due to noise and conducts, Tr1
Since node 4 is non-conductive, it is possible to prevent node c from being lowered from H level to L level. FIG. 3 shows a time chart in the embodiment of FIG.

FIG. 4 shows an embodiment in which the one-shot pulse generation circuit 16 shown in FIG. 2 is applied to a NOR gate composed of Tr17 and Tr18. FIG. 5 shows a time chart at that time. Also in this embodiment, as in the previous example, even if Tr17 or Tr18 becomes conductive due to noise,
Since 14 is non-conductive, malfunction can be prevented.

FIG. 6 shows another embodiment of the present invention. FIG.
Shows a time chart of the circuit of FIG. FIG.
Is constituted by a delay circuit, and the delay circuit 19 is constituted by connecting four stages of inverters in series. The input terminal of the delay circuit 19 is supplied with the clock signal CLK, and the output terminal is connected to the gate of Tr14. The clock signal delayed by the plurality of inverters is input to the gate of Tr14. During the noise generation period, the clock signal is delayed, and since the node d is at the L level, Tr14 is non-conductive, so that malfunction can be prevented.

FIG. 8 shows a circuit diagram of still another embodiment of the present invention. FIG. 9 shows a time chart of the circuit of FIG. In this embodiment, the signals A,
Delay circuits 19a and 19b each composed of four stages of serially connected inverters having B as an input are used. The gates are connected to the outputs of the delay circuits 19a and 19b, respectively, and Tr20 and Tr21 connected in series are connected between Tr13 and the ground. Thereby, during the noise generation period, Tr2
Since 0 and Tr21 are non-conductive, malfunction can be prevented.

FIGS. 10 and 11 show a circuit diagram and a time chart of still another embodiment of the present invention. In this embodiment,
Two one-shot pulse generation circuits 16a and 16b using signals A and B as inputs are used as timing control circuits. One-shot pulse generation circuit 16a,
The NOR signal of the two outputs of 16b is applied to the transistor Tr1.
Input to gate 4. As a result, the transistor Tr14 is turned off during the noise generation period, so that malfunction can be prevented.

FIG. 12 shows nxm input signals X11 to Xmn.
An embodiment in which the present invention is applied to the AND-AND circuit 22 of FIG. As the timing control circuit 15, FIG.
4 and 6 can be applied, and the same effects as those of the embodiments can be obtained.

[0016]

According to the present invention, a current path of a transistor constituting a logic circuit is forcibly turned off during a time period when noise is generated, so that malfunction of the circuit due to noise can be reliably prevented. Further, the through current is smaller than that of the conventional malfunction prevention circuit, and low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of the circuit shown in FIG. 2;

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a time chart of the circuit shown in FIG. 4;

FIG. 6 is a diagram showing still another embodiment of the present invention.

FIG. 7 is a diagram showing a time chart of the circuit shown in FIG. 6;

FIG. 8 is a diagram showing still another embodiment of the present invention.

9 is a diagram showing a time chart of the circuit shown in FIG.

FIG. 10 is a diagram showing still another embodiment of the present invention.

11 is a diagram showing a time chart of the circuit shown in FIG.

FIG. 12 is a diagram showing still another embodiment of the present invention.

FIG. 13 is a circuit diagram of a conventional dynamic NAND gate.

FIG. 14 is a diagram illustrating a time chart of the circuit illustrated in FIG. 13;

FIG. 15 is a conventional circuit diagram for preventing malfunction due to noise.

16 is a diagram showing a time chart of the circuit shown in FIG.

[Explanation of symbols]

Tr11, Tr12, Tr13, Tr14: MOS transistors; 15: timing control circuit.

Claims (5)

(57) [Claims] A first conductive type MOSFET having a gate supplied with a clock signal, one of a source and a drain connected to a first power supply, an output terminal and a power supply terminal, wherein the output terminal is connected to the first power supply terminal; The power supply terminal is connected to the other of the source or the drain of the one conductivity type MOSFET, the power supply terminal is connected to a second power supply, and a plurality of input signals synchronized with the clock signal are input. A second conductivity type MOSFET logic circuit for outputting to the output terminal as two power supply levels, wherein the first conductivity type MOSFET and the second conductivity type MOSFET are provided.
A connection point with the ET logic circuit is a synchronous logic circuit in which the first power supply is charged while the clock signal is at the first level, and the logical operation result is output while the clock signal is at the second level. One of a source and a drain is the second conductivity type MOSF
The second conductivity type MO connected to the power supply terminal of the ET logic circuit and the other of the source and the drain is connected to the second power supply;
An SFET and an output terminal connected to the gate of the second conductivity type MOSFET, an input signal supplied in synchronization with the clock signal, and a certain period after the input signal transitions from the first level to the second level A control circuit for outputting a signal for bringing the second conductivity type MOSFET into a non-conductive state. 2. The one-shot pulse generation circuit according to claim 1, wherein the control circuit receives the clock signal as input, and generates a signal for turning off the second conductivity type MOSFET for a predetermined period in synchronization with the clock signal. 2. The synchronous logic circuit according to claim 1, wherein: 3. The control circuit receives a plurality of input signals synchronized with the clock signal as inputs, and synchronizes the plurality of input signals with the plurality of input signals for a predetermined period of time.
2. The synchronous logic circuit according to claim 1, wherein the synchronous logic circuit is a one-shot pulse generation circuit that generates a signal for turning off the SFET. 4. The control circuit is an even-numbered inverter connected in series with the clock signal as an input, and these inverters generate a delayed clock signal for turning off the second conductivity type MOSFET. The synchronous logic circuit according to claim 1, wherein 5. The second conductive type MOSFET is a plurality of second conductive type MOSFETs connected in series between the power supply terminal and the second power supply. A plurality of series-connected even-stage inverters each having a terminal connected to the gates of the plurality of second conductivity type MOSFETs and having a plurality of input signals synchronized with the clock signal as inputs, respectively, The second conductivity type MOSFET
2. The synchronous logic circuit according to claim 1, wherein the synchronous logic circuit generates a plurality of delayed input signals to make the non-conductive state.