JPH0256971A - Vertical type double diffused mosfet - Google Patents
Vertical type double diffused mosfetInfo
- Publication number
- JPH0256971A JPH0256971A JP63208860A JP20886088A JPH0256971A JP H0256971 A JPH0256971 A JP H0256971A JP 63208860 A JP63208860 A JP 63208860A JP 20886088 A JP20886088 A JP 20886088A JP H0256971 A JPH0256971 A JP H0256971A
- Authority
- JP
- Japan
- Prior art keywords
- cells
- gate
- sections
- shape
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- POFWRMVFWIJXHP-UHFFFAOYSA-N n-benzyl-9-(oxan-2-yl)purin-6-amine Chemical compound C=1C=CC=CC=1CNC(C=1N=C2)=NC=NC=1N2C1CCCCO1 POFWRMVFWIJXHP-UHFFFAOYSA-N 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はチップ表面のセル内に２重拡散によりウェルと
ソースが形成され、チップ裏面にドレインが形成されて
おり、ウェル表面にチャネルが形成される縦型２重拡散
ＭＯ３ＦＥＴ （ＶＤＭＯＳＦＥＴ）に関するものであ
る。Detailed Description of the Invention (Industrial Application Field) The present invention is characterized in that a well and a source are formed by double diffusion in cells on the surface of a chip, a drain is formed on the back surface of the chip, and a channel is formed on the surface of the well. The present invention relates to a vertical double-diffused MO3FET (VDMOSFET).
縦型２重拡散ＭＯＳＦＥＴは、個別素子として、又は他
のＭＯＳＦＥＴなどとともにＩＣ化されて用いられ１例
えばパワーＭＯＳＦＥＴとして利用される。The vertical double diffusion MOSFET is used as an individual element or integrated into an IC together with other MOSFETs, for example, as a power MOSFET.
（従来の技術）
縦型２重拡＠ＭＯＳＦＥＴではチップに多数のセルが配
置される。セルの平面形状としては、四角形、円形、八
角形などがある。角度をもつセルでは角の部分が辺の部
分に比べてドレイン電流の流れが不均一になり、電界も
高くなる。また、面積効率の点でもやや不利である。ド
レイン電流の均一性や面積効率の点では円形のセルが最
も有利であるが、円形のセルではセル間のゲート酸化膜
領域が広くなり、ゲート容量が大きくなって駆動の際の
充放電時間が長くなる欠点がある。(Prior Art) In a vertical double expansion @MOSFET, a large number of cells are arranged on a chip. The planar shape of the cell may be a square, a circle, an octagon, or the like. In a cell with an angle, the drain current flows more unevenly at the corners than at the sides, and the electric field also becomes higher. It is also somewhat disadvantageous in terms of area efficiency. Circular cells are most advantageous in terms of uniformity of drain current and area efficiency, but in circular cells, the gate oxide film area between cells becomes larger, the gate capacitance becomes larger, and the charging/discharging time during driving becomes shorter. It has the disadvantage of being long.
（発明が解決しようとする課題）
本発明は縦型２重拡散ＭＯＳＦＥＴにおいて、ドレイン
電流を均一に流し、かつ、ゲート容量を減らして駆動の
際の充放電時間を短縮することのできるセル形状及びそ
の配置を提供することを目的とするものである。(Problems to be Solved by the Invention) The present invention provides a cell shape and a cell shape that can uniformly flow drain current and reduce gate capacitance to shorten charging and discharging time during driving in a vertical double diffusion MOSFET. The purpose is to provide that arrangement.
（課題を解決するための手段）
本発明の縦型２重拡散ＭＯＳＦＥＴでは、セルの平面形
状が八角形であり、セル間のゲート部分が格子状につな
がるよう、にセルが配置され、かつ、ゲート部分の格子
点部分にはフィールド酸化膜が形成されている。(Means for Solving the Problems) In the vertical double diffusion MOSFET of the present invention, the planar shape of the cells is octagonal, and the cells are arranged so that the gate portions between the cells are connected in a grid pattern, and A field oxide film is formed at the lattice point portion of the gate portion.
（作用）
八角形は四角形や八角形に比べて角度が大きく、従って
、角の部分でもドレイン電流が均一に流れる。(Function) An octagon has a larger angle than a square or an octagon, so the drain current flows uniformly even at the corners.
ゲート部分の格子点部分はセルから離れた位置にあるた
め、ドレイン電流には大きく影響しない。Since the lattice point portion of the gate portion is located away from the cell, it does not significantly affect the drain current.
ゲート部分の格子点部分に設けられたフィールド酸化膜
はゲート容量を小さくするのに寄与する。The field oxide film provided at the lattice point portion of the gate portion contributes to reducing the gate capacitance.
（実施例）
第１図は一実施例の部分平面図、第２図は第１図のＡ−
Ａ ’線位置での断面図、第３図は第１図のＢ−Ｂ’線
位置での断面図である。(Example) Fig. 1 is a partial plan view of one embodiment, and Fig. 2 is A-A in Fig. 1.
3 is a cross-sectional view taken along line A', and FIG. 3 is a cross-sectional view taken along line B-B' in FIG.
２はＮ１型単結晶シリコン基板であり、その表面にＮ−
型シリコンエピタキシャル暦４が形成されている。セル
５の部分では、第３図に示されるように、エピタキシャ
ル層４の表面に拡散によってＰ型ウェル６、Ｎ４型ソー
ス８及びＰ０領域１０が形成されている。エピタキシャ
ル層４の表面上にはゲート酸化膜１２を介して多結晶シ
リコン層１４が形成されている。基板２はドレインとな
る。2 is an N1 type single crystal silicon substrate, with N-
A type silicon epitaxial layer 4 is formed. In the cell 5 portion, as shown in FIG. 3, a P-type well 6, an N4-type source 8, and a P0 region 10 are formed on the surface of the epitaxial layer 4 by diffusion. A polycrystalline silicon layer 14 is formed on the surface of the epitaxial layer 4 with a gate oxide film 12 interposed therebetween. Substrate 2 becomes a drain.
１６はＰＳＧ膜であり、ＰＳＧ膜１６に設けられたコン
タクトホールを介してソース８に接続されるアルミニウ
ム配線１８が形成されている。ＰＳＧ膜１６はゲートで
ある多結晶シリコンＮ１４とソース８の間の眉間絶縁膜
となる。16 is a PSG film, and an aluminum wiring 18 connected to the source 8 through a contact hole provided in the PSG film 16 is formed. The PSG film 16 becomes an insulating film between the eyebrows between the polycrystalline silicon N14, which is the gate, and the source 8.
セル５は第１図に示されるようにその平面形状は八角形
である。セル５とセル５の間の部分１４はゲート部分で
あり、セル５はゲート部分１４が格子状につながるよう
に配置されている。ゲート部分１４の格子点部分、すな
わち４個のセル５から等間隔にある部分は面積が大きい
ので、その部分全てにゲート酸化膜が存在するとゲート
容量が大きくなる。そのため、ゲート部分１４の格子点
部分には厚さが１００００〜１５０００人程度のフィー
ルド酸化膜２０が形成されている。フィールド酸化膜２
０の平面形状は四角形である。セル５の八角形は正八角
形でもよいが、実施例のセル５はフィールド酸化膜２０
と対向する辺が他の辺より短かくなった八角形である。As shown in FIG. 1, the cell 5 has an octagonal planar shape. A portion 14 between the cells 5 is a gate portion, and the cells 5 are arranged so that the gate portions 14 are connected in a grid pattern. Since the lattice point portions of the gate portion 14, that is, the portions equidistant from the four cells 5, have a large area, the gate capacitance increases if the gate oxide film is present in all of these portions. Therefore, a field oxide film 20 having a thickness of approximately 10,000 to 15,000 layers is formed at the lattice point portion of the gate portion 14. field oxide film 2
The planar shape of 0 is a quadrilateral. Although the octagon of the cell 5 may be a regular octagon, the cell 5 of the embodiment has a field oxide film 20.
It is an octagon with the opposite side shorter than the other sides.
本実施例は従来の円形や四角形などの形状のセルと同じ
プロセスで製造することができる。例えば、エピタキシ
ャル層４上にゲート酸化膜１２を形成し、その上に多結
晶シリコンＮ１４を堆積し、写真製版とエツチングによ
って多結晶シリコン層１４にパターン化を施す。その後
、多結晶シリコン層１４をマスクとして自己整合技術に
よりウェル６とソース８を二重拡散により形成する。ウ
ェル６とソース８の拡散幅の差によってウェル６の表面
にチャネル領域を形成する。This embodiment can be manufactured using the same process as conventional cells having shapes such as circular or rectangular. For example, a gate oxide film 12 is formed on the epitaxial layer 4, polycrystalline silicon N14 is deposited thereon, and the polycrystalline silicon layer 14 is patterned by photolithography and etching. Thereafter, the well 6 and the source 8 are formed by double diffusion using the polycrystalline silicon layer 14 as a mask using a self-alignment technique. A channel region is formed on the surface of the well 6 due to the difference in diffusion width between the well 6 and the source 8.
本実施例において、ゲートである多結晶シリコン層１４
にゲート電圧を印加すると、ウェル６の表面のチャネル
領域にエンハンスメントモードのＮチャネルが形成され
、ドリフト領域であるエピタキシャルｒｆ５４の表面に
デプリーションモードのＮチャネルがそれぞれ形成され
て、矢印のように電子電流がドレインである基板２へ流
れる。In this embodiment, the polycrystalline silicon layer 14 which is the gate
When a gate voltage is applied to , an enhancement mode N channel is formed in the channel region on the surface of the well 6, and a depletion mode N channel is formed in the surface of the epitaxial rf 54, which is the drift region, as shown by the arrow. Electron current flows to the substrate 2, which is the drain.
次に、セル形状が正八角形、第４図に示される正方形、
第５図に示される円形、第６図に示される正八角形につ
いて最大面積効率を算出する。Next, the cell shape is a regular octagon, a square shown in Fig. 4,
The maximum area efficiency is calculated for the circle shown in FIG. 5 and the regular octagon shown in FIG.
まず、セルのウェルの周辺長Ｚ、単位セル面積Ａｃｅｌ
ｌを算出すると第１表のようになり、さらにチャネル面
積Ａｃｈと単位セル面積Ａｃｅｌｌの比を算出すると第
２表のようになる。First, the peripheral length Z of the cell well, the unit cell area Acel
When l is calculated, the results are shown in Table 1, and when the ratio of the channel area Ach to the unit cell area Acell is further calculated, the results are shown in Table 2.
第１表
第２表
ここで、Ｑｃはウェル間隔、Ｑｓはウェルの中心から周
辺までの長さである。また、ｘ＝Ｑｓ／Ｑｃである。Table 1 Table 2 Here, Qc is the well spacing, and Qs is the length from the center to the periphery of the well. Moreover, x=Qs/Qc.
Ａｃｈ／ ＡｃｅｌｌはＸの関数である。そこで、Ａｃ
ｈ／Ａｃｅｌｌの最大値Ａｃｈ／ Ａｃｅｌｌ（ｗａｘ
）と、その時のＸ値ｘ （ｗａｘ）を第３表に示す。Ach/Acell is a function of X. Therefore, Ac
Maximum value of h/Acell Ach/Acell(wax
) and the X value x (wax) at that time are shown in Table 3.
第３表
ｘ＝Ｑｓ／Ｑｅのうち、Ｑｃはオン抵抗の一部であるＲ
ｊｆｅｔ （ウェル６とドリフト層４により形成される
ＪＦＥＴ部分の抵抗）を決定する長さであり、比較のた
めにこれを一定とすると、最もｘ （＋＋ａｘ）の小さ
い形状のセルが全セルを配置したときの総面積で有利と
なる。この結果によれば、セル形状が円形と八角形のも
のが有利であることがわかる。円形の場合は、不要なゲ
ート酸化膜領域が多くなってゲート容量が大きくなる欠
点をもっており、本実施例では第１図に示されるように
四角形のフィールド酸化膜２０を設けることにより、こ
の不要なゲート酸化膜領域を除くことができる。In Table 3, x=Qs/Qe, Qc is R, which is a part of the on-resistance.
jfet (the resistance of the JFET portion formed by the well 6 and the drift layer 4), and if this is kept constant for comparison, the cell with the smallest x (++ax) shape will be the one in which all the cells are arranged. It is advantageous in terms of total area. The results show that circular and octagonal cell shapes are advantageous. In the case of a circular shape, there is a disadvantage that the unnecessary gate oxide film area increases and the gate capacitance increases.In this embodiment, as shown in FIG. 1, by providing a rectangular field oxide film 20, this unnecessary The gate oxide region can be eliminated.
実施例はＮチャネル型に適用した例であるが、Ｐチャネ
ル型に適用することもできる。Although the embodiment is an example in which the present invention is applied to an N-channel type, it can also be applied to a P-channel type.
（発明の効果）
本発明の縦型２重拡散ＭＯＳＦＥＴでは、セルの平面形
状が八角形であり、セル間のゲート部分が格子状につな
がるようにセルが配置されているので、従来の四角形や
八角形の平面形状のセルをもつものに比べて、面積効率
がよくなる。(Effects of the Invention) In the vertical double diffusion MOSFET of the present invention, the planar shape of the cell is octagonal, and the cells are arranged so that the gate portions between the cells are connected in a lattice shape, so that The area efficiency is better than that of cells with an octagonal planar shape.
また、不要なゲート酸化膜領域にフィールド酸化膜を設
けることによって、ゲート駆動効率を上げることができ
る。このフィールド酸化膜は円形のセルの場合にも設け
ることができるが、その場合はフィールド酸化膜の形状
が複雑となる。それに対し、本発明のようにセル形状が
八角形であれ４、このフィールド酸化膜形状を四角形と
することができ、設計が容易である。Further, by providing a field oxide film in an unnecessary gate oxide film region, gate drive efficiency can be increased. This field oxide film can also be provided in the case of a circular cell, but in that case the shape of the field oxide film becomes complicated. On the other hand, even if the cell shape is octagonal as in the present invention, the field oxide film shape can be square, which facilitates the design.
第１図は一実施例を示す部分平面図、第２図は第１図の
Ａ−Ａ ’線位置での断面図、第３図は第１図のＢ−Ｂ
’線位置での断面図である。第４図、第５図及び第６図
はそれぞれ従来のセル形状を示す平面図である。
２・・・・・・シリコン基板、４・・・・・・シリコン
エピタキシャル層、５・・・・・・セル、６・・・・・
・Ｐ型ウェル、８・・・・・・Ｎ＋型ソース、１２・・
・・・・ゲート酸化膜、１４・・・・・・多結晶シリコ
ン層、２０・・・・・・フィールド酸化膜。Fig. 1 is a partial plan view showing one embodiment, Fig. 2 is a sectional view taken along line A-A' in Fig. 1, and Fig. 3 is a sectional view taken along line B-B in Fig. 1.
It is a cross-sectional view at the ' line position. FIG. 4, FIG. 5, and FIG. 6 are plan views showing conventional cell shapes, respectively. 2...Silicon substrate, 4...Silicon epitaxial layer, 5...Cell, 6...
・P-type well, 8...N+ type source, 12...
...Gate oxide film, 14...Polycrystalline silicon layer, 20...Field oxide film.
Claims (1)
ースが形成されており、チップ裏面にドレインが形成さ
れており、前記ウェル表面にチャネルが形成される縦型
２重拡散ＭＯＳＦＥＴにおいて、前記セルの平面形状が
八角形であり、セル間のゲート部分が格子状につながる
ようにセルが配置され、かつ、前記ゲート部分の格子点
部分にはフィールド酸化膜が形成されていることを特徴
とする縦型２重拡散ＭＯＳＦＥＴ。(1) In a vertical double diffusion MOSFET, a well and a source are formed by double diffusion in a cell on the front surface of the chip, a drain is formed on the back surface of the chip, and a channel is formed on the surface of the well. The planar shape of the cells is octagonal, the cells are arranged so that gate portions between the cells are connected in a lattice pattern, and a field oxide film is formed at the lattice point portions of the gate portions. Vertical double diffusion MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63208860A JPH0256971A (en) | 1988-08-22 | 1988-08-22 | Vertical type double diffused mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63208860A JPH0256971A (en) | 1988-08-22 | 1988-08-22 | Vertical type double diffused mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0256971A true JPH0256971A (en) | 1990-02-26 |
Family
ID=16563318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63208860A Pending JPH0256971A (en) | 1988-08-22 | 1988-08-22 | Vertical type double diffused mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0256971A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03128935U (en) * | 1990-04-05 | 1991-12-25 | ||
| JPH07193241A (en) * | 1990-12-21 | 1995-07-28 | Siliconix Inc | Method for controlling defect formed in manufacture of silicon integrated circuit, method for controlling quality of oxide film and formation of defect, and method for forming double-diffusion integrated circuit device cell and integrated circuit mosfet cell |
| JPH08197134A (en) * | 1995-01-24 | 1996-08-06 | Yodogawa Steel Works Ltd | Device for coiling surface treated metallic strip and method thereof |
| US5760454A (en) * | 1995-04-11 | 1998-06-02 | Oki Electric Industry Co., Ltd. | Pattern form of an active region of a MOS type semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149057A (en) * | 1983-02-15 | 1984-08-25 | Nissan Motor Co Ltd | Vertical metal oxide semiconductor transistor |
| JPS59151466A (en) * | 1983-02-17 | 1984-08-29 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor field-effect transistor |
-
1988
- 1988-08-22 JP JP63208860A patent/JPH0256971A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59149057A (en) * | 1983-02-15 | 1984-08-25 | Nissan Motor Co Ltd | Vertical metal oxide semiconductor transistor |
| JPS59151466A (en) * | 1983-02-17 | 1984-08-29 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor field-effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03128935U (en) * | 1990-04-05 | 1991-12-25 | ||
| JPH07193241A (en) * | 1990-12-21 | 1995-07-28 | Siliconix Inc | Method for controlling defect formed in manufacture of silicon integrated circuit, method for controlling quality of oxide film and formation of defect, and method for forming double-diffusion integrated circuit device cell and integrated circuit mosfet cell |
| JPH08197134A (en) * | 1995-01-24 | 1996-08-06 | Yodogawa Steel Works Ltd | Device for coiling surface treated metallic strip and method thereof |
| US5760454A (en) * | 1995-04-11 | 1998-06-02 | Oki Electric Industry Co., Ltd. | Pattern form of an active region of a MOS type semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4860821B2 (en) | Semiconductor device manufacturing method | |
| US11270993B2 (en) | MOSFET device of silicon carbide having an integrated diode and manufacturing process thereof | |
| US7317213B2 (en) | Semiconductor device having super junction structure and method for manufacturing the same | |
| US20050263853A1 (en) | Insulated gate semiconductor device | |
| US6264167B1 (en) | Semiconductor device | |
| GB2137811A (en) | High power mosfet with direct connection from connection pads to underlying silicon | |
| US6037631A (en) | Semiconductor component with a high-voltage endurance edge structure | |
| US20200259005A1 (en) | Semiconductor device and manufacturing method therefor | |
| JP2007042892A (en) | Trenched misfet | |
| US6955970B1 (en) | Process for manufacturing a low voltage MOSFET power device having a minimum figure of merit | |
| KR910004318B1 (en) | Vertical type dmos transistors cell | |
| JP3525637B2 (en) | Semiconductor device | |
| JPH0256971A (en) | Vertical type double diffused mosfet | |
| JPH06104438A (en) | Film transistor | |
| US20040155258A1 (en) | Semiconductor device | |
| JPS6180859A (en) | Power mosfet | |
| JPH01238173A (en) | Power mosfet | |
| JP3855386B2 (en) | Semiconductor device | |
| JP2723868B2 (en) | Semiconductor device | |
| JPH02178975A (en) | Mos type semiconductor device | |
| JPH04188877A (en) | Power mosfet of high breakdown strength | |
| US10957791B2 (en) | Power device with low gate charge and low figure of merit | |
| JP2004031386A (en) | Semiconductor device | |
| JPH01292862A (en) | Semiconductor device | |
| US7482285B2 (en) | Dual epitaxial layer for high voltage vertical conduction power MOSFET devices |