JP3525637B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3525637B2 JP3525637B2 JP21162596A JP21162596A JP3525637B2 JP 3525637 B2 JP3525637 B2 JP 3525637B2 JP 21162596 A JP21162596 A JP 21162596A JP 21162596 A JP21162596 A JP 21162596A JP 3525637 B2 JP3525637 B2 JP 3525637B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- element isolation
- diffusion region
- source electrode
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 42
- 238000002955 isolation Methods 0.000 claims description 61
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 238000009792 diffusion process Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 46
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 46
- 230000015556 catabolic process Effects 0.000 description 18
- 230000002093 peripheral effect Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、電力用半導体素
子として用いられる半導体装置、すなわち縦型ＭＯＳＦ
ＥＴ（Ｍetal Ｏxide Ｓemiconductor Ｆield Ｅff
ect Ｔransistor）やＩＧＢＴ（Ｉnsulated Ｇate Ｂi
polar Ｔransistor ）等に係り、その用途としては、
例えば電力用半導体素子を組み込んだＭＯＳＩＣ等があ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as a power semiconductor element, that is, a vertical MOSF.
ET (Metal Oxide Semiconductor Field Eff)
ect Transistor) and IGBT (Insulated Gate Bi)
Polar Transistor) etc.
For example, there is a MOSIC or the like incorporating a power semiconductor element.
【０００２】[0002]
【従来の技術】縦型パワーＭＯＳＦＥＴは、周波数特性
が優れ、スイッチング速度が速く、かつ低電力で駆動で
きる等多くの特長を有することから、近年多くの産業分
野で使用されている。例えば、日経マグロウヒル社発行
“日経エレクトロニクス”の１９８６年５月１９日号，
ｐｐ．１６５−１８８には、パワーＭＯＳＦＥＴの開発
の焦点が低耐圧品および高耐圧品に移行している旨が記
載されている。さらに、この文献には、耐圧１００Ｖ以
下のパワーＭＯＳＦＥＴチップのオン抵抗は、１０ｍΩ
レベルまで低くなってきていることが記載されており、
この理由として、パワーＭＯＳＦＥＴの製造にＬＳＩの
微細加工を利用したり、そのセルの形状を工夫したりす
ることにより、面積当たりのチャネル幅が大きくとれる
ようになったことにある旨が述べられている。又、この
文献には主流であるＤＭＯＳ型（二重拡散型）セルを使
用した縦型パワーＭＯＳＦＥＴを中心に述べられてい
る。その理由は、ＤＭＯＳ型はチャネル部分にシリコン
ウエハの平坦な主表面をそのまま使用することを特長と
するプレーナプロセスにより作製されるため、歩留まり
が良くコストが安いという製造上の利点があるからであ
る。2. Description of the Related Art Vertical power MOSFETs have been used in many industrial fields in recent years because they have many characteristics such as excellent frequency characteristics, fast switching speed, and low power consumption. For example, the May 19, 1986 issue of “Nikkei Electronics” published by Nikkei McGraw-Hill,
pp. 165-188 describes that the focus of development of power MOSFETs has shifted to low withstand voltage products and high withstand voltage products. Further, in this document, the on-resistance of a power MOSFET chip having a withstand voltage of 100 V or less is 10 mΩ.
It is described that it is getting lower to the level,
It is stated that the reason for this is that the channel width per area can be increased by utilizing the microfabrication of the LSI for manufacturing the power MOSFET or devising the shape of the cell. There is. Further, this document mainly describes a vertical power MOSFET using a DMOS type (double diffusion type) cell which is the mainstream. The reason is that the DMOS type is manufactured by a planar process which is characterized in that the flat main surface of a silicon wafer is used as it is for the channel portion, and therefore has a manufacturing advantage that the yield is high and the cost is low. .
【０００３】一方、縦型パワーＭＯＳＦＥＴの普及に伴
って低損失化、低コスト化がさらに求められているが、
微細加工やセルの形状の工夫によるオン抵抗低減は限界
にきている。例えば、特開昭６３−２６６８８２号公報
によると、ＤＭＯＳ型においては微細加工によりユニッ
トセルの寸法を小さくしてもオン抵抗がそれ以上減少し
ない極小点があり、その主原因がオン抵抗の成分を成す
ＪＦＥＴ抵抗の増加であることが分かっている。ＤＭＯ
Ｓ型において、特開平２−８６１３６号公報に示されて
いるように、現在の微細加工技術の下ではオン抵抗が極
小点をとるユニットセルの寸法は１５μｍ付近である。On the other hand, with the spread of vertical power MOSFETs, there is a demand for further reduction in loss and cost.
Reducing the on-resistance by microfabrication and devising the cell shape has reached its limit. For example, according to Japanese Patent Laid-Open No. 63-266882, the DMOS type has a minimum point at which the on-resistance does not decrease further even if the size of the unit cell is reduced by microfabrication, and the main cause is the on-resistance component. It has been found to be an increase in JFET resistance. DMO
In the S type, as disclosed in Japanese Patent Laid-Open No. 2-86136, under the current fine processing technology, the size of the unit cell where the on-resistance has a minimum point is around 15 μm.
【０００４】この限界を突破するために種々の構造が提
案されている。それらに共通した特徴は素子表面に溝を
形成し、その溝の側面にチャネル部を形成した構造であ
り、この構造により前述のＪＦＥＴ抵抗を大幅に減少さ
せることができる。さらに、この溝の側面にチャネル部
を形成した構造においては、ユニットセル寸法を小さく
してもＪＦＥＴ抵抗の増大は無視することができるた
め、特開昭６３−２６６８８２号公報に記載されたよう
なユニットセル寸法の縮小に対してオン抵抗が極小点を
とるという限界が無く、１５μｍを切って微細加工の限
界まで小さくすることができる。Various structures have been proposed to overcome this limitation. A feature common to them is a structure in which a groove is formed on the device surface and a channel portion is formed on the side surface of the groove. This structure can greatly reduce the JFET resistance. Further, in the structure in which the channel portion is formed on the side surface of the groove, the increase in JFET resistance can be ignored even if the unit cell size is reduced, and therefore, as described in JP-A-63-266882. There is no limit that the on-resistance takes a minimum point with respect to the reduction of the unit cell size, and it can be reduced to 15 μm or less to the limit of fine processing.
【０００５】このように、溝の側面にチャネル部を形成
する構造の従来の製造方法として例えば特開昭６１−１
９９６６６号公報に開示されているようにＲＩＥ（反応
性イオンエッチング）で溝を形成し、その溝の側面にチ
ャネル部を形成した、いわゆるトレンチ構造のものがあ
る。ここで、ＲＩＥはプロセスの制御性の優れた物理的
なエッチングである。すなわちＲＩＥは、ガス雰囲気中
に置かれた半導体基板の上下に電極を配置して前記電極
間に高周波電力を印加すると、ガスが電子とイオンとに
電離する。この電極間での電子とイオンの移動度の大き
な違いによって半導体基板上部に陰極降下が生じる。そ
してこの陰極降下によって電界を生じさせ、この電界に
よって前記イオンを半導体基板方向に加速させ、被エッ
チング面に物理的に衝突させてそのエネルギーで半導体
基板をエッチングするものである。そして、ＲＩＥは電
離したガスを加速させるため、前記半導体基板上に絶対
値にして１０Ｖ〜５００Ｖ程度の陰極降下が発生するよ
うに前記電極間に高周波電力が印加される。ＲＩＥにお
いては電離したガスをある一定方向に加速させるため、
非常に優れた異方性を有しサイドエッチが起こりにくい
という特徴がある。しかしながら、ＲＩＥにおいては、
物理的に電離されたガスを半導体基板に衝突させるた
め、エッチングされた面に格子欠陥が必然的に発生し、
移動度が下がり結果としてオン抵抗が増加してしまうと
いう問題がある。As a conventional manufacturing method of the structure in which the channel portion is formed on the side surface of the groove as described above, for example, Japanese Patent Laid-Open No. 61-1
As disclosed in Japanese Patent No. 99666, there is a so-called trench structure in which a groove is formed by RIE (reactive ion etching) and a channel portion is formed on the side surface of the groove. Here, RIE is physical etching with excellent process controllability. That is, in RIE, when electrodes are arranged above and below a semiconductor substrate placed in a gas atmosphere and high-frequency power is applied between the electrodes, the gas is ionized into electrons and ions. Due to the large difference in the mobility of electrons and ions between the electrodes, a cathode drop occurs in the upper part of the semiconductor substrate. Then, an electric field is generated by this cathode fall, and the ions are accelerated toward the semiconductor substrate by this electric field to physically collide with the surface to be etched and the semiconductor substrate is etched by the energy. Since RIE accelerates the ionized gas, high frequency power is applied between the electrodes so that a cathode fall of about 10 V to 500 V in absolute value occurs on the semiconductor substrate. In RIE, to accelerate the ionized gas in a certain direction,
It has a very excellent anisotropy, and side etching is unlikely to occur. However, in RIE,
Since the physically ionized gas collides with the semiconductor substrate, lattice defects inevitably occur on the etched surface,
There is a problem that the mobility decreases and as a result, the on-resistance increases.
【０００６】ここで格子欠陥が発生いくい半導体装置と
して、例えば国際公開ＷＯ９３／０３５０２号や特開昭
６２−１２１６７号公報に開示されているようにウエッ
トエッチングを用いて製造した半導体装置がある。これ
らの形状は、トレンチ形状に対してバスタブ形状といわ
れる。As a semiconductor device in which lattice defects are generated, there is a semiconductor device manufactured by using wet etching as disclosed in International Publication WO93 / 03502 and Japanese Patent Laid-Open No. 62-12167. These shapes are called bathtub shapes, as opposed to trench shapes.
【０００７】[0007]
【発明が解決しようとする課題】このように、ＪＦＥＴ
抵抗をなくした構造である溝を形成したＤＭＯＳＦＥＴ
では、従来のプレーナＤＭＯＳＦＥＴに対して、１／２
以下に特性オン抵抗を低減することができる。従って、
溝を形成したＤＭＯＳＦＥＴによりチップを作製した場
合、オン抵抗を同一にするには、チップ面積は約１／２
にでき、チップサイズを小さくすることができる。しか
しながら、チップ面積のうちセル面積は１／２以下にな
るものの、セル形成領域の周囲の領域（ゲート電極引出
線領域や耐圧構造領域）の面積は変わらない。従って、
特性オン抵抗が低減するほど、チップ面積を小さくでき
るが、セル形成領域の周囲の領域がチップの面積に占め
る割合が大きくなってくる。このため、セル形成領域の
周囲の領域も面積を低減することが重要な課題になって
くる。As described above, the JFET is
DMOSFET having a groove having a structure without resistance
Then, compared with the conventional planar DMOSFET,
The characteristic on-resistance can be reduced as follows. Therefore,
When a chip is made of a DMOSFET having a groove, the chip area is about 1/2 for the same ON resistance.
Therefore, the chip size can be reduced. However, although the cell area of the chip area is ½ or less, the area of the area around the cell formation area (gate electrode lead-out line area or breakdown voltage structure area) does not change. Therefore,
As the characteristic on-resistance decreases, the chip area can be reduced, but the ratio of the area around the cell formation area to the chip area increases. Therefore, it is important to reduce the area of the area around the cell formation area.
【０００８】具体例を図９，１０を用いて説明する。チ
ップにおけるセル形成領域Ｚ１の回りには素子分離領域
Ｚ２が形成され、素子分離領域Ｚ２には内側のゲート電
極引出し線領域Ｚ３と外側の耐圧構造領域Ｚ４とを備え
ている。ゲート電極引出線領域Ｚ３にはゲート電極用ア
ルミ配線（引出し線）５１が延設され、アルミ配線５１
がポリシリコンゲート電極５２と接続され、アルミ配線
５１によりゲート信号が時間遅れなく伝搬する。即ち、
配線材としてのポリシリコンは金属（アルミ）に比べて
抵抗が２桁程度高く、このため、アルミ配線５１を周囲
に配置することによってゲート信号の伝搬を速くしてい
る。又、素子分離領域Ｚ２にはディープｐウェル領域５
３が形成され、ディープｐウェル領域５３は耐圧構造領
域Ｚ４に形成されたアルミ配線５４と接続されている。A specific example will be described with reference to FIGS. An element isolation region Z2 is formed around the cell formation region Z1 in the chip, and the element isolation region Z2 includes an inner gate electrode lead-out line region Z3 and an outer breakdown voltage structure region Z4. Aluminum wiring (leading wire) 51 for the gate electrode is extended in the gate electrode leading wire area Z3.
Is connected to the polysilicon gate electrode 52, and the aluminum wiring 51 allows the gate signal to propagate without delay. That is,
Polysilicon as a wiring material has a resistance of about two digits higher than that of metal (aluminum). Therefore, by arranging the aluminum wiring 51 around, the propagation of the gate signal is accelerated. Further, the deep p-well region 5 is formed in the element isolation region Z2.
3 is formed, and the deep p-well region 53 is connected to the aluminum wiring 54 formed in the breakdown voltage structure region Z4.
【０００９】又、アルミ配線５４はソース電極５５と接
続されるとともに、ディープｐウェル領域５３から距離
Ｌ１０だけ外側に張り出しており、アルミ配線５４がフ
ィールドプレートとして機能している。これにより１０
０Ｖ程度のドレイン・ソース間耐圧が得られる構造とな
っている。ところが、素子分離領域Ｚ２において、ソー
ス電極５５と接続されたアルミ配線（フィールドプレー
ト）５４とゲート電極用アルミ配線５１が個別に設けら
れているため、素子分離領域Ｚ２が幅２００μｍ程度と
大きくなっていた。The aluminum wiring 54 is connected to the source electrode 55 and extends outward from the deep p well region 53 by a distance L10, and the aluminum wiring 54 functions as a field plate. This gives 10
It has a structure capable of obtaining a drain-source breakdown voltage of about 0V. However, since the aluminum wiring (field plate) 54 connected to the source electrode 55 and the aluminum wiring 51 for the gate electrode are individually provided in the element isolation region Z2, the element isolation region Z2 has a large width of about 200 μm. It was
【００１０】そこで、この発明の目的は、セル形成領域
の周辺領域を小面積化してチップ面積を小さくすること
ができる半導体装置を提供することにある。Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the area of the peripheral region of the cell forming region to reduce the chip area.
【００１１】[0011]
【課題を解決するための手段】請求項１に記載の発明
は、セル形成領域の周囲における素子分離用不純物拡散
領域の上に酸化膜を介してＭＯＳＦＥＴのゲート電極の
金属配線を素子分離用不純物拡散領域よりも外側に張り
出した状態で延設し、ゲート電極の金属配線をフィール
ドプレートとして用いたことを特徴としている。よっ
て、セル形成領域の周囲において、図１０に示したソー
ス電極と接続されたアルミ配線（フィールドプレート構
成体）５４とアルミ配線５１とを個別に備えた場合に比
べて、セル形成領域の周囲の素子分離領域の幅を狭くで
き、セル形成領域の周辺領域を小面積化してチップ面積
を小さくすることができる。SUMMARY OF THE INVENTION The first aspect of the present invention, the impurity element separating metal wiring of the gate electrode of the MOSFET via an oxide film on the element isolation impurity diffusion regions at the periphery of the cell forming region It is characterized in that the metal wiring of the gate electrode is used as a field plate by extending in a state of overhanging from the diffusion region. Therefore, as compared with the case where the aluminum wiring (field plate structure) 54 and the aluminum wiring 51 connected to the source electrode shown in FIG. The width of the element isolation region can be narrowed, and the peripheral area of the cell formation region can be reduced in area to reduce the chip area.
【００１２】また、ソース電極をセル形成領域の角部か
ら外方に延設し、当該角部外方にてソース電極延設部と
素子分離用不純物拡散領域とを電気的に接続すると、角
部以外でソース電極延設部と素子分離用不純物拡散領域
とを接続する場合に比べ無駄なコンタクトスペースが無
くなる。 Further, to extend outwardly of the source electrode from the corner of the cell forming region, when electrically connecting the source electrode extension portion and the element isolation impurity diffusion regions at the corner outer sides, corners A wasteful contact space is eliminated as compared with the case where the source electrode extension portion and the element isolation impurity diffusion region are connected to each other.
【００１３】請求項２に記載の発明は、セル形成領域の
周囲における素子分離用不純物拡散領域の上にゲート酸
化膜の厚さより厚く形成された酸化膜を介してＭＯＳＦ
ＥＴのポリシリコンゲート電極を素子分離用不純物拡散
領域よりも外側に張り出した状態で延設し、ポリシリコ
ンゲート電極延設部をフィールドプレートとして用いた
ことを特徴としている。よって、セル形成領域の周囲に
おいて、図１０に示したソース電極と接続されたアルミ
配線（フィールドプレート構成体）５４とアルミ配線５
１とを備えた場合に比べてセル形成領域の周囲の素子分
離領域の幅を狭くでき、セル形成領域の周辺領域を小面
積化してチップ面積を小さくすることができる。ここ
で、請求項３に記載のように、ソース電極をセル形成領
域の角部から外方に延設し、当該角部外方にてソース電
極延設部と素子分離用不純物拡散領域とを電気的に接続
すると、角部以外でソース電極延設部と素子分離用不純
物拡散領域とを接続する場合に比べ無駄なコンタクトス
ペースが無くなる。 According to a second aspect of the present invention, a gate oxide is formed on the element isolation impurity diffusion region around the cell formation region.
MOSF through the oxide film formed thicker than the oxide film
It is characterized in that the polysilicon gate electrode of ET is extended in a state of protruding outside the impurity diffusion region for element isolation, and the extension portion of the polysilicon gate electrode is used as a field plate. Therefore, around the cell formation region, the aluminum wiring (field plate structure) 54 and the aluminum wiring 5 connected to the source electrode shown in FIG.
1, the width of the element isolation region around the cell formation region can be narrowed, and the peripheral region of the cell formation region can be reduced in area to reduce the chip area. here
Then, as described in claim 3, the source electrode is formed in the cell formation region.
Extend from the corner of the area to the outside and source the source outside the corner.
Electrical connection between the pole extension and the element isolation impurity diffusion region
Then, the source electrode extension part and the element isolation impurity except the corner part
Useless contact contacts compared to connecting to the object diffusion area
I lose my pace.
【００１４】請求項１〜３の半導体装置において、ＭＯ
ＳＦＥＴのユニットセルの平面形状を四角形とすると、
セル形成領域Ｚ１の形状を矩形にでき、セル形成領域Ｚ
１の外周部（境界部）を直線化できる。そのためＭＯＳ
ＦＥＴのユニットセルの平面形状を四角形以外の形状と
した場合に比べ、素子分離領域の面積を小さくできる。In the semiconductor device according to any one of claims 1 to 3, MO
If the planar shape of the SFET unit cell is a quadrangle,
The shape of the cell formation region Z1 can be made rectangular and the cell formation region Z1
The outer peripheral portion (boundary portion) of 1 can be linearized. Therefore MOS
The area of the element isolation region can be made smaller than in the case where the planar shape of the unit cell of the FET is a shape other than a quadrangle.
【００１５】[0015]
（第１の実施の形態）以下、この発明の第１の実施の形
態を図面に従って説明する。(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
【００１６】図１は、本実施の形態の縦型パワーＭＯＳ
ＦＥＴ（チップ）の平面図である。チップの中央部には
セル形成領域Ｚ１が形成され、セル形成領域Ｚ１にユニ
ットセルが縦横に規則正しく多数配置されている。ユニ
ットセルは、その平面形状が略正方形であり、ピッチ
（寸法）Ｐが１０〜１６μｍ程度である。セル形成領域
Ｚ１はその平面形状が長方形状をなしている。FIG. 1 shows a vertical power MOS of this embodiment.
It is a top view of FET (chip). A cell formation region Z1 is formed in the center of the chip, and a large number of unit cells are regularly arranged in the cell formation region Z1 in the vertical and horizontal directions. The unit cell has a substantially square planar shape and a pitch (dimension) P of about 10 to 16 μm. The cell formation region Z1 has a rectangular planar shape.
【００１７】図２には、図１でのチップ角部の拡大図を
示す。図３には図２のＡ−Ａ断面図を示し、図４には図
２のＢ−Ｂ断面図を示し、図５には図２のＣ−Ｃ断面図
を示す。FIG. 2 shows an enlarged view of the corner portion of the chip in FIG. 2 is shown in FIG. 3, FIG. 4 is a sectional view taken along the line BB of FIG. 2, and FIG. 5 is a sectional view taken along the line CC of FIG.
【００１８】図３〜図５に示すように、チップ（半導体
基板）１において、ｎ+ 型シリコン基板２の上にはｎ-
型エピタキシャル層３が形成されている。ｎ+ 型シリコ
ン基板２は不純物濃度が２×１０19ｃｍ-3程度で厚さが
１００〜４００μｍである。ｎ- 型エピタキシャル層３
は不純物濃度が１０16ｃｍ-3程度で厚さが７μｍ前後で
ある。半導体基板１のセル形成領域Ｚ１の周辺部には素
子分離領域（外周部）Ｚ２が形成され、素子分離領域
（外周部）Ｚ２はその幅が１５０μｍ程度である。図１
０に示した従来の構造では素子分離領域Ｚ２の幅が２０
０μｍ程度であったが、本例では１５０μｍ程度に短く
なっている。セル形成領域Ｚ１を拡大したもの（図３の
Ｘ部拡大図）を図６に示す。この図６を用いてセル形成
領域Ｚ１を説明する。As shown in FIGS. 3 to 5, in the chip (semiconductor substrate) 1, n − on the n + type silicon substrate 2.
The type epitaxial layer 3 is formed. The n + type silicon substrate 2 has an impurity concentration of about 2 × 10 19 cm −3 and a thickness of 100 to 400 μm. n − type epitaxial layer 3
Has an impurity concentration of about 10 16 cm −3 and a thickness of about 7 μm. An element isolation region (outer peripheral portion) Z2 is formed around the cell formation region Z1 of the semiconductor substrate 1, and the element isolation region (outer peripheral portion) Z2 has a width of about 150 μm. Figure 1
In the conventional structure shown in FIG. 0, the width of the element isolation region Z2 is 20
It was about 0 μm, but in this example, it is shortened to about 150 μm. FIG. 6 shows an enlarged view of the cell formation region Z1 (enlarged view of X part in FIG. 3). The cell formation region Z1 will be described with reference to FIG.
【００１９】ｎ- 型エピタキシャル層３の表層部におい
ては、深いｐ型のベース領域４および浅いｎ+ 型のソー
ス領域５が形成されている。半導体基板１における上面
（表面）には溝６が形成され、この溝６の側面６ａは斜
状（テーパ状）となっている。又、溝６の底面６ｂはｎ
- 型エピタキシャル層３の配置領域にあり、溝６の側面
６ａにベース領域４およびソース領域５が形成されてい
る。このように溝６の側面６ａにおける上部にソース領
域５が形成されるとともにソース領域５の下にベース領
域４が形成されている。ｐ型ベース領域４は深さが１μ
ｍ程度であり、ｎ+ 型ソース領域５は深さが０．５μｍ
程度である。そして、溝６の側面６ａに０．５μｍ程度
のチャネルが設定される。ベース領域４とソース領域５
とは二重拡散により形成されたものである。In the surface layer portion of the n − type epitaxial layer 3, a deep p type base region 4 and a shallow n + type source region 5 are formed. A groove 6 is formed on the upper surface (front surface) of the semiconductor substrate 1, and a side surface 6 a of the groove 6 is oblique (tapered). The bottom surface 6b of the groove 6 is n
The base region 4 and the source region 5 are formed on the side surface 6 a of the groove 6 in the arrangement region of the − type epitaxial layer 3. Thus, the source region 5 is formed on the upper portion of the side surface 6 a of the groove 6 and the base region 4 is formed under the source region 5. The p-type base region 4 has a depth of 1 μm.
and the depth of the n + type source region 5 is 0.5 μm.
It is a degree. Then, a channel of about 0.5 μm is set on the side surface 6 a of the groove 6. Base region 4 and source region 5
Is formed by double diffusion.
【００２０】さらに、溝６の底面６ｂと側面６ａとの角
部は丸みを有し、さらに、溝６の側面６ａと半導体基板
１の表面との角部も丸みを有している。この溝形状は、
ＬＯＣＯＳ酸化膜にて溝６を形成することにより得られ
るものである。この溝６をコンケイブ（concave ）と呼
び、本実施の形態のＭＯＳＦＥＴはコンケイブ型ＭＯＳ
ＦＥＴとなっている。この溝６によりオン抵抗の低減が
図られる。Further, the corners between the bottom surface 6b and the side surface 6a of the groove 6 are rounded, and the corners between the side surface 6a of the groove 6 and the surface of the semiconductor substrate 1 are also rounded. This groove shape is
It is obtained by forming the groove 6 with a LOCOS oxide film. The groove 6 is called a concave, and the MOSFET of this embodiment is a concave MOS.
It is a FET. The groove 6 reduces the on-resistance.
【００２１】溝６の内壁面、および溝６の周辺部におけ
るソース領域５の表面には、ゲート絶縁膜としての薄い
シリコン酸化膜７が形成されている。溝６の内部および
溝６の周辺部におけるシリコン酸化膜７の上にはポリシ
リコンゲート電極８が配置されている。このように、溝
６の側面６ａと半導体基板１の表面との角部に対向して
ゲート絶縁膜としてのシリコン酸化膜７を介してポリシ
リコンゲート電極８が延設されている。溝６の内壁のシ
リコン酸化膜（ゲート酸化膜）７は厚さが４０〜６０ｎ
ｍ程度であり、ポリシリコンゲート電極８の厚さは４０
０ｎｍ程度である。A thin silicon oxide film 7 as a gate insulating film is formed on the inner wall surface of the trench 6 and the surface of the source region 5 in the peripheral portion of the trench 6. A polysilicon gate electrode 8 is arranged on the silicon oxide film 7 in the trench 6 and in the peripheral portion of the trench 6. In this way, the polysilicon gate electrode 8 is extended to face the corner between the side surface 6a of the groove 6 and the surface of the semiconductor substrate 1 with the silicon oxide film 7 serving as the gate insulating film interposed therebetween. The silicon oxide film (gate oxide film) 7 on the inner wall of the groove 6 has a thickness of 40 to 60 n.
and the thickness of the polysilicon gate electrode 8 is 40
It is about 0 nm.
【００２２】ｎ- 型エピタキシャル層４におけるｐ型ベ
ース領域４の中央部には周囲よりも深いｐ型ウェル領域
（ディープｐウェル領域）９が形成されている。このｐ
型ウェル領域９によりドレイン・ソース間に高電圧が印
加されたときに、ｐ型ベース領域４の底面の中央部でブ
レークダウンが起こるようになっている。A p-type well region (deep p-well region) 9 deeper than the surroundings is formed in the central portion of the p-type base region 4 in the n − type epitaxial layer 4. This p
When a high voltage is applied between the drain and the source by the mold well region 9, breakdown occurs in the central portion of the bottom surface of the p-type base region 4.
【００２３】さらに、ポリシリコンゲート電極８の上に
はＢＰＳＧ等の層間絶縁膜１０が配置されている。層間
絶縁膜１０は厚さが１μｍ程度である。層間絶縁膜１０
の上にはアルミ等よりなるソース電極（エミッタ電極、
カソード電極）１１が配置され、ソース電極１１はコン
タクトホール（開口部）１２を通してソース領域５およ
びベース領域４と接している。Further, an interlayer insulating film 10 such as BPSG is arranged on the polysilicon gate electrode 8. The interlayer insulating film 10 has a thickness of about 1 μm. Interlayer insulating film 10
The source electrode (emitter electrode, made of aluminum, etc.
A cathode electrode 11 is arranged, and the source electrode 11 is in contact with the source region 5 and the base region 4 through a contact hole (opening) 12.
【００２４】又、半導体基板１の裏面にはドレイン電極
（コレクタ電極、アノード電極）１３が配置されてい
る。図３，４，５に示すように、素子分離領域Ｚ２にお
いて、半導体基板１の表面に厚さ１μｍ程度のＬＯＣＯ
Ｓ酸化膜（フィールド酸化膜）１４が形成されている。
ＬＯＣＯＳ酸化膜１４の上には、ポリシリコンゲート電
極８から延びるポリシリコンゲート電極延設部１５が配
置されている。ポリシリコンゲート電極延設部１５の上
を含むＬＯＣＯＳ酸化膜１４の上にはシリコン酸化膜１
６が配置されている。このシリコン酸化膜１６の上には
金属配線としてのアルミ配線１７が配置され、アルミ配
線１７は図２に示すように素子分離領域Ｚ２の角部以外
の箇所において延設されている。A drain electrode (collector electrode, anode electrode) 13 is arranged on the back surface of the semiconductor substrate 1. As shown in FIGS. 3, 4 and 5, in the element isolation region Z2, a LOCO having a thickness of about 1 μm is formed on the surface of the semiconductor substrate 1.
An S oxide film (field oxide film) 14 is formed.
A polysilicon gate electrode extension 15 extending from the polysilicon gate electrode 8 is arranged on the LOCOS oxide film 14. The silicon oxide film 1 is formed on the LOCOS oxide film 14 including the polysilicon gate electrode extension portion 15.
6 are arranged. Aluminum wirings 17 as metal wirings are arranged on the silicon oxide film 16, and the aluminum wirings 17 are extended at portions other than the corners of the element isolation region Z2 as shown in FIG.
【００２５】図３に示すように、ポリシリコンゲート電
極延設部１５はコンタクトホール（開口部）１８を通し
てアルミ配線１７と接続されている。アルミ配線１７は
図１に示すように、ゲートパッド２３と接続されてい
る。As shown in FIG. 3, the polysilicon gate electrode extension 15 is connected to the aluminum wiring 17 through a contact hole (opening) 18. The aluminum wiring 17 is connected to the gate pad 23 as shown in FIG.
【００２６】又、図３，４，５に示すように、素子分離
領域Ｚ２において、ｎ- 型エピタキシャル層３には素子
分離用不純物拡散領域としてのディープｐウェル領域１
９が素子分離領域Ｚ２の全域（全周）にわたり延設され
ている。ディープｐウェル領域１９はセル形成領域Ｚ１
のｐ型ウェル領域９と同時に形成される。図２，５に示
すように、シリコン酸化膜１６の上においてソース電極
１１に対しセル形成領域Ｚ１の角部から外方に向かって
アルミ２１が延設され、素子分離領域Ｚ２の角部におい
てコンタクトホール（開口部）２０を通してソース電極
延設部２１とディープｐウェル領域１９とが接続されて
いる。図２に示すように、アルミ配線（ゲート電極引出
し線）１７とソース電極延設部２１とは間隔４０をおい
て離間しており、両者は絶縁されている。Further, as shown in FIGS. 3, 4 and 5, in the element isolation region Z2, the n − type epitaxial layer 3 has a deep p well region 1 as an element isolation impurity diffusion region.
9 extends over the entire area (entire circumference) of the element isolation region Z2. The deep p-well region 19 is the cell formation region Z1.
And the p-type well region 9 are formed at the same time. As shown in FIGS. 2 and 5, aluminum 21 extends outward from the corner of the cell formation region Z1 with respect to the source electrode 11 on the silicon oxide film 16, and contacts at the corner of the element isolation region Z2. The source electrode extension 21 and the deep p-well region 19 are connected through a hole (opening) 20. As shown in FIG. 2, the aluminum wiring (gate electrode lead-out line) 17 and the source electrode extension portion 21 are separated by a gap 40, and both are insulated.
【００２７】さらに、図３，４，５に示すように、ソー
ス電極１１、ソース電極延設部２１およびアルミ配線１
７の上にはパッシベーション膜２２が配置されている。
又、図２，３に示すように、四角形をなす素子分離領域
Ｚ２の辺の部分においては、アルミ配線１７の外側端が
ディープｐウェル領域１９の外周端から距離Ｌ１だけ外
側に位置しており、アルミ配線１７がフィールドプレー
トとして機能している。Further, as shown in FIGS. 3, 4 and 5, the source electrode 11, the source electrode extension portion 21 and the aluminum wiring 1 are provided.
A passivation film 22 is arranged on the surface 7.
Further, as shown in FIGS. 2 and 3, in the side portion of the element isolation region Z2 having a quadrangle, the outer end of the aluminum wiring 17 is located outside the outer peripheral end of the deep p-well region 19 by a distance L1. The aluminum wiring 17 functions as a field plate.
【００２８】つまり、パワーＭＯＳＦＥＴのドレイン・
ソース間の耐圧が問題となる場合は、モータなどのＬ負
荷の駆動時にデバイスをオン状態からオフ状態にするた
めにゲート電圧をソース電位に変化させた時である。こ
の時、Ｌ負荷により生じる逆起電力、即ち、はねあがり
電圧がドレインに印加される。図３の構造では、アルミ
配線（ゲート電極引出し線）１７がポリシリコンゲート
電極８と接続されている。従って、デバイスのオン状態
ではデバイスを動作させるために必要な数Ｖがアルミ配
線１７に印加されているが、ドレイン電極１３にはチッ
プのオン電圧、即ち、高々数Ｖ程度の電圧が印加されて
いるにすぎず、外周の耐圧構造は、この場合あまり問題
が無い。オフ時には、ドレイン電極１３には数十Ｖのは
ねあがり電圧が印加されるが、アルミ配線１７はソース
電位に固定されているため、アルミ配線１７の代わりに
ソース電極によりフィールドプレートを形成した場合と
全く同一の耐圧を得ることができる。従って、アルミ配
線１７をフィールドプレートとして用いることができ、
耐圧構造領域の耐圧を維持したまま、図１０に示した従
来構造における素子分離領域（外周部）Ｚ２の幅を小さ
くできる。つまり、図１０に示した従来構造において
は、ソース電極５５に接続されたアルミ配線５４とゲー
ト電極引出し線５１とを個別に備えたが、これに対し、
図３に示すように、本実施の形態ではチップの外形のサ
イズを小さくできる（素子分離領域Ｚ２の幅を、１５０
μｍ程度にできる）。That is, the drain of the power MOSFET
When the breakdown voltage between the sources becomes a problem, the gate voltage is changed to the source potential in order to turn the device from the ON state to the OFF state when driving the L load such as the motor. At this time, the counter electromotive force generated by the L load, that is, the rebounding voltage is applied to the drain. In the structure of FIG. 3, the aluminum wiring (gate electrode lead-out line) 17 is connected to the polysilicon gate electrode 8. Therefore, in the ON state of the device, the required number of V for operating the device is applied to the aluminum wiring 17, but the ON voltage of the chip, that is, a voltage of about several V at most is applied to the drain electrode 13. However, in this case, the withstand voltage structure on the outer circumference does not cause much problem. When the drain electrode 13 is turned off, a jumping voltage of several tens of volts is applied, but since the aluminum wiring 17 is fixed to the source potential, when the field plate is formed by the source electrode instead of the aluminum wiring 17. It is possible to obtain exactly the same breakdown voltage. Therefore, the aluminum wiring 17 can be used as a field plate,
The width of the element isolation region (outer peripheral portion) Z2 in the conventional structure shown in FIG. 10 can be reduced while maintaining the breakdown voltage of the breakdown voltage structure region. That is, in the conventional structure shown in FIG. 10, the aluminum wiring 54 connected to the source electrode 55 and the gate electrode lead wire 51 are individually provided.
As shown in FIG. 3, in the present embodiment, the outer size of the chip can be reduced (the width of the element isolation region Z2 is 150
It can be about μm).
【００２９】又、図２，５に示すように、四角形をなす
素子分離領域Ｚ２の角の部分においては、ソース電極延
設部２１の外側端がディープｐウェル領域１９の外周端
から距離Ｌ３だけ外側に位置しており、ソース電極延設
部２１がフィールドプレートとして機能している。よっ
て、図１０に示した従来構造におけるゲート電極引出し
線５１が不要となるため、素子分離領域（外周部）Ｚ２
の幅を小さくできる。つまり、角部以外でソース電位に
固定した場合に生じる無駄なディープｐウェル領域１９
とソース電極１１とのコンタクトスペースが無くなるた
めチップサイズを小さくできる。As shown in FIGS. 2 and 5, at the corners of the element isolation region Z2 having a quadrangular shape, the outer end of the source electrode extension portion 21 is separated from the outer peripheral end of the deep p-well region 19 by a distance L3. It is located outside and the source electrode extension portion 21 functions as a field plate. Therefore, since the gate electrode lead-out line 51 in the conventional structure shown in FIG. 10 is unnecessary, the element isolation region (outer peripheral portion) Z2
The width of can be reduced. In other words, the useless deep p-well region 19 that occurs when the source potential is fixed except at the corners
Since there is no contact space between the source electrode 11 and the source electrode 11, the chip size can be reduced.
【００３０】又、チップ内には複数の角部があるため、
この各角部をコンタクト部としてディープｐウェル領域
１９の電位をソース電位に固定すると、チップ内で均一
に電位を固定することができる。このようにすると、ス
イッチング時にドレイン電極にドレイン・ソース間電圧
以上の電圧が印加された場合に、局所的にアバランシェ
ブレークダウンが発生せずチップ面内で均一にアバラン
シェブレークダウンが発生するため、破壊耐量を高くす
ることができる。Since the chip has a plurality of corners,
By fixing the electric potential of the deep p-well region 19 to the source electric potential with each corner as a contact portion, the electric potential can be fixed uniformly in the chip. In this way, when a voltage higher than the drain-source voltage is applied to the drain electrode during switching, avalanche breakdown does not occur locally, and avalanche breakdown occurs uniformly within the chip surface. The withstand amount can be increased.
【００３１】尚、角部以外の図３で示す箇所においてセ
ル形成領域Ｚ１とアルミ配線１７（ゲート電極引出し
線）を最短で接続しているため、チップのスイッチング
速度は従来構造の図１０と変わらない（スイッチング速
度の低下は回避される）。Since the cell forming region Z1 and the aluminum wiring 17 (gate electrode lead-out line) are connected in the shortest place other than the corners as shown in FIG. 3, the switching speed of the chip is different from that of the conventional structure shown in FIG. No (a reduction in switching speed is avoided).
【００３２】さらに、図２，４に示すように、四角形を
なす素子分離領域Ｚ２の辺の部分と角の部分の境界部分
においては、ポリシリコンゲート電極延設部１５の外側
端はディープｐウェル領域１９の外周端から距離Ｌ２だ
け外側に位置しており、ポリシリコンゲート電極延設部
１５がフィールドプレートとして機能し、この張り出し
部分Ｌ２により耐圧構造を得ている。Further, as shown in FIGS. 2 and 4, the outer end of the polysilicon gate electrode extension 15 is located at the deep p-well at the boundary between the side and the corner of the quadrangular element isolation region Z2. The polysilicon gate electrode extension 15 is located outside the outer periphery of the region 19 by a distance L2 and functions as a field plate, and the projecting portion L2 provides a breakdown voltage structure.
【００３３】つまり、この箇所（図２の間隔４０を設け
た箇所）においてはソース電極延設部２１とアルミ配線
（ゲート電極引出し線）１７を絶縁しており、この箇所
ではポリシリコンゲート電極延設部１５をフィールドプ
レートとして用いている。厳密に述べると、図４の構造
は、フィールドプレート（１５）の下部の酸化膜の厚み
が図３に比べシリコン酸化膜（層間絶縁膜）１６の分だ
けわずかに薄くなる。従って、ドレイン電極１３に電圧
を印加した場合にシリコン表面の電界強度が図３の構造
より上昇する。そのため、耐圧は、図３の構造よりわず
かに低下する。しかし、この低下は、図４のフィールド
プレート（１５）の張り出し長さＬ２を図３の長さＬ１
より長くすることによりシリコン表面の電界強度を緩和
することができ耐圧を図３と等しくすることができる。
つまり、素子分離領域Ｚ２の全周にわたりフィールドプ
レート張り出し長さＬ１，Ｌ２，Ｌ３を調整することに
より、チップ外周の耐圧を全域で等しくしている。That is, the source electrode extension 21 and the aluminum wiring (gate electrode lead-out line) 17 are insulated at this location (where the space 40 is provided in FIG. 2), and at this location, the polysilicon gate electrode extension is provided. The installation portion 15 is used as a field plate. Strictly speaking, in the structure of FIG. 4, the thickness of the oxide film below the field plate (15) is slightly thinner than that of FIG. 3 by the amount of the silicon oxide film (interlayer insulating film) 16. Therefore, when a voltage is applied to the drain electrode 13, the electric field strength on the silicon surface is higher than that in the structure of FIG. Therefore, the breakdown voltage is slightly lower than that of the structure of FIG. However, this decrease is caused by the extension length L2 of the field plate (15) shown in FIG. 4 from the length L1 shown in FIG.
By making it longer, the electric field strength on the silicon surface can be relaxed and the breakdown voltage can be made equal to that in FIG.
That is, by adjusting the field plate overhanging lengths L1, L2, L3 over the entire circumference of the element isolation region Z2, the breakdown voltage of the chip outer circumference is made equal throughout.
【００３４】このようにして図４の断面構造では、図１
０に示した従来構造でのゲート電極用アルミ配線５１、
およびディープｐウェル領域５３とアルミ配線５４のコ
ンタクトスペースが無くなるため、図１０に示した従来
構造における素子分離領域（外周部）Ｚ２の幅を小さく
できる。Thus, in the sectional structure of FIG.
Aluminum wiring 51 for the gate electrode in the conventional structure shown in 0,
Since the contact space between the deep p-well region 53 and the aluminum wiring 54 is eliminated, the width of the element isolation region (outer peripheral portion) Z2 in the conventional structure shown in FIG. 10 can be reduced.
【００３５】このように本実施の形態は、下記の特徴を
有する。
（イ） 図３に示すように、セル形成領域Ｚ１の周囲に
おけるディープｐウェル領域（素子分離用不純物拡散領
域）１９の上に酸化膜１４，１６を介して縦型ＭＯＳＦ
ＥＴのポリシリコンゲート電極８のアルミ配線（金属配
線）１７をディープｐウェル領域１９よりも外側に張り
出した状態で延設し、アルミ配線１７をフィールドプレ
ートとして用いたので、セル形成領域Ｚ１の周囲の素子
分離領域Ｚ２において、図１０に示したソース電極と接
続されたアルミ配線（フィールドプレート構成体）５４
とアルミ配線５１とを個別に備えた場合に比べて、素子
分離領域Ｚ２の幅を狭くでき、素子分離領域Ｚ２を小面
積化してチップ面積を小さくすることができる。
（ロ） 図５に示すように、ソース電極１１をセル形成
領域Ｚ１の角部から外方に延設し、角部外方にてソース
電極延設部２１とディープｐウェル領域（素子分離用不
純物拡散領域）１９とを電気的に接続したので、角部以
外でソース電極延設部とディープｐウェル領域１９とを
接続する場合に比べ無駄なコンタクトスペースが無くな
る。
（ハ） 図４に示すように、素子分離領域Ｚ２における
ディープｐウェル領域（不純物拡散領域）１９の上にＬ
ＯＣＯＳ酸化膜１４を介して縦型ＭＯＳＦＥＴのポリシ
リコンゲート電極８をディープｐウェル領域１９よりも
外側に張り出した状態で延設し、ポリシリコンゲート電
極延設部１５をフィールドプレートとして用いたので、
素子分離領域Ｚ２において、図１０に示したソース電極
と接続されたアルミ配線（フィールドプレート構成体）
５４とアルミ配線５１とを備えた場合に比べて素子分離
領域Ｚ２の幅を狭くでき、素子分離領域Ｚ２を小面積化
してチップ面積を小さくすることができる。
（ニ） ＭＯＳＦＥＴのユニットセルの平面形状が四角
形（正方形）となっているので、セル形成領域Ｚ１の形
状を矩形（長方形）にでき、セル形成領域Ｚ１の外周部
（境界部）を直線化できる（凹凸のない形状にでき
る）。そのためＭＯＳＦＥＴのユニットセルの平面形状
を四角形以外の形状とした場合に比べ、素子分離領域
（耐圧構造領域）の面積を小さくできる。As described above, the present embodiment has the following features. (A) As shown in FIG. 3, a vertical MOSF is formed on the deep p-well region (element isolation impurity diffusion region) 19 around the cell formation region Z1 via oxide films 14 and 16.
Since the aluminum wiring (metal wiring) 17 of the polysilicon gate electrode 8 of ET is extended in a state of protruding outside the deep p well region 19 and the aluminum wiring 17 is used as a field plate, the periphery of the cell formation region Z1 is used. Of the aluminum wiring (field plate structure) 54 connected to the source electrode shown in FIG.
The width of the element isolation region Z2 can be narrowed, and the area of the element isolation region Z2 can be reduced to reduce the chip area, as compared with the case where the aluminum wiring 51 and the aluminum wiring 51 are individually provided. (B) As shown in FIG. 5, the source electrode 11 is extended outward from the corner of the cell formation region Z1, and the source electrode extension 21 and the deep p-well region (for element isolation) are provided outside the corner. Since the impurity diffusion region) 19 is electrically connected, useless contact space is eliminated as compared with the case where the source electrode extension portion and the deep p-well region 19 are connected at a portion other than the corner portion. (C) As shown in FIG. 4, L is formed on the deep p-well region (impurity diffusion region) 19 in the element isolation region Z2.
Since the polysilicon gate electrode 8 of the vertical MOSFET is extended via the OCOS oxide film 14 in a state of overhanging to the outside of the deep p well region 19, and the polysilicon gate electrode extension 15 is used as a field plate.
Aluminum wiring (field plate structure) connected to the source electrode shown in FIG. 10 in the element isolation region Z2.
The width of the element isolation region Z2 can be narrowed as compared with the case where 54 and the aluminum wiring 51 are provided, and the element isolation region Z2 can be reduced in area to reduce the chip area. (D) Since the planar shape of the unit cell of the MOSFET is a quadrangle (square), the shape of the cell formation region Z1 can be a rectangle (rectangle), and the outer peripheral portion (boundary portion) of the cell formation region Z1 can be linearized. (Can be made into a shape without irregularities). Therefore, the area of the element isolation region (breakdown voltage structure region) can be made smaller than in the case where the planar shape of the unit cell of the MOSFET is not a quadrangle.
【００３６】尚、ユニットセルの形状は略正方形であっ
たが、三角形や五角以上の多角形や円形でもよい。又、
帯状（ストライプ形状）でもよい。
（第２の実施の形態）次に、この発明の第２の実施の形
態を、第１の実施の形態との相違点を中心に説明する。Although the unit cell has a substantially square shape, it may have a triangular shape, a polygon having five or more pentagons, or a circular shape. or,
It may be strip-shaped (striped). (Second Embodiment) Next, a second embodiment of the present invention will be described focusing on the difference from the first embodiment.
【００３７】図７は、第１の実施の形態の図２に代わる
本実施の形態の縦型パワーＭＯＳＦＥＴ（チップ）の平
面図である。図８は図７のＤ−Ｄ断面図であり、図７の
Ｅ−Ｅ断面は図３と同じである。FIG. 7 is a plan view of a vertical power MOSFET (chip) of this embodiment, which replaces FIG. 2 of the first embodiment. 8 is a sectional view taken along the line DD of FIG. 7, and the sectional view taken along the line EE of FIG. 7 is the same as that of FIG.
【００３８】上記第１の実施の形態ではセル形成領域Ｚ
１の角部外方にてソース電極延設部２１とディープｐウ
ェル領域（素子分離用不純物拡散領域）１９とを電気的
に接続したが、本例では図７に示すように、角部以外の
素子分離領域Ｚ２においてポリシリコンゲート電極８の
アルミ配線（金属配線）１７よりもセル側でポリシリコ
ンゲート電極延設部１５の無い領域２４（図８に示す）
を設け、この領域２４においてソース電極延設部２５と
ディープｐウェル領域（素子分離用不純物拡散領域）１
９とをコンタクトホール（開口部）２６を通して電気的
に接続している。この構造においても図１０に示したゲ
ート電極と接続されたアルミ配線５４とアルミ配線５１
とを備えた場合に比べて素子分離領域Ｚ２の幅を狭くで
き、素子分離領域Ｚ２を小面積化してチップ面積を小さ
くすることができる。さらにこの構造を用いると、素子
分離領域Ｚ２の角部においてソース電極延設部（２１）
とディープｐウェル領域（不純物拡散領域）１９とを電
気的に接続していないためポリシリコンゲート電極８の
アルミ配線（金属配線）１７をチップ外周全域につなげ
て形成することができるためチップ全域にゲート信号を
高速に伝えることができる。さらに、フィールドプレー
ト構造はゲート電極と接続されたアルミ配線１７のみに
より形成されるようになり、フィールドプレート構造の
耐圧はチップ面内で完全に等しくなるため、フィールド
プレート構造の耐圧より高い電圧がドレイン・ソース間
に加わった場合においてもチップ面内で均一にアバラン
シェブレークダウンが発生するため破壊耐量を高くする
ことができる。In the first embodiment, the cell formation region Z
The source electrode extension portion 21 and the deep p-well region (element isolation impurity diffusion region) 19 were electrically connected to each other outside the corner portion of 1. However, in this example, as shown in FIG. 24 in the element isolation region Z2 of the polysilicon gate electrode 8 on the cell side of the aluminum wiring (metal wiring) 17 without the polysilicon gate electrode extension 15 (shown in FIG. 8).
In this region 24, the source electrode extension 25 and the deep p-well region (element isolation impurity diffusion region) 1 are provided.
9 are electrically connected to each other through a contact hole (opening) 26. Also in this structure, the aluminum wiring 54 and the aluminum wiring 51 connected to the gate electrode shown in FIG.
The width of the element isolation region Z2 can be made narrower than that in the case of including, and the area of the element isolation region Z2 can be reduced to reduce the chip area. Further, by using this structure, the source electrode extension portion (21) is provided at the corner of the element isolation region Z2.
Since the deep p-well region (impurity diffusion region) 19 is not electrically connected, the aluminum wiring (metal wiring) 17 of the polysilicon gate electrode 8 can be formed by being connected to the entire outer periphery of the chip, so that the entire area of the chip can be formed. The gate signal can be transmitted at high speed. Further, the field plate structure is formed only by the aluminum wiring 17 connected to the gate electrode, and the withstand voltage of the field plate structure is completely equal within the chip surface. Therefore, a voltage higher than the withstand voltage of the field plate structure is drained. -Avalanche breakdown occurs evenly in the chip surface even when it is applied between the sources, so the breakdown resistance can be increased.
【００３９】これまで説明した各実施の形態の他にも次
のように実施してもよい。上記実施の形態では、ｎチャ
ネル型について説明したが、ｎ型とｐ型の半導体の導電
型を入れ換えたｐチャネル型についても同様の効果が得
られることは言うまでもない。In addition to the embodiments described above, the following may be implemented. In the above-described embodiment, the n-channel type has been described, but it goes without saying that the same effect can be obtained also for the p-channel type in which the conductivity types of the n-type semiconductor and the p-type semiconductor are switched.
【００４０】さらに、溝を有する縦型ＭＯＳＦＥＴ以外
にも、ラテラルＤＭＯＳＦＥＴを含む横型パワーＭＯＳ
ＦＥＴ、あるいは溝のないプレーナ型のＭＯＳＦＥＴに
適用してもよい。Further, in addition to the vertical MOSFET having a groove, a lateral power MOS including a lateral DMOSFET.
It may be applied to a FET or a planar MOSFET having no groove.
【００４１】さらには、上記実施の形態では、縦型パワ
ーＭＯＳＦＥＴのみを用いたＩＣについて説明したが、
それに限定されるものではなく、このような縦型パワー
ＭＯＳＦＥＴを組み込んだパワーＭＯＳＩＣに適用して
もよい。Further, in the above embodiment, the IC using only the vertical power MOSFET has been described.
The present invention is not limited to this, and may be applied to a power MOSIC incorporating such a vertical power MOSFET.
【００４２】又、上記実施の形態では、半導体基板とし
てｎ+ 型半導体基板を用いた縦型パワーＭＯＳＦＥＴに
ついて説明したが、ｐ+ 型半導体基板を用いた絶縁ゲー
ト型バイポーラトランジスタ（ＩＧＢＴ）のゲート構造
にも適用することができる。Further, although the vertical power MOSFET using the n + type semiconductor substrate as the semiconductor substrate has been described in the above embodiment, the gate structure of the insulated gate bipolar transistor (IGBT) using the p + type semiconductor substrate. Can also be applied to.
【図１】 実施の形態の縦型パワーＭＯＳＦＥＴの平面
図。FIG. 1 is a plan view of a vertical power MOSFET according to an embodiment.
【図２】 図１でのチップ角部の拡大図。FIG. 2 is an enlarged view of a corner portion of the chip in FIG.
【図３】 図２のＡ−Ａ断面図。3 is a sectional view taken along line AA of FIG.
【図４】 図２のＢ−Ｂ断面図。FIG. 4 is a sectional view taken along line BB of FIG.
【図５】 図２のＣ−Ｃ断面図。5 is a sectional view taken along line CC of FIG.
【図６】 図３のＸ部拡大図。FIG. 6 is an enlarged view of part X in FIG.
【図７】 第２の実施の形態におけるチップ角部の拡大
平面図。FIG. 7 is an enlarged plan view of a corner portion of a chip according to the second embodiment.
【図８】 図７のＤ−Ｄ断面図。8 is a cross-sectional view taken along the line DD of FIG.
【図９】 従来の縦型パワーＭＯＳＦＥＴの平面図。FIG. 9 is a plan view of a conventional vertical power MOSFET.
【図１０】 図９のＦ−Ｆ断面図。10 is a sectional view taken along line FF of FIG.
１…半導体基板、６…溝、８…ポリシリコンゲート電
極、１１…ソース電極、１３…ドレイン電極、１４…Ｌ
ＯＣＯＳ酸化膜、１５…ポリシリコンゲート電極延設
部、１６…シリコン酸化膜、１７…金属配線としてのア
ルミ配線、１９…素子分離用不純物拡散領域としてのデ
ィープｐウェル領域、２１…ソース電極延設部、Ｚ１…
セル形成領域、Ｚ２…素子分離領域。1 ... Semiconductor substrate, 6 ... Groove, 8 ... Polysilicon gate electrode, 11 ... Source electrode, 13 ... Drain electrode, 14 ... L
OCOS oxide film, 15 ... Polysilicon gate electrode extension, 16 ... Silicon oxide film, 17 ... Aluminum interconnection as metal interconnection, 19 ... Deep p-well region as element isolation impurity diffusion region, 21 ... Source electrode extension Department, Z1 ...
Cell formation region, Z2 ... Element isolation region.
Claims (6)
ＳＦＥＴのユニットセルが多数形成されるとともに半導
体基板の表面にソース電極が形成され、さらに、前記セ
ル形成領域の周囲において半導体基板の表層部に当該表
層部の導電型とは逆導電型の素子分離用不純物拡散領域
が延設されるとともに当該素子分離用不純物拡散領域の
上に酸化膜を介してフィールドプレートが前記素子分離
用不純物拡散領域よりも外側に張り出した状態で延設さ
れた半導体装置において、 前記セル形成領域の周囲における前記素子分離用不純物
拡散領域の上に酸化膜を介してＭＯＳＦＥＴのゲート電
極の金属配線を前記素子分離用不純物拡散領域よりも外
側に張り出した状態で延設し、ゲート電極の金属配線を
フィールドプレートとして用いるとともに、前記ソース
電極を前記セル形成領域の角部から外方に延設し、当該
角部外方にてソース電極延設部と前記素子分離用不純物
拡散領域とを電気的に接続したことを特徴とする半導体
装置。1. A MO to cell forming region definitive the semiconductor substrate
A large number of SFET unit cells are formed, a source electrode is formed on the surface of the semiconductor substrate, and element isolation of a conductivity type opposite to the conductivity type of the surface layer portion is formed on the surface layer portion of the semiconductor substrate around the cell formation region. the isolation field plate through the oxide film on the element isolation diffusion region with use impurity diffusion region is extended
In the semiconductor device extended in a state of being projected outward from the impurity diffusion region for use, a metal wiring of the gate electrode of the MOSFET is formed on the impurity diffusion region for element isolation around the cell formation region via an oxide film. the element than isolation impurity diffused region extending in a state of projecting outward, a metal wiring of the gate electrodes as a field plate Rutotomoni, the source
The electrode is extended outward from the corner of the cell formation region,
The source electrode extension and the element isolation impurities outside the corner
A semiconductor device characterized by being electrically connected to a diffusion region .
ＳＦＥＴのユニットセルが多数形成されるとともに半導
体基板の表面にソース電極が形成され、さらに、前記セ
ル形成領域の周囲において半導体基板の表層部に当該表
層部の導電型とは逆導電型の素子分離用不純物拡散領域
が延設されるとともに当該素子分離用不純物拡散領域の
上に酸化膜を介してフィールドプレートが前記素子分離
用不純物拡散領域よりも外側に張り出した状態で延設さ
れた半導体装置において、 前記ＭＯＳＦＥＴにおけるポリシリコンゲート電極の半
導体基板側にはゲート酸化膜が形成されており、 前記セル形成領域の周囲における前記素子分離用不純物
拡散領域の上には、ゲート酸化膜の厚さより厚く形成さ
れた酸化膜を介して前記ポリシリコンゲート電極を前記
素子分離用不純物拡散領域よりも外側に張り出した状態
で延設したポリシリコンゲート電極延設部を設け、該ポ
リシリコンゲート電極延設部をフィールドプレートとし
て用いたことを特徴とする 半導体装置。2. An MO in a cell formation region of a semiconductor substrate.
A large number of SFET unit cells are formed and a semiconductor
A source electrode is formed on the surface of the body substrate.
The surface layer of the semiconductor substrate around the
Impurity diffusion region for element isolation of the conductivity type opposite to that of the layer portion
Of the impurity diffusion region for element isolation
The field plate is separated by the oxide film on the top.
Extending outside the impurity diffusion area for
In the semiconductor device described above, half of the polysilicon gate electrode in the MOSFET is
A gate oxide film is formed on the conductor substrate side, and the element isolation impurities around the cell formation region are formed.
Over the diffusion region, formed thicker than the thickness of the gate oxide film.
The polysilicon gate electrode through the oxide film
The state of overhanging from the impurity diffusion region for element isolation
The polysilicon gate electrode extension part extended by
The extension of the polysilicon gate electrode is used as the field plate.
Semiconductor device characterized by being used as
部から外方に延設し、当該角部外方にてソース電極延設
部と前記素子分離用不純物拡散領域とを電気的に接続し
た請求項２に記載の半導体装置。3. The source electrode is formed at a corner of the cell formation region.
From the corner to the outside, and the source electrode extends outside the corner.
Part and the element isolation impurity diffusion region are electrically connected to each other.
The semiconductor device according to claim 2 .
る請求項１〜３のいずれか１項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the MOSFET has a groove.
平面形状が四角形である請求項１〜４のいずれか１項に
記載の半導体装置。5. A semiconductor device according to any one of claims 1-4 unit cell of the MOSFET is its plan shape is square.
外方に延設し、当該外方にて前記ソース電極延設部と前
記素子分離用不純物拡散領域とを電気的に接続したこと
を特徴とする請求項２に記載の半導体装置。 6. The source electrode from the cell formation region
Extend outward, and in front of the source electrode extension portion in front of the outside
Electrically connected to the impurity diffusion region for element isolation
The semiconductor device according to claim 2, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21162596A JP3525637B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21162596A JP3525637B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1056174A JPH1056174A (en) | 1998-02-24 |
| JP3525637B2 true JP3525637B2 (en) | 2004-05-10 |
Family
ID=16608877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21162596A Expired - Fee Related JP3525637B2 (en) | 1996-08-09 | 1996-08-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3525637B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003086801A (en) * | 2001-09-13 | 2003-03-20 | Sanyo Electric Co Ltd | Insulation gate type semiconductor device and method of manufacturing the same |
| JP4731796B2 (en) * | 2003-03-31 | 2011-07-27 | 三洋電機株式会社 | MOSFET |
| JP3715971B2 (en) | 2003-04-02 | 2005-11-16 | ローム株式会社 | Semiconductor device |
| JP4576799B2 (en) * | 2003-04-24 | 2010-11-10 | 富士電機システムズ株式会社 | Semiconductor device and manufacturing method thereof |
| JP4860102B2 (en) | 2003-06-26 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5223291B2 (en) | 2007-10-24 | 2013-06-26 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| DE112009004277T5 (en) * | 2008-12-25 | 2012-10-04 | Mitsubishi Electric Corp. | POWER SEMICONDUCTOR DEVICE |
| WO2011045834A1 (en) | 2009-10-14 | 2011-04-21 | 三菱電機株式会社 | Power semiconductor device |
| WO2011125274A1 (en) | 2010-04-06 | 2011-10-13 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing same |
| WO2011161721A1 (en) | 2010-06-24 | 2011-12-29 | 三菱電機株式会社 | Power semiconductor device |
| JP5641131B2 (en) | 2011-03-17 | 2014-12-17 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP6207676B2 (en) * | 2016-06-16 | 2017-10-04 | ルネサスエレクトロニクス株式会社 | Power MOSFET |
| JP7316746B2 (en) * | 2017-03-14 | 2023-07-28 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN107146812B (en) * | 2017-03-29 | 2019-12-03 | 西安电子科技大学 | Enhanced grid field plate GaN base current apertures hetero junction field effect device and preparation method thereof |
-
1996
- 1996-08-09 JP JP21162596A patent/JP3525637B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1056174A (en) | 1998-02-24 |
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