JP2003086801A - Insulation gate type semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a conventional MOSFET, a contact area in a chip corner section is large and therefore an interlayer insulation film in a corner section of an actual operation region is excessively etched at the time of contact photo etching, resulting in the increase in short defects between the gate and the source. SOLUTION: Since contact photo etching is conducted by using such a mask as to make an interlayer insulation film for protection in the chip corner section, excessive etching never goes beyond the interlayer insulation film for protection and thereby a predetermined area is obtained for the interlayer insulation film in the actual operation region. Consequently, the reduction in short defects between the gate and the source can be realized by a conventional process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an insulated gate which prevents over-etching of an interlayer insulating film at the outermost periphery of an actual operating region and reduces a gate-source short circuit defect. Type semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art The structure of a conventional power MOSFET having a trench structure is shown in FIG. 9 by taking an N-channel type as an example.

On the N ⁺ type silicon semiconductor substrate 21, N ⁻
A drain region 22 made of a positive type epitaxial layer is provided, and a P type channel layer 24 is provided on the surface thereof. A trench 27 penetrating the channel layer 24 and reaching the drain region 22 is provided, and the inner wall of the trench 27 is covered with the gate oxide film 3
A gate electrode 33 made of polysilicon, which is coated with 1 and is filled in the trench 27, is provided. An N ⁺ type source region 35 is formed on the surface of the channel layer 24 adjacent to the trench 27, and a P ⁺ type body contact is formed on the surface of the channel layer 24 between the source regions 35 of two adjacent cells and on the outer periphery of the actual operating region. Regions 34 and 34a are provided. Further, when the gate electrode 33 is applied, a channel region (not shown) is formed from the source region 35 along the trench 27. The gate electrode 33 is covered with an interlayer insulating film 36, and a source electrode 37 that contacts the source region 35 and the body contact regions 34 and 34a is provided. Specifically, one cell is represented by a small square.

Referring to FIGS. 10 to 17, a process of manufacturing a conventional power MOSFET having a trench structure will be described.

In FIG. 10, an N ⁺ type silicon semiconductor substrate 2 is shown.
A drain region 22 is formed by laminating an N ⁻ type epitaxial layer on the substrate 1. After forming an oxide film (not shown) on the surface, the oxide film in the planned channel layer 24 is etched. A dose of 3.0 is applied to the entire surface using this oxide film as a mask.
After implanting boron at × 10 ^13, it is diffused to form a P-type channel layer 24.

11 to 13 show a process of forming a trench.

In FIG. 11, NSG is formed on the entire surface by the CVD method.
(Non-doped Silicate Glass
The CVD oxide film 25 of s) is formed to a thickness of 3000Å.
Next, a mask made of a resist film is removed except for the portion to be the trench opening 26, and the CVD oxide film 25 is dry-etched to be partially removed. It is formed to 0.0 μm.

In FIG. 12, with the CVD oxide film 25 as a mask, the silicon semiconductor substrate in the trench opening 26 is dry-etched with CF-based gas and HBr-based gas to penetrate the channel layer 24 to reach the drain region 22.
A trench 27 having a depth of 0 μm is formed.

In FIG. 13, the trench 27 is formed by dummy oxidation.
A dummy oxide film of about 3000 Å is formed on the inner wall and the surface of the channel layer 24 to remove etching damage during dry etching. By removing the dummy oxide film formed by this dummy oxidation and the CVD oxide film 25 simultaneously with an oxide film etchant such as hydrofluoric acid, a stable gate oxide film can be formed. Further, there is an effect that the opening portion of the trench 27 is rounded by thermal oxidation at a high temperature to avoid electric field concentration in the opening portion of the trench 27.

In FIG. 14, a gate oxide film 31 and a gate electrode 33 are formed. That is, the entire surface is thermally oxidized to form the gate oxide film 31 with a thickness of, for example, about 700 Å according to the threshold value. Then, the gate electrode 33 embedded in the trench 27 is formed. That is, a non-doped polysilicon layer 32 is deposited on the entire surface, phosphorus is injected and diffused at a high concentration to increase the conductivity, and the gate electrode 33 is formed. After that, the polysilicon layer 32 deposited on the entire surface is dry-etched without a mask to fill the trench 27 with the gate electrode 3
Leave 3

In FIG. 15, a mask made of a resist film is used.
Selective boron dose 2.0 × 10¹⁵With ion injection
Enter, P⁺Shape body contact regions 34, 34a
After the formation, the resist film is removed. Furthermore, a new register
Expose the planned source region 35 and gate electrode 33 with
Mask so that it comes out, and dose arsenic 5.0 × 10 ¹⁵
Ion implantation with N⁺The source region 35 of the mold to the trench 2
7 is formed on the surface of the channel layer 24 adjacent to
Remove the membrane.

In FIG. 16, BPSG (Boron) is formed on the entire surface.
Phosphorus Silicate Glass
The s) layer is deposited by the CVD method to form the interlayer insulating film 36. After that, the interlayer insulating film 36 is left at least on the gate electrode 33 using the resist film PR as a mask. Also,
A contact hole between the source electrode 37 and the substrate (body contact region 34a) is provided on the outer periphery of the actual operation region, and patterning is performed so that the interlayer insulating film 36 remains on the outer periphery thereof.

In FIG. 17, a source electrode 37 is formed by depositing aluminum on the entire surface by a sputtering apparatus to contact the source region 35 and the body contact regions 34 and 34a.
To form.

[0014]

Such a conventional power M
A top view of the OSFET is shown in FIG. FIG. 18A is a corner portion of the chip, and FIG. 18B is an enlarged view thereof. The source electrode is omitted. The body contact regions 34 and 34a are provided in each cell of the actual operation region 40 and around the actual operation region 40. The body contact region 3 around the cell and the actual operating region is formed on the insulating film provided on the entire surface.
Photo-etching is performed using a mask patterned so as to expose 4, 34a to form an interlayer insulating film 36 on the gate electrode and on the outer periphery of the chip.

The body contact regions 34 and 34a are provided to stabilize the potential of the substrate. By contacting the source electrode with the body contact regions 34, 34a, the floating electrode state is suppressed and the avalanche withstand capability is prevented from lowering. Inside the actual operation region 40, the body contact region 34 is inevitably smaller in order to improve the cell density. Therefore, in the outer periphery of the actual operation region 40 where cells (trench) are not formed, the substrate surface is larger than each cell surface. Is exposed to contact the body contact region 34a and the source electrode.

Here, in the corner portion of the actual operation region 40, no trench is formed in the region close to the routed portion 50 of the gate electrode surrounding the outer periphery thereof (FIG. 18).
(A)). This is because when applied to the gate electrode, the applied voltage value of the gate electrode close to the corner is the actual operating region 40.
There is a possibility that it will be lower than the applied voltage value of the internal gate electrode, and even if a trench is formed up to that portion, for example, the actual operating area increase amount is less than 1%, so some space is secured at the corner portion. This is because it is better to do it. That is, in the corner portion of the chip, each cell (trench) is formed in a region that is chamfered at an angle of 45 degrees from the peripheral end portion of the gate electrode routing portion 50 around the chip.
The body contact region 34a is also larger.

Body contact region 34a having a large area
Is effective for stabilizing the potential of the substrate as described above. However, in contact photoetching, a photoresist mask is formed by exposure and etching is performed. Therefore, an etching error occurs due to the aperture ratio, and the larger the contact area (opening area), the larger the etching area. There's a problem. For example, although there is no problem in a small area like the body contact region 34 of the actual operation region 40, the outer periphery of the actual operation region, especially the body contact area 34a of the corner portion is very large, and therefore etching proceeds excessively. Therefore, the outermost cell of the actual operation area 40 is affected. That is,
The interlayer insulating film 36 covering the outermost peripheral gate electrode does not have a predetermined area due to contact etching on the outer side thereof, and the source electrode and the gate electrode provided thereon are short-circuited,
There is a problem that a leak occurs.

[0018]

The present invention has been made in view of the above problems, and is characterized in that a protective interlayer insulating film is provided on a semiconductor substrate outside an actual operation region in which cells of many MOS transistors are arranged. The protective interlayer insulating film is provided outside the interlayer insulating film on the gate electrode at the outermost periphery of the actual operation region to reduce the gate-source short circuit failure.

The mask pattern is characterized in that photo-etching is performed so that a protective insulating film is formed on the semiconductor substrate outside the actual operation region in which cells of many MOS transistors are arranged. By changing it, a protective insulating film can be formed, and the contact aperture ratio adjacent to the outermost periphery of the actual operation region can be reduced.

Thus, an insulated gate semiconductor device can be manufactured which can prevent excessive etching of the interlayer insulating film covering the gate electrode at the outermost periphery of the actual operating region and reduce the gate-source short circuit defect without increasing the number of special steps. It provides a method.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail by taking an N-channel trench MOSFET as an example.

FIG. 1 shows the structure of the power MOSFET of the present invention. 1A is a cross-sectional view and FIG. 1B is a top view of a corner portion.

The power MOSFET includes semiconductor substrates 1 and 2.
, Channel layer 4, trench 7, and gate insulating film 11
, A gate electrode 13, a source region 15, a body contact region 14, an interlayer insulating film 16 and a protective interlayer insulating film 16a.

The semiconductor substrate is formed by laminating an N ⁻ type epitaxial layer to be the drain region 2 on an N ⁺ type silicon semiconductor substrate 1.

The channel layer 4 is a diffusion region in which P type boron or the like is selectively implanted into the surface of the drain region 2 and is formed shallower than the depth of the trench 7. This channel layer 4
A channel region (not shown) is formed in the region adjacent to the trench 7.

The trench 7 penetrates the channel layer 4 and reaches the drain region 2. Generally, patterning is performed on a semiconductor substrate in a lattice shape or a stripe shape. A gate oxide film 11 is provided on the inner wall of the trench 7 so that the gate electrode 1
Embed polysilicon to form 3.

The gate oxide film 11 is provided at least on the inner wall of the trench 7 which is in contact with the channel layer 4 and has a thickness of several hundred Å according to the driving voltage. Since the gate oxide film 11 is an insulating film, it has a MOS structure by being sandwiched between the gate electrode 13 provided in the trench 7 and the semiconductor substrate.

The gate electrode 13 is made of polysilicon buried in the trench 7, and N-type impurities are introduced into the polysilicon in order to reduce the resistance. The gate electrode 13 extends to a gate connection electrode (not shown) surrounding the semiconductor substrate and is connected to a gate pad electrode (not shown) provided on the semiconductor substrate.

The source region 15 is a diffusion region in which N ⁺ type impurities are implanted into the surface of the channel layer 4 adjacent to the trench 7, and is in contact with the metal source electrode 17 covering the operation region. Further, on the surface of the channel layer 4 between the adjacent source regions 15 and the surface of the channel layer 4 around the actual operation region,
Body contact region 1 which is a P ⁺ -type impurity diffusion region
4 is provided to stabilize the potential of the substrate. As a result, the portion surrounded by the adjacent trenches 7 becomes one cell, and a large number of these cells are gathered to form the actual operation region 20.

The inter-layer insulating film 16 is provided to insulate the source electrode 17 and the gate electrode 13 from each other.
Is provided so as to cover a part of the trench and leave a part of the trench opening.

The protective interlayer insulating film 16a is provided on the surface of the semiconductor substrate outside the actual operating region 20. It is continuous with the interlayer insulating film 16 covering the gate electrode 13 in the actual operation region 20, and reaches the outside of the outermost trench of the actual operation region 20. In addition, the interlayer insulating film 16 and the protective interlayer insulating film 16
A body contact region 14a having the same shape as the body contact region 14 of each cell is provided between a and a.

The source electrode 17 is a metal electrode formed by sputtering aluminum or the like into a desired shape, covers the actual operation region, and contacts the source region 15 and the body contact regions 14 and 14a.

As is clear from the figure, the body contact region 34a on the outer periphery of the actual operation region is minute. Since the photoetching at the time of forming the interlayer insulating films 16 and 16a etches this minute opening width, the interlayer insulating film 16 covering the gate electrode at the outermost periphery of the actual operating region is not affected by excessive etching. . Further, although a large area is opened on the outer side, the actual operation region is not affected even if the lateral etching is excessive here because of the protective interlayer insulating film 16a.

Further, the protective interlayer insulating film 16a has only to be provided once around the outer periphery of the actual operating region, and the body contact region 14a having the same shape as the cell is further provided, which is sufficient to stabilize the potential of the substrate. Is.

Next, a method of manufacturing an insulated gate type semiconductor device having a trench structure according to the present invention will be described with reference to an N channel type power MOSF.
An example of ET is shown in FIGS.

In the method for manufacturing a power MOSFET of the present invention, a step of forming a channel layer of one conductivity type on a semiconductor substrate of one conductivity type to be a drain region and a trench penetrating the channel layer and reaching the drain region are formed. Steps, a step of forming a gate insulating film covering the inner wall of the trench, a step of forming a gate electrode to be embedded in the trench, a source region of one conductivity type is formed on the surface of the channel layer adjacent to the trench, and a large number of cells are arranged. And a step of forming an actual operating region, an insulating film is formed on the entire surface, and an insulating film that covers the gate electrode and a protective insulating film that covers the semiconductor substrate around the corner of the actual operating region are formed. It is composed of a step of photoetching using a mask patterned as described above and a step of forming a metal electrode on the entire surface.

As shown in FIG. 2, the first step of the present invention is to form a channel layer 4 of opposite conductivity type on the surface of a semiconductor substrate of one conductivity type which becomes the drain region 2.

A drain region 2 is formed by laminating an N ⁻ type epitaxial layer on the N ⁺ type silicon semiconductor substrate 1. After forming an oxide film (not shown) on the surface, the oxide film in the portion of the planned channel layer 4 is etched. Using this oxide film as a mask, boron is implanted into the entire surface at a dose of 1.0 × 10 ¹³ and then diffused to form a P-type channel layer 4.

In the second step of the present invention, as shown in FIG. 3, the trench 7 penetrating the channel layer 4 and reaching the drain region 2 is formed.
To form.

In FIG. 3, NSG is formed on the entire surface by the CVD method.
(Non-doped Silicate Glass
The CVD oxide film 5 of s) is formed to a thickness of 3000Å. After that, a mask made of a resist film is applied except for the portion to be the trench opening, and the CVD oxide film 5 is partially dry-etched to form the trench opening in which the channel region 4 is exposed.

Then, using the CVD oxide film 5 as a mask, the silicon semiconductor substrate in the trench opening is CF-based and HB-based.
Dry etching is performed by using an r-based gas to form a trench 7 that penetrates the channel layer 4 and reaches the drain region 2.

The third step of the present invention is to form a gate insulating film on the inner wall of the trench 7 as shown in FIG.

Dummy oxidation is performed to form an oxide film (not shown) on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during the dry etching, and then this oxide film and the CVD oxide film 5 are removed. Remove by etching.

Further, the entire surface is thermally oxidized to form the gate oxide film 11
Is formed to have a thickness of about 700 Å according to the driving voltage.

The fourth step of the present invention is to form an electrode made of a semiconductor material to be buried in the trench, as shown in FIG.

A non-doped polysilicon layer is attached to the entire surface, and phosphorus is injected / diffused at a high concentration to increase the conductivity,
The gate electrode 13 is formed. After that, the polysilicon layer attached to the entire surface is dry-etched without a mask to leave the gate electrode 13 buried in the trench 7.

In the fifth step of the present invention, as shown in FIG. 6, a source region 15 of one conductivity type is formed in the channel layer 4 adjacent to the trench 7 to form an actual operation region in which a large number of cells are arranged. Especially.

First, in order to stabilize the potential of the substrate,
Boron is selectively ion-implanted at a dose of 2.0 × 10 ¹⁵ by a mask made of a resist film to form P ⁺ type body contact regions 14 and 14a, and then the resist film is removed.

After that, a new resist film is used to mask the planned source region 15 and gate electrode 13 so as to expose them, and arsenic is ion-implanted at a dose of 5.0 × 10 ^{15.
After the +} type source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7, the resist film is removed.

As a result, the region surrounded by the trench 7 is M
One OSFET cell is formed, and the actual operation region 20 in which many cells are arranged is formed.

In the sixth step of the present invention, as shown in FIG. 7, an insulating film is formed on the entire surface, and an insulating film for covering the gate electrode and a protective insulating film for covering the semiconductor substrate around the corner of the actual operating region are formed. Photoetching is performed using a mask patterned so that a film and a film are formed.

This step is a characteristic step of the present invention,
An interlayer insulating film for insulating the source electrode formed over the actual operation region and the gate electrode of each cell in a later step is formed. That is, BPSG (Boron Ph
An osphorus Silicate Glass) layer 16 is deposited by a CVD method. After that, the resist film P
R is attached, and the resist except for the formation of the interlayer insulating film is removed by a photolithography process (see FIG.
(A)), contact photo etching is performed. Specifically, the resist is provided on the gate electrode (trench) of each cell, and has a pattern having the same shape as the protective interlayer insulating film for at least one circumference outside the trench which is the outermost circumference of the actual operation region. Provide in part. After that, BPSG in the portion without the resist is removed by photoetching, and the interlayer insulating film 16 and the protective interlayer insulating film 16a are provided (FIG. 7B).

The interlayer insulating film 16 and the protective interlayer insulating film 16a are separated from each other by a contact region 14a having the same shape as the body contact region 14 of each cell. That is,
The body contact region 14a and the interlayer insulating film 16a are formed at the corner portion outside the actual operation region in the same shape as in the actual operation region 20 on the substrate surface without the trench.

In photoetching, when the aperture ratio is increased, the progress of etching in the lateral direction is increased, so that there is a problem of excessive etching when the contact opening area is large. However, in this step, by providing the protective interlayer insulating film 16a outside the actual operating region 20, the outside of the actual operating region 20 becomes a fine body contact region 14a having the same shape as each cell. That is, in this photoetching process, the interlayer insulating film 16 at the outermost periphery of the actual operation region 20 is not excessively etched, and the interlayer insulating film 16 having a predetermined size can be secured. Although the opening area is large outside the area and the lateral etching may be excessive, the interlayer insulating film 16a for protection does not affect the interlayer insulating film 16 at the outermost periphery of the cell.

As a result, when the source electrode 17 is formed in a later step, it is possible to prevent a short circuit between the gate and the source due to excessive etching of the interlayer insulating film.
This can greatly contribute to the reduction of short-circuit defects between sources.

The seventh step of the present invention is to form the metal electrode 17 on the entire surface as shown in FIG. Aluminum or the like is attached to the entire surface by a sputtering apparatus to cover the entire surface of the actual operation region 20 and form a source electrode 17 that contacts the source region 15 and the body contact region 14.

As described above, the embodiment of the present invention has been described by taking the N-channel type power MOSFET as an example, but the same can be applied to a MOS transistor whose conductivity type is reversed.

[0058]

According to the structure of the present invention, by providing the protective interlayer insulating film on the outer periphery of the actual operating region and providing the contact portion having the same shape as the body contact region, the contact opening area on the outer periphery of the actual operating region is provided. Therefore, excessive etching of the interlayer insulating film on the outermost peripheral gate electrode can be suppressed. Further, since the wide body contact region of the chip corner is formed, the interlayer insulating film 16 for protection is provided even if the lateral etching is excessive, so that the interlayer insulating film on the outermost peripheral gate electrode is affected. Therefore, short-circuit defects between the gate and the source can be reduced.

The protective interlayer insulating film may be provided only once, and since the body contact portion having the same shape as that of each cell is provided, the potential of the substrate is stabilized and the reduction of the avalanche withstand capability can be suppressed and the on-resistance can be suppressed. Also has the advantage that it can be secured as usual.

According to the manufacturing method of the present invention, the first
In addition, since it can be performed only by changing the mask pattern for forming the conventional interlayer insulating film, it is possible to provide a method for manufacturing an insulated gate semiconductor device that reduces short-circuit defects between the gate and the source by using the conventional process and apparatus.

Secondly, since it is only necessary to copy the contact pattern in the actual operation area, there is an advantage that the mask can be changed very easily.

That is, it is possible to provide a method for manufacturing an insulated gate semiconductor device capable of easily reducing the gate-source short circuit defect without changing the conventional process.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an insulated gate semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a conventional insulated gate semiconductor device.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the conventional insulated gate semiconductor device.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional insulated gate semiconductor device.

FIG. 15 is a cross-sectional view illustrating a method of manufacturing a conventional insulated gate semiconductor device.

FIG. 16 is a cross-sectional view illustrating the method of manufacturing the conventional insulated gate semiconductor device.

FIG. 17 is a cross-sectional view illustrating the method of manufacturing the conventional insulated gate semiconductor device.

FIG. 18 is an explanatory diagram of a conventional insulated gate semiconductor device.

Claims (8)

[Claims] 1. An insulated gate semiconductor device, comprising: a protective interlayer insulating film provided on a semiconductor substrate outside an actual operation region in which a large number of MOS transistor cells are arranged. 2. A semiconductor substrate of one conductivity type to be a drain region, a channel layer of opposite conductivity type provided on the surface of the semiconductor substrate, a trench penetrating the channel layer and reaching the semiconductor substrate, and a trench of the trench. A gate insulating film provided on the surface, a gate electrode made of a semiconductor material embedded in the trench, a source region of one conductivity type provided adjacent to the trench on the surface of the channel layer, and adjacent to the source region. In an insulated gate semiconductor device having an actual operation region in which a large number of cells each having a reverse-conductivity type body contact region provided on the surface of the channel layer and an interlayer insulating film covering at least the gate electrode are arranged, An insulated gate semiconductor device comprising: a protective interlayer insulating film provided on a semiconductor substrate outside the region. 3. The insulated gate semiconductor device according to claim 2, wherein the protective interlayer insulating film has the same shape as an interlayer insulating film covering the gate electrode. 4. The protective inter-layer insulating film and the inter-layer insulating film covering the outermost peripheral gate electrode of the actual operating region are separated from each other in a contact region having the same shape as that of the body contact region, in the actual operating region corner portion. The insulated gate semiconductor device according to claim 2, wherein the insulated gate semiconductor device is provided at least once. 5. A method of manufacturing an insulated gate type semiconductor device, characterized in that photoetching is performed so that a protective insulating film is formed on a semiconductor substrate outside an actual operation region in which cells of a large number of MOS transistors are arranged. Method. 6. A step of forming a channel layer of one conductivity type on a semiconductor substrate of one conductivity type to be a drain region, a step of forming a trench penetrating the channel layer and reaching the drain region, an inner wall of the trench A step of forming a gate insulating film covering the gate, a step of forming a gate electrode buried in the trench, and a source region of one conductivity type formed on the surface of the channel layer adjacent to the trench to form a large number of cells. A step of forming an actual operating region, an insulating film is formed on the entire surface, and an insulating film covering the gate electrode and a protective insulating film covering a semiconductor substrate around the corner of the actual operating region are formed. Of an insulated gate semiconductor device, comprising: a step of photoetching using a mask patterned as described above; and a step of forming a metal electrode on the entire surface. Production method. 7. The insulating film for protection is photo-etched using a mask patterned to have the same shape as an insulating film covering the gate electrode in the actual operation region. A method for manufacturing an insulated gate semiconductor device according to claim 6. 8. The insulating film for protection and the insulating film covering the gate electrode in the actual operating region are formed in a contact region having the same shape as the body contact region in the actual operating region and separated from each other. 7. The method for manufacturing an insulated gate semiconductor device according to claim 5 or 6.