JPH0254962A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0254962A JPH0254962A JP20698188A JP20698188A JPH0254962A JP H0254962 A JPH0254962 A JP H0254962A JP 20698188 A JP20698188 A JP 20698188A JP 20698188 A JP20698188 A JP 20698188A JP H0254962 A JPH0254962 A JP H0254962A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- layer
- sio2
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 239000011521 glass Substances 0.000 claims abstract description 6
- 239000010453 quartz Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 7
- 239000000377 silicon dioxide Substances 0.000 abstract 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 4
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000006722 reduction reaction Methods 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置及びその製造方法に関する。特に、
ＳＯ工溝構造持つ高速ＬＳＩの高信頼性化及び液晶テレ
ビに用いる薄膜トランジスタの高速、高信頼性化に有効
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same. especially,
It is effective in increasing the reliability of high-speed LSIs with SO groove structure and in increasing the speed and reliability of thin film transistors used in LCD televisions.
［従来の技ＷＩ］
従来、ＳＯ工半導体装置は、３１基板上には、Ｓｉｎ、
膜が形成され、５ｉ０２膜上に単結晶Ｓｉ％Ｊ膜が形成
されていた。こ、の半導体装置は２枚の熱酸化されたＳ
ｉ基板をはり合わせた後、−方の基板を研磨することに
より製作されていたため、接着部の５ＩＯ１／Ｓｉ０□
界面の接着強度が弱く、該Ｓｉ研磨工程や、該Ｓｉ薄膜
にデバイスを作成する工程で、該接着部Ｓ ｉ Ｏｚ
／ Ｓ １０を界面がはがれるという不具合が多発した
。また、薄膜トランジ゛スタ（ＴＩＦＴ）は、石英また
はガラス基板上に、多結晶またはアモルファスＳｉ層を
形成して、デバイスを作成したためデバイスの高速化が
困難であった。[Conventional Techniques WI] Conventionally, SO semiconductor devices have 31 substrates with Sin,
A single crystal Si%J film was formed on the 5i02 film. This semiconductor device consists of two thermally oxidized S
Since it was manufactured by polishing the − side of the board after gluing the i-boards together, 5IO1/Si0□ of the bonded part
The adhesion strength at the interface is weak, and during the Si polishing process or the process of creating a device on the Si thin film, the adhesion part SiOz
/ S10 had many problems with the interface peeling off. Furthermore, thin film transistors (TIFT) are fabricated by forming a polycrystalline or amorphous Si layer on a quartz or glass substrate, making it difficult to increase the speed of the device.
［発明が解決しようとする課Ｎ］
本発明は、かかる従来の不具合を回避し、Ｓｉ薄膜のは
がれが生じない、密着性の優れた高信頼性なかつ高速動
作可能な半導体装置とその製造方法を提供することを目
的とする。[Problem N to be solved by the invention] The present invention avoids such conventional problems, provides a highly reliable semiconductor device with excellent adhesion, which does not cause peeling of the Si thin film, and is capable of high-speed operation, and a manufacturing method thereof. The purpose is to provide.
［課題を解決するための手段］
本発明は、該単結晶Ｓｉ薄膜と該Ｓｉ０．基板間には、
Ｔａ、Ｖ、Ｔｉ、ＺｒｔＨｆなどのＶＡまたはＩＶＡ金
属の酸化膜が形成されることを特徴とし、該金属酸化膜
は、２枚のはり合わせるＳｉ基板の熱酸化膜とＳｉＯ□
基板を還元する反応によって得られるため、該金属酸化
膜とＳｉＯ□基板、Ｓｉ薄膜または５１０２膜とは非常
に優れた密着強度を持つ。このため、該Ｓｉ薄膜が該Ｓ
ｉ０□基板からはがれるという不具合が生じない。[Means for Solving the Problems] The present invention provides the single crystal Si thin film and the Si0. Between the boards,
It is characterized in that an oxide film of VA or IVA metal such as Ta, V, Ti, and ZrtHf is formed, and the metal oxide film is a thermal oxide film of two Si substrates to be bonded together and a SiO□
Since it is obtained by a reaction that reduces the substrate, the metal oxide film and the SiO□ substrate, Si thin film, or 5102 film have very excellent adhesion strength. Therefore, the Si thin film is
The problem of peeling off from the i0□ board does not occur.
［実施例］
以下実施例を用いて説明する。第１〜３図は、本発明に
よる半導体装置及びその製造工程断面図である。石英ま
たはガラスの３１０２基板１上には、Ｔｉ層２を形成し
、Ｓｉ基板６上には熱酸化膜５１０２層４を形成後（第
１図）、該’ｒＢ傷２と該Ｓｉｎ、層４を接触させ、熱
処理により、該Ｓｉｎ、基板１と該Ｓｉｎ、層４とを還
元し、７１０２層５を形成する（第２図）。この時、完
全にＴ１を酸化させる必要はな（，５で示す層にはＴｌ
Ｏ２にサンドイッチされたＴ１が残っても良い。また該
ＴｉＯ□層５上には、５１０２膜４′が残っても良い。[Example] The following will explain using examples. 1 to 3 are cross-sectional views of a semiconductor device according to the present invention and its manufacturing process. After forming a Ti layer 2 on a quartz or glass 3102 substrate 1 and forming a thermal oxide film 5102 layer 4 on a Si substrate 6 (FIG. 1), the 'rB scratches 2 and the Sin layer 4 are formed. are brought into contact with each other, and heat treatment reduces the Sin substrate 1 and the Sin layer 4 to form a 7102 layer 5 (FIG. 2). At this time, it is not necessary to completely oxidize T1 (the layer indicated by , 5 has Tl).
T1 sandwiched in O2 may remain. Further, the 5102 film 4' may remain on the TiO□ layer 5.
Ｔ１の膜厚と熱処理条件によりＳｉＯ□膜４′の膜厚は
コントロールできる。The thickness of the SiO□ film 4' can be controlled by the thickness of T1 and the heat treatment conditions.
また７１０２層５とＳｉｎ、膜４′の間には、Ｓｉ０．
の還元により生じる、ＴｉＳｉ□またはＳｉ層が存在し
ても良い。もしｓ ｉ ｏ２膜４が全部還元される時は
、ｓｉｏ、中の残りのＳｌは該Ｓｉ基板上に固相成長し
単結晶化する。第３図においては、該Ｓｉ基板３を研磨
することにより単結晶Ｓｉ薄膜層５′を得る。この後、
通常工程により、薄ＭＳＩ層３′に、ＴＩＦＴやデバイ
スを作成することにより、ＳＯ工溝構造持つ高速半導体
装置を得る。実施例ではＴ１を用いたが、Ｔａ。Moreover, between the 7102 layer 5 and the Sin film 4', Si0.
A TiSi□ or Si layer may also be present, resulting from the reduction of TiSi□ or Si. If the sio2 film 4 is completely reduced, the remaining sl in the sio2 film grows on the Si substrate in a solid phase and becomes a single crystal. In FIG. 3, the Si substrate 3 is polished to obtain a single crystal Si thin film layer 5'. After this,
By forming TIFTs and devices in the thin MSI layer 3' using normal processes, a high-speed semiconductor device having an SO groove structure is obtained. Although T1 was used in the example, Ta.
Ｖ、Ｚｒ、Ｈｆでも同様な効果を得ることができる。Similar effects can be obtained with V, Zr, and Hf.
第１図、第２図及び第３図は本発明による半導体装置の
製造工程断面図。
１・・・・・・・・・Ｓｉ０．基板
２・・・・・・・・・Ｔ１膜
６・・・・・・・・・Ｓｉ基板
４・・・・・・・・・ＳｉＯ□膜
５・・・・・・・・・ＴｌＯ２
４′・・・・・・Ｓｉ０．膜
以上
［発明の効果コ
本発明によれば、該Ｓｉ０２基板１と単結晶薄膜３′と
の接着は、Ｓｉｎ、膜の還元反応により行なわれるため
、密着性に優れ、デバイス作成時に膜はがれが生じない
。従って、高信頼性な半導体装置及びその製造方法が可
能になる。1, 2, and 3 are cross-sectional views of the manufacturing process of a semiconductor device according to the present invention. 1...Si0. Substrate 2...T1 film 6...Si substrate 4...SiO□ film 5...TlO2 4 '...Si0. More than a film [Effects of the invention] According to the present invention, the adhesion between the Si02 substrate 1 and the single crystal thin film 3' is performed by a reduction reaction of the Si film, so the adhesion is excellent and the film does not peel off during device fabrication. Does not occur. Therefore, a highly reliable semiconductor device and its manufacturing method are possible.
Claims (3)
ｉ薄膜にはデバイスを形成する、いわゆるＳＯＩ半導体
装置において、石英またはガラス基板上には、IVＡまた
はＶＡ金属酸化膜が形成され、該金属酸化膜上には、単
結晶Ｓｉ薄膜が形成されてなることを特徴とする半導体
装置。(1) Form a single-crystal Si thin film on an insulating film, and
In a so-called SOI semiconductor device in which a device is formed in an i-thin film, an IVA or VA metal oxide film is formed on a quartz or glass substrate, and a single-crystal Si thin film is formed on the metal oxide film. A semiconductor device characterized by:
属酸化膜及びＳｉＯ＿２膜が形成され、該上層ＳｉＯ＿
２膜上には、単結晶Ｓｉ薄膜が形成されてなることを特
徴とする半導体装置。(2) An IVA or VA metal oxide film and a SiO_2 film are formed on the quartz or glass substrate, and the upper layer SiO_2
1. A semiconductor device characterized in that a single crystal Si thin film is formed on the two films.
Ｓｉ基板IIを用い、Ｓｉ基板IIには熱酸化膜が形成され
、該ＳｉＯ＿２基板 I 上にはIVＡまたはＶＡ金属を蓄
積後、ＳｉＯ＿２基板 I の該金属面とＳｉ基板IIのＳ
ｉＯ＿２面とを接触させた後、熱処理により、ＳｉＯ＿
２基板 I 及びＳｉ基板IIのＳｉＯ＿２膜を還元し、該
金属の酸化物を形成後、該Ｓｉ基板IIを研磨することに
より、該ＳｉＯ＿２基板上に形成された絶縁層上には、
単結晶Ｓｉ薄膜が形成されることを特徴とする半導体装
置の製造方法。(3) Using a SiO_2 substrate I and a Si substrate II made of quartz or glass, a thermal oxide film is formed on the Si substrate II, and after accumulating IVA or VA metal on the SiO_2 substrate I, S of metal surface and Si substrate II
After contacting the iO_2 surface, the SiO_
2. By reducing the SiO_2 films of the substrate I and the Si substrate II to form an oxide of the metal, and polishing the Si substrate II, the insulating layer formed on the SiO_2 substrate has the following properties:
A method for manufacturing a semiconductor device, characterized in that a single crystal Si thin film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20698188A JPH0254962A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20698188A JPH0254962A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0254962A true JPH0254962A (en) | 1990-02-23 |
Family
ID=16532200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20698188A Pending JPH0254962A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0254962A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286252B1 (en) * | 1997-09-11 | 2001-04-16 | 박호군 | Electrostatic-thermal junction method for semiconductor sub strates |
| EP1225625A1 (en) * | 2001-01-18 | 2002-07-24 | Comtecs Co., Ltd | A method of manufacturing an SOI (Silicon On Insulator) wafer |
-
1988
- 1988-08-19 JP JP20698188A patent/JPH0254962A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286252B1 (en) * | 1997-09-11 | 2001-04-16 | 박호군 | Electrostatic-thermal junction method for semiconductor sub strates |
| EP1225625A1 (en) * | 2001-01-18 | 2002-07-24 | Comtecs Co., Ltd | A method of manufacturing an SOI (Silicon On Insulator) wafer |
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