JPH025442A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH025442A JPH025442A JP63154775A JP15477588A JPH025442A JP H025442 A JPH025442 A JP H025442A JP 63154775 A JP63154775 A JP 63154775A JP 15477588 A JP15477588 A JP 15477588A JP H025442 A JPH025442 A JP H025442A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bonding
- corner
- pad
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子に関し、特に、そのワイヤボンディ
ングの為のパッドの形態を改良してパッドへのワイヤの
ボンデ４フフ位置に融通性をもたせることのできる技術
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular, improves the shape of a pad for wire bonding to provide flexibility in the bonding position of a wire to a pad. Regarding the technology that can be used.
半導体チップは多数の外部への接続端子を持っており、
これらの端子を何らかの方法で接続してはじめてその機
能を発揮させることができる。その接続方法の一つはワ
イヤボンディング法であり、複数本の当該ボンディング
用のワイヤの各一端部と半導体チップ（以下チップとい
う）の上記各接続端子とをボンディングするとともに、
当該各ワイヤの他端部とチップを搭載している支持体例
えばリードフレームとをボンディングしている。当該ワ
イヤボンディング法にてワイヤボンディングされるチッ
プには、接続端子としてチップ内配線と接続した電極部
パッドをその周辺内側に備えている。このボンディング
すべき部分であるパッドは、例えばＡ２よりなる金属蒸
着被膜により構成され【いる。Semiconductor chips have many external connection terminals.
The function can only be achieved by connecting these terminals in some way. One of the connection methods is a wire bonding method, in which one end of each of the plurality of bonding wires is bonded to each of the connection terminals of a semiconductor chip (hereinafter referred to as a chip), and
The other end of each wire is bonded to a support, such as a lead frame, on which the chip is mounted. A chip to be wire-bonded by the wire bonding method is provided with electrode pads connected to internal wiring on the chip as connection terminals on the inner side of the periphery. The pad, which is the part to be bonded, is made of a metal vapor-deposited film made of A2, for example.
従来、このワイヤボンディングパッドは一般ニ同じ長さ
の四辺をもつ正方形に構成されている。Conventionally, wire bonding pads are generally square shaped with four sides of equal length.
なお、かかるワイヤボンディングパッドについて述べた
特許の例としては、特開昭５５−５５５４１号公報があ
げられる。Incidentally, an example of a patent describing such a wire bonding pad is Japanese Patent Application Laid-open No. 55541/1983.
しかるに、このように同じ長さの四辺をもつ正方形に構
成されたワイヤボンディングパッドを配列した場合には
、当該チップを収納するパッケージ品の変更に際して、
どうしてもそれまでのボンディングルールには適合しな
いということが起ってくる。その場合、このように、ど
うしてもボンディングルールを満足しないものについて
は、従来そのワイヤボッディングパッド（以下、単にパ
ッドという）の位置を変更するということで対処してき
た。そうなるとパッド設計に際し、パッド位置のみ異な
るマスクを例えば２種類用意する必要があるなど、極め
て効率の悪いものとならざるを得ない。However, when the wire bonding pads are arranged in a square shape with four sides of the same length, when changing the package that houses the chip,
Inevitably, something will happen that does not comply with the existing bonding rules. In such a case, if the bonding rule cannot be satisfied by any means, it has conventionally been dealt with by changing the position of the wire bonding pad (hereinafter simply referred to as pad). In this case, when designing a pad, it is necessary to prepare, for example, two types of masks that differ only in the pad position, which inevitably results in extremely inefficient design.
また、ワイヤと隣接するリードフレームのインナーリー
ドとのショートを回避するために、インナーリードへの
ワイヤのボンディングＱｔをパッケージ品の種類に応じ
て変更しなければならないということＫなる。Furthermore, in order to avoid short-circuiting between the wire and the inner lead of the adjacent lead frame, the bonding Qt of the wire to the inner lead must be changed depending on the type of packaged product.
なお、前記特開昭５５−５５５４１号公報には、インナ
ーリードの方向に合せて菱形のパッドを配列することが
記載されているが、これは、ワイヤボンディングのし易
さおよびパッド間隔を小にできるという効果があるもの
で、ボンディングルールに適合しないときには同様にパ
ッド位置の変更やインナーリードへのボンディング位置
の変更などを余儀なくされざるを得ない。Note that JP-A No. 55-5541 describes arranging diamond-shaped pads in accordance with the direction of the inner leads, but this is to facilitate wire bonding and to reduce the spacing between the pads. However, if the bonding rules are not met, it is necessary to change the pad position or the bonding position to the inner lead.
そこで、本発明はかかる従来技術の有する欠点を解消し
て、−のチップをベースとして、各種のパッケージ品を
パッド位置の変更などな（して展開することができ、ボ
ンディングルールへの対応を円滑にすることができ、特
に、柔軟な対応が要求されるゲートアレイ品に有効な技
術を提供することを目的とする。Therefore, the present invention eliminates the drawbacks of the prior art, and allows various packaged products to be developed based on the - chip without changing the pad position, thereby making it possible to smoothly comply with bonding rules. The purpose is to provide a technology that is particularly effective for gate array products that require flexible handling.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、均一な大きさの四辺の長さが同
じ正方形のパッドを配列するのではなく、チップのコー
ナー部の角に近づくにつれて、そのパッドの当該チップ
のコーナー辺に平行な一対の辺の長さを長くするように
、パッドを配列した。That is, in the present invention, instead of arranging square pads of uniform size and having the same length on all four sides, as the corner of the chip approaches, a pair of pads parallel to the corner sides of the chip are arranged. The pads were arranged to lengthen the sides.
ワイヤボンディングに際し、特に、ボンディングルール
を満足しないようになるのはチップコーナー部であり、
コーナー部の角に近づくに従ってそれはきびしくなる。During wire bonding, it is especially the chip corners that do not satisfy the bonding rules.
It gets more severe as you get closer to the corners.
コーナー部の角に近づ（につれてパッドのチップコーナ
ー辺に平、行な二辺が・長くなっていれば、パッドにワ
イヤをボンディングするに、ボーンディングルールを満
足するようにそのボンディング位置をずらすことができ
、すなわちボンディングの自由度を向上させることがで
き、ボンディングルールへの対応がスムーズになる。ボ
ンディングルールに対応しないからといって、パッド自
体の位置を変更したりすることが必要なくなる。従って
、同一製品でパッド位置のみが異なるマスクを２種類用
意するというな必要もなくなり、設計効率が良好になる
。If the two sides parallel to the chip corner side of the pad become longer as you approach the corner of the corner, shift the bonding position to satisfy the bonding rules when bonding the wire to the pad. In other words, the degree of freedom in bonding can be improved, and compliance with bonding rules becomes smooth.There is no need to change the position of the pad itself even if it does not comply with bonding rules. Therefore, there is no need to prepare two types of masks that are the same product but differ only in pad positions, and design efficiency is improved.
また、上記の如きパッド配列の１つのベースチップから
幾種類ものパッケージを展開することができ、設計に柔
軟性が要求されるゲートアレイ製品に極めて有利となる
。Further, it is possible to develop many types of packages from one base chip having the pad arrangement as described above, which is extremely advantageous for gate array products that require flexibility in design.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
第１図は本発明の実施例を示す平面図で、第２図は同要
部拡大平面図である。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is an enlarged plan view of the same essential parts.
これら図において、１はチップ、２はパッド、３は入出
力端子、４はボンディングワイヤ、５はインナーリード
、６はリードフレームのタブ部、７はタブ吊りリードで
ある。In these figures, 1 is a chip, 2 is a pad, 3 is an input/output terminal, 4 is a bonding wire, 5 is an inner lead, 6 is a tab portion of a lead frame, and 7 is a tab suspension lead.
第１図に示すように、本発明では、チップｌの周辺内側
に複数適宜間隔を置いて配列されたパッド２について、
チップ１のコーナー部の角に行くにつれて、そのチップ
１のコーナー辺に平行な１対の辺の長さが長くなるよう
にしである。As shown in FIG. 1, in the present invention, a plurality of pads 2 are arranged at appropriate intervals inside the periphery of the chip l.
The length of a pair of sides parallel to the corner side of the chip 1 is made longer as one approaches the corner of the chip 1.
第２図に示すように、チップ１のコーナー部の角に最も
近いパッド２について見てみると、上記のようにチップ
１のコーナー辺に平行な１対の辺の長さが長くなった長
方形に構成しているので、インナーリード５とチップ１
のパッド２とをボンディングワイヤ４によりワイヤボン
ディングするに、例えば、パッド２における点Ａの位置
ではボンディングルールを満足しないときには点Ｂの位
置で、あるいは点Ｃの位置でというように、そのボンデ
ィング位置を変更できる自由度を増すことができる。As shown in Figure 2, when we look at the pad 2 closest to the corner of the chip 1, we see that it is a rectangle with a longer length of a pair of sides parallel to the corner sides of the chip 1, as shown above. Since the structure is configured as follows, inner lead 5 and chip 1
When performing wire bonding with the pad 2 using the bonding wire 4, for example, if the bonding rule is not satisfied at the position of point A on the pad 2, the bonding position is changed to the position of point B or the position of point C. You have more freedom to make changes.
第１図におけるａはボンディングワイヤ４と、隣接する
インナーリード５との間隔を示すが、この間隔ａ′を大
きくすることができ、所謂ワイヤシヲートを回避できる
。In FIG. 1, a indicates the distance between the bonding wire 4 and the adjacent inner lead 5, and this distance a' can be increased to avoid a so-called wire seat.
第３図は当該チップを収納したプラスチックパッケージ
の一部切欠斜視図を示し、当該パッケージ８は第１図や
第２図に示すようにワイヤボンディング後、樹脂モール
ドをして成り、樹脂モールド部９からはリードフレーム
１０のアウターリード１１が多数外部に引き出しされて
いる。FIG. 3 shows a partially cutaway perspective view of a plastic package that houses the chip, and the package 8 is formed by resin molding after wire bonding as shown in FIGS. 1 and 2, and the resin molded part 9 A large number of outer leads 11 of the lead frame 10 are drawn out from the.
当該リードフレーム１０は、例えばＦｅ−Ｎｉ合今によ
り構成されている。The lead frame 10 is made of, for example, a Fe--Ni composite.
チップ（半導体素子）１は、例えばシリコン単結晶基板
から成り、周知の技術によってこのチップ内には多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭＯＳ）ランジスタから
成り、これらの回路素子によって、例えば論理回路およ
びメモリの回路機能が形成されている。A chip (semiconductor element) 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A concrete example of a circuit element is, for example, a transistor (MOS), and these circuit elements form, for example, a logic circuit and a memory circuit function.
パッド２は１例えば、Ａ２蒸着膜により構成されている
。The pad 2 is made of, for example, an A2 vapor deposited film.
ボンディングワイヤ４は、例えばＡ ｕ線により構成さ
れている。The bonding wire 4 is made of, for example, an Au wire.
樹脂モールド部９は、例えばエポキシレジンにより構成
されている。The resin mold part 9 is made of, for example, epoxy resin.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
不発明によれば、パッドへのワイヤのボンディング位置
に融通性を持たせることができ、一つのバクドパターン
をもったチップにより、各種のパッケージに、ボンディ
ングルールに適合して対処することができた。According to the invention, it is possible to have flexibility in the bonding position of the wire to the pad, and a chip with one back pattern can be used in various packages in accordance with the bonding rules. Ta.
【図面の簡単な説明】
第１図は不発明の実施例を示す要部平面図、第２図は同
拡大平面図、
第３図は本発明の実施例を示すパッケージの一部切欠斜
視図である。
１・・・チップ、２・・パッド、３・・・入出力端子、
４・・ボンディングワイヤ、５・・・インナーリード、
６・・・タブ部、７・・・タブ吊りリード、８・・・パ
ッケージ、９・・・樹脂モールド部、１０・・・リード
フレーム、】１・・・アクタ−リード。
代理人 弁理士 小 川 勝 男
第 ３ ス[Brief Description of the Drawings] Fig. 1 is a plan view of essential parts showing an embodiment of the invention, Fig. 2 is an enlarged plan view of the same, and Fig. 3 is a partially cutaway perspective view of a package showing an embodiment of the invention. It is. 1...chip, 2...pad, 3...input/output terminal,
4...Bonding wire, 5...Inner lead,
6...Tab portion, 7...Tab hanging lead, 8...Package, 9...Resin mold part, 10...Lead frame, ]1... Actor lead. Agent: Patent Attorney Katsuo Ogawa No. 3
Claims (1)
ッドを複数当該半導体素子の周辺に沿って配列してなる
半導体素子において、当該素子の周辺に平行な前記ワイ
ヤボンディングパッドの一対の辺を、当該素子のコーナ
ー部の角に向って順次その長さを長くして成ることを特
徴とする半導体素子。1. In a semiconductor device in which a plurality of rectangular wire bonding pads are arranged along the periphery of the semiconductor device at appropriate intervals, a pair of sides of the wire bonding pads parallel to the periphery of the device are A semiconductor device characterized in that the length of the corner portion of the semiconductor device is gradually increased toward the corner of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63154775A JPH025442A (en) | 1988-06-24 | 1988-06-24 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63154775A JPH025442A (en) | 1988-06-24 | 1988-06-24 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025442A true JPH025442A (en) | 1990-01-10 |
Family
ID=15591623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63154775A Pending JPH025442A (en) | 1988-06-24 | 1988-06-24 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025442A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009267302A (en) * | 2008-04-30 | 2009-11-12 | Nec Electronics Corp | Semiconductor device and inspection method |
-
1988
- 1988-06-24 JP JP63154775A patent/JPH025442A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009267302A (en) * | 2008-04-30 | 2009-11-12 | Nec Electronics Corp | Semiconductor device and inspection method |
| US8334201B2 (en) | 2008-04-30 | 2012-12-18 | Renesas Electronics Corporation | Semiconductor device and inspection method therefor |
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