JPH025437A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a series resistance between a source and a gate by providing source, drain regions made of an epitaxial layer adjacent to a gate electrode and on a channel layer. CONSTITUTION:A nondoped GaAs buffer layer 12, a nondoped AlGaAs potential barrier layer 13 and an N-type GaAs channel layer 2 are sequentially laminated and formed on a semi-insulating GaAs substrate 11 by an epitaxially growing method, and a gate electrode 4 having a structure in which a nondoped AlGaAs gate high resististivity semiconductor layer 43 and a gate metal such as tungsten nitride 41 are laminated on an N-type GaAs layer 2 and N-type GaAs source, drain regions 6, 7 are formed by an epitaxially growing method. Thus, a field- effect transistor in which a series resistance between the source and the gate is reduced to improve its gm and to be adapted for a high speed operation, and the material of the source, drain region can be widely selected so as to have ohmic contact easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a field effect transistor using a semiconductor substrate and a method for manufacturing the same.

(Prior Art) There is a field effect transistor for high-speed operation using a compound semiconductor such as gallium arsenide (GaAs), which has higher electron mobility at room temperature than silicon, as a semiconductor substrate.

Among these field effect transistors, Figure 4 shows a cross section of a Schottky junction field effect transistor (hereinafter simply referred to as a field effect transistor), which is often used as a basic element of integrated circuits due to its simple structure. (
41) is a semi-insulating GaAs substrate, and (42) is an n-type channel region provided by ion implantation into the surface of this substrate.

A gate electrode (44) having Schottky characteristics is provided on this region. Also, this gate electrode (
44) Since ions are implanted from above, n-type source/drain regions (46) and (47) are formed in self-alignment on both sides. And on these regions are source/drain electrodes (48) exhibiting ohmic properties of AuGe.

(49) is provided. However, in such a field effect transistor, the current leaks through the substrate from the channel region (42) to the drain region (47) shown by the broken line, and the current flowing in the channel region (42) As the current drive capability (K value) decreases, the Schottky characteristic deteriorates as the impurity concentration of the n-type channel region (42) increases.

In order to prevent these problems, a transistor with a cross-sectional structure as shown in Fig. 5 is manufactured using a non-doped aluminum gallium arsenide (Aj:GaAs) layer (Aj:GaAs), which has a wider forbidden band width and higher resistivity than GaAs.
43) and (412) sandwich the channel region (42) from above and below to prevent the value and Schottky characteristics from deteriorating. The mutual conductance of this field effect transistor is expressed by the following equation (Yuro).

gm''' 1+Rs 0gmo'...(A
) gmo is the intrinsic conductance, and this is the maximum performance that can be extracted from this. Further, Rs is a series resistance between the source and gate.

However, this field four effect transistor has the following problems.

■ Since AI G, a A s, which has a wider bandgap and higher specific resistance than GaAs, is always located under the ohmic electrode, the series resistance CR, s between the source and cat
) will be higher. As a result, this field effect transistor has a high series resistance between the source and the gate, and as a result, the gm
It was not possible to make it larger. This has become a major problem as field effect transistors are miniaturized to form integrated circuit devices.

■ Not only under the gate electrode IJit (44), but also under the Au
Ge source/drain electrodes (48), (49)! AnGaAs source/drain region (46) that is difficult to make ohmic contact with this source/drain electrode V
, (47), so as long as this gate structure is adopted, the source/drain electrodes (4g) , (49
), the ohmic contact resistance of each of them becomes high.

(Problems to be Solved by the Invention) The present invention has been made in view of the above problems.
In addition to reducing the series resistance between gates and improving mutual conductance, it is suitable for high-speed operation, and the source and drain materials are selected to achieve good Ohmink contact without changing the gate structure. The first objective is to provide a possible field effect transistor.

A second object of the present invention is to provide a method for manufacturing a field effect transistor that can easily form such a field effect transistor.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above 3WJ, the first invention provides a channel layer exhibiting one conductivity type and a gate high resistivity semiconductor provided on the channel layer. A gate electrode consisting of a film and a gate metal layered on the gate high resistivity semiconductor film, and a source/drain region consisting of an epitaxial layer adjacent to the gate electrode and provided on the channel layer, respectively. The present invention provides a field effect transistor characterized by comprising:

A second invention also provides a channel layer exhibiting one conductivity type, a gate high resistivity semiconductor film formed with this channel layer, a gate metal formed on this gate high resistivity semiconductor film, and this gate metal. Provided is a field effect transistor comprising a gate electrode made of an insulator provided on the side wall of the transistor, and source and drain regions adjacent to the gate electrode and provided on the channel layer. It is.

Furthermore, a third invention includes a step of forming a channel layer exhibiting one conductivity type on the high resistivity layer, a step of forming a high resistivity semiconductor film on the channel layer, and a step of forming a high resistivity semiconductor film on the high resistivity semiconductor film. forming a gate metal processed into a desired shape; forming an insulator on the sidewalls of the gate metal; By selectively etching and removing the film and leaving the high resistivity semiconductor film under the gate metal and the insulator as a gate high resistivity semiconductor film, the gate metal, the insulator, and the gate high resistivity are removed. A step of forming a gate electrode made of a semiconductor film, and forming a source/drain region made of an epitaxial layer having the same conductivity type as the channel region and provided on the exposed surface of the channel layer in a self-aligned manner with the gate electrode. The present invention provides a method for manufacturing a field effect transistor, characterized by comprising the steps of:

(Function) The first and second inventions are provided with a gate electrode having a structure in which a gate metal is provided on a gate high resistivity semiconductor film, and a source/drain region that is self-aligned with this gate electrode is placed directly on a channel layer. is forming. As a result, the same film as the gate high resistivity semiconductor film is not interposed between the source region and the gate electrode, so that the series resistance between the source and the gate is reduced.

Furthermore, despite having such a gate electrode structure, the source/drain regions can be formed using a material that makes good ohmic contact with the source/drain electrodes, so the material for the source/drain regions can be selected as desired. I can do it.

In the third invention, the source region can be formed in self-alignment with the gate electrode after forming the insulator on the sidewalls of the gate metal, so even if the source region is formed thicker than the gate metal, it can still be in contact with the gate metal. There's nothing to do. Therefore, since fine control of the thickness of the source region is not required, a field effect transistor can be easily formed.

(Example) The details of the present invention will be explained according to examples.

FIG. 1 is a diagram showing a field effect transistor according to a first embodiment of the present invention. However, FIG. 1(a) is a plan view, and FIG. 1(b) is a sectional view taken along line A-A' of this plan view.

First, a non-doped GaAs buffer layer (12) and a non-doped AJ2G were formed on a semi-insulating GaAs substrate (11).
aAs potential barrier layer (13), n-type GaAs
Channel layers (2) are successively formed in layers by epitaxial growth. Here, "non-doped" means that no impurities are intentionally added, for example, 1 x 1015 pieces/ad.
is the impurity concentration. This n-type GaAs layer (2) J:
, a gate high resistivity semiconductor layer (43) of non-doped AjqGaAs, a gate electrode (4) having a structure in which a gate metal such as tungsten nitride (41) is laminated, and
N-type GaAs source/drain regions (6) and (7) are each formed by epitaxial growth. In this way, the source/drain regions (6) and (7) are formed in self-alignment with the gate electrode (4). Furthermore, the epitaxial layer can have a higher impurity concentration than the ion-implanted layer, making it suitable for lowering resistance. (32) is non-doped A
This is a non-doped AlGaAs layer formed from the same epitaxial layer as ρGaAsJW (43).

Further, on the source/drain regions (6) and (7), there are source/drain electrodes (8) having a two-layer structure of AuGe/Au from the bottom and exhibiting ohmic properties.

(9) is set. Furthermore, an insulating film, for example (1
02) and (103-) are connected to each other.

What is important here is that the lower sides of the source/drain regions (6) and (7), which have trapezoidal cross sections, do not contact the conductive gate metal (41) and have a high gate resistivity. The point is that it is formed so as to contact only the side wall of the semiconductor film (43) (the area surrounded by the broken line circle). As a result, there is no distance between the source/drain regions (6) and (7) from directly under the sidewall of the gate metal (41) in the gate length direction and vertical direction, so the series resistance between the source and gate can be kept low. can. Moreover, there must be A1 between the source electrode and the channel layer.
Unlike conventional field effect transistors in which a GaAs layer is interposed, in the field effect transistor of this embodiment, the source electrode is in direct contact with the n-type GaAs channel layer (2), so this point can be solved. Sauce from
This allows the series resistance between gate layers to be reduced. Therefore,
A field effect transistor in which the series resistance between the source and gate can be reduced by these methods can be made to have a large mutual conductance (gm), as seen from equation (A).

Furthermore, the Schottky gate breakdown voltage is greatly improved compared to the conventional method. This is because the conventional structure shown in Figure 5 is
Since the Schottky gate electrode (44) is in contact with the source/drain regions (46) and (47) (the part surrounded by the broken line of the circle), when a large negative voltage is applied to the gate electrode (44), these regions (46) ), (47) to the Schottky gate electrode (44), whereas in the field effect transistor of this embodiment, the gate metal (41) is connected to the source/drain regions (6), (7). This is because the structure is such that there is no direct contact, so this leakage is less likely to occur.

Furthermore, in a field effect transistor with such a structure, source/drain voltage? >(ill) and (9) are in direct contact with the n+ type GaAs source/drain regions (6) and (7) which have good ohmic contact with these, so like a conventional field effect transistor,
Compared to providing an ohmic electrode on AJGaAs, where it is difficult to form an ohmic contact, the resistance of the ohmic contact can be reduced.

In other words, while maintaining the gate electrode (4) structure in which metal is provided on the high resistivity semiconductor layer, it is possible to freely select materials for the source and drain regions that facilitate ohmic contact.

FIG. 2 is a cross-sectional view showing a field effect transistor according to a second embodiment of the present invention in the order of manufacturing steps.

First, a GaAs buffer layer (12) and a non-doped A [G
aAs layer (13), S L of 2×10[8ctn-3
a doped 100 nm thick n-type GaAs layer (2), and
Non-doped A1GaAs layer (3) as a high resistivity semiconductor
are sequentially laminated by, for example, the MBE method (FIG. 2(a)).

Next, a gate metal (41) of Schottky metal such as tungsten nitride is etched into a non-doped A1GaAs layer (41) by conventional reactive sputtering and dry etching.
3) Process and form on top (FIG. 2(b)).

Thereafter, an insulating film such as silicon oxide (51) is deposited over the entire surface, and a resist mask (52) with holes for source/drain formation regions is formed (FIG. 2(C)). Next, anisotropic etching is performed on this mask (52) until the non-doped A1GaAs layer (3) is exposed. This leaves the insulator (42) on the sidewalls of the gate metal (41) in the direction perpendicular to the gate length direction, and also forms a surface protective film (53).
form. After this, the mask (52) is removed (FIG. 2(d)).

Next, the non-doped A1GaAs layer (3) exposed on the surface is removed by J-etching using hydrogen peroxide and ammonia solution to expose the n-type GaAs layer (2) (FIG. 2(e)).

Further, on the exposed n-type GaAs layer (2), n”Ga
Source/drain regions (6), (7) made of AsWII
) is formed by selective epitaxial growth. At this time, the gate metal (41) and source/drain regions (6), (7
), since the insulator (42) is interposed between the source and drain regions (6).

(7) does not contact the gate metal (43) even if it becomes thicker than the gate high resistivity semiconductor film (43).

Therefore, here, the source/drain region (6).

Since there is no need for detailed control such as making the thickness of (7) thinner than the gate high resistivity semiconductor film (43), it is easy to form these regions (FIG. 2(f)).

Finally, A u G e / A u are stacked from the bottom and alloyed at 450°C to form source and drain electrodes (8) and (9) exhibiting ohmic properties to complete the field effect transistor. (Figure 2 (g)).

The field effect transistor formed in this way has a series resistance between the source and gate of 0.2Ω, and a gm of 600Ω.
It showed a high value of as/mm. For comparison, we fabricated a field effect transistor with the same size as the conventional structure shown in FIG. 5
It reached twice as much, and GM was also low. Further, like the previous embodiment, this field effect transistor also obtains effects such as material selectivity of the source/drain regions and high Schottky gate breakdown voltage.

Next, FIG. 3 shows a sectional view of a field effect transistor according to a third embodiment of the present invention. The same parts as in the previous second embodiment are indicated by the same reference numerals. The difference from the second implementation Te 1 is as follows:
Source/drain region (6).

(7) is made of a metal exhibiting ohmic properties instead of being formed of an n'' GaAs layer, and is deposited on the channel region (2) of direct-hole GaAs.

By forming the source/drain regions in this way,
This eliminates the step of forming the source/drain regions by epitaxial growth as in the previous example, which simplifies the manufacturing process, and also allows these regions to be used as gate electrodes (4) without being concerned with the thickness of the source/drain regions. ) and can be formed in self-alignment, increasing manufacturing reliability. Further, the source-drain electrodes (6), (7) are formed in self-alignment with the gate electrode (4), and in particular, the source-train region (6),
The distance to (7) is the insulator (41) interposed between this distance.
The series resistance between the source and drain is also reduced from this point of view.

The present invention is not limited to the above embodiments, but may be implemented as follows.

(1) In the above embodiment, tungsten nitride was used as the gate metal, but the gate metal is not limited to this, as long as the Schottky characteristics are maintained even after heat treatment of the alloy. For example, tungsten, tungsten silicide, tungsten and aluminum (W-AJ), molybdenum, M
oA42 or the like may also be used.

(2) Although n-type GaAs is used for the channel layer, other compound semiconductors with high electron mobility, such as indium gallium (InGaAs), may also be used.

(3) The potential barrier layer is non-doped ANGaA
A Peter junction was formed at the interface of the n-type GaAs channel layer using s, but any semiconductor layer that acts as a potential barrier may be used, for example, non-doped GaAs or p-type a.
It may be As, etc.

(4) Here, a buffer layer and a potential barrier layer were formed on a GaAs substrate, and then a channel layer was formed.
A channel layer may be formed directly on the GaAsg layer.

(5) In the above embodiments, a GaAs-based compound semiconductor was used as the base material, but the present invention is not limited to this, and other compound semiconductors may be used. For example, injunum phosphide (InP) may be used as the substrate. It can also be applied to field effect transistors using aluminum oxide (A 12203) for the gate high resistivity semiconductor film, aluminum for the gate metal, and AuGe for the source and drain electrodes.

(B) Although the case of an n-channel field effect transistor has been exclusively described here, the present invention may also be applied to a P-channel field effect transistor in which a P-type semiconductor is used for the channel layer.

It goes without saying that the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] The above configuration reduces the series resistance between the source and gate, improves gm, and is suitable for high-speed operation, as well as enabling the field effect to be selected from a wide range of materials for the source and drain regions to facilitate ohmic contact. A transistor can be easily formed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing a second embodiment of the invention, FIG. 3 is a diagram showing a third embodiment of the invention, and FIGS. 4 and 5 are diagrams showing a conventional example. 11...Semi-insulating GaAs substrate 12...Buffer layer 13 of non-doped GaAs...
・Non-dope Aj! GaAs potential barrier layer 2...n-type GaAs channel region 41...
Gate metal 42... Insulator 43... Gate high resistivity semiconductor film

Claims (10)

[Claims] (1) A gate electrode consisting of a channel layer exhibiting one conductivity type, a gate high specific resistance semiconductor film provided on this channel layer, and a gate metal provided in a laminated manner on this gate high specific resistance semiconductor film. , source and drain regions formed of epitaxial layers adjacent to the gate electrode and provided on the channel layer, respectively. (2) A channel layer exhibiting one conductivity type, a gate high resistivity semiconductor film formed on this channel layer, a gate metal formed on this gate high resistivity semiconductor/film, and a sidewall of this gate metal. A field effect transistor comprising a gate electrode made of an insulator, and source and drain regions adjacent to the gate electrode and on the channel layer. (3) The field effect transistor according to claim 1 or 2, wherein the gate high resistivity semiconductor film is made of a semiconductor of a different type from the channel layer and forms a heterojunction with the channel layer. (4) The field effect transistor according to claim 1 or 2, wherein the channel layer is formed on a semi-insulating substrate. (5) The field effect transistor according to claim 1 or 2, characterized in that a potential barrier semiconductor layer having a higher resistivity than the channel layer is provided below the channel layer. (6) The field effect transistor according to claim 1, wherein the source/drain region is made of an epitaxially grown layer of the same semiconductor as the channel region. (7) Claim 1, wherein the source/drain region is a metal that makes ohmic contact with the channel layer.
Field effect transistor as described. (8) The field effect transistor according to claim 1 or 2, wherein the channel layer is made of gallium arsenide, and the gate high resistivity semiconductor film is made of undoped aluminum gallium arsenide. (9) The field effect transistor according to claim 1 or 2, wherein the channel layer is made of indium gallium arsenide. (10) A step of forming a channel layer exhibiting one conductivity type on the high resistivity layer, a step of forming a high resistivity semiconductor film on the channel layer, and a step of forming a desired shape on the high resistivity semiconductor film. a step of forming a processed gate metal, a step of forming an insulator on the sidewalls of the gate metal, and a step of selecting the high resistivity semiconductor film from above the gate metal and the insulator until the channel layer is exposed. The gate metal, the insulator, and the gate high resistivity semiconductor film are removed by etching, and the high resistivity semiconductor film under the gate metal and the insulator is left as a gate high resistivity semiconductor film. forming a gate electrode having;
A field effect characterized by comprising the step of forming a source/drain region made of an epitaxial layer having the same conductivity type as the channel region and provided on the exposed surface of the channel layer in self-alignment with the gate electrode. Method of manufacturing transistors.