JPH025200U - - Google Patents

Info

Publication number
JPH025200U
JPH025200U JP7618688U JP7618688U JPH025200U JP H025200 U JPH025200 U JP H025200U JP 7618688 U JP7618688 U JP 7618688U JP 7618688 U JP7618688 U JP 7618688U JP H025200 U JPH025200 U JP H025200U
Authority
JP
Japan
Prior art keywords
insulating layer
bit line
word line
memory cell
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7618688U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7618688U priority Critical patent/JPH025200U/ja
Publication of JPH025200U publication Critical patent/JPH025200U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】
第1図は本考案の一実施例の要部であるメモリ
セル部を部分的に示す概略的平面図、第2図は第
1図の−′線に沿つた断面図、第3図は第1
図の−′線に沿つた断面図、第4図は第1図
例のメモリセル部及び読み出し回路部を示す回路
図である。 1……P型シリコン基板、2,2,2
…ワード線、3……SiO層、311,312
・・・333……SiO層部分、4,4
……ビツト線、511,512・・・533
……メモリセル。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板上に絶縁体層を挟んでワード線及び
    ビツト線を形成し、上記ワード線及び上記ビツト
    線が交差する部分に挟まれた絶縁体層部分をメモ
    リセルとして成るマスクROM。
JP7618688U 1988-06-08 1988-06-08 Pending JPH025200U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7618688U JPH025200U (ja) 1988-06-08 1988-06-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7618688U JPH025200U (ja) 1988-06-08 1988-06-08

Publications (1)

Publication Number Publication Date
JPH025200U true JPH025200U (ja) 1990-01-12

Family

ID=31301228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7618688U Pending JPH025200U (ja) 1988-06-08 1988-06-08

Country Status (1)

Country Link
JP (1) JPH025200U (ja)

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