JPH0250695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control angle α generation device for a thyristor that is calculated by a program, and more specifically, by generating a control angle α by hardware even when the execution of the program is stopped. This invention relates to a gate pulse generator for backup.

In conventional gate pulse generators of this type, when the program operation is stopped for some reason (hereinafter referred to as "software stop"), a gate pulse is generated following the control angle α. Therefore, (1) the gate pulse disappears or (2) the control angle α
becomes constant, resulting in damage to the thyristor converter, damage to the motor drive system, and further damage to the mechanical system.

First, a conventional gate pulse generator will be explained based on FIGS. 1 to 4. FIG. 1 shows the overall configuration of a conventional gate pulse generator. In the figure, a gate pulse generator 1 calculates a control angle α based on a program, and sequentially outputs the calculation result D〓. device 2 and the computing device 2
The calculation output D〓 is received from , and based on this, the zero point of the output of the synchronous power supply 5 is detected, and the output of the zero point detector 8, which outputs a zero point detection pulse, is used as a trigger signal to operate an internal counter and generate a gate pulse at a predetermined timing. A gate pulse generator 3 outputs P _G to a thyristor converter 4. Typical operating methods for the internal counter of the gate pulse generator 3 are (1) a countdown method and (2) a method in which a digital comparator is added to the counter. The former method presets a control angle α calculated by a program into a counter, starts counting in synchronization with the power supply, and generates a gate pulse when a certain value, for example, the count value reaches zero. The latter compares the count value of a counter that counts up in synchronization with the power supply with the calculated value of the control angle α, and generates a gate pulse when a match or inequality is established.

An example of the latter is JP-A-47-123709 "Phase control device"
is described in detail. Although the embodiments of the present invention will be explained using the former example, the present invention can be applied in substantially the same manner to the latter example, and the control angle calculation value α may be changed by hardware.

Now, FIG. 2 is a flowchart showing the operation of the gate pulse generator 1 shown in FIG. An angle α is calculated.

Furthermore, in the next step 24, it is determined whether the calculated value α of the control angle α satisfies α _nio < α < α _nax (α _nio and α _nax are the upper and lower limit values of the control angle α, respectively). .
If it is determined in step 24 that α _nio < α < α _nax , then in step 26 α = α is set, and in step 32 data D〓 (data indicating the calculated value α) is stored in the counter in the gate pulse generator 3. Set. If it is determined in step 24 that α<α _nio , then in step 28 it is determined that α=α _nio , and the process proceeds to step 32.

If it is determined in step 24 that α>α _nax , then in step 30 α=α _nax is set, and then the process moves to step 32, where the same processing is performed.

Furthermore, in step 34, the counter in the gate pulse generator is activated by the zero point detection pulse of the zero point detector 8, and performs a countdown operation by the clock pulse. When the contents of the counter reach zero, a gate pulse signal is output from the gate pulse generator 3 to the thyristor converter 4, and the next step is started.
Processing ends at 38.

Next, Fig. 3 shows the gate pulse generator 1 of Fig. 1.
The specific configuration of the gate pulse generator 3 that constitutes the is shown below. In the figure, the counter 40 receives data from the data input terminal D at the timing of a write pulse when data D (16 bits in parallel) is input to the load terminal L from the arithmetic unit 2 that calculates the control angle α based on a program.
is input and set. Next, zero point detector 8
is the zero point (α) of the power supply voltage (frequency _s ) of the synchronous power supply 5
= 0° timing), outputs a zero point detection pulse (count start command pulse) P _cs to the terminal CS of the counter 40, and outputs the count pulse (frequency _c ) from the reference oscillator 42 at the timing of this pulse P _cs . In response, the counter 40 starts counting down from the set value D〓. When the count content of the counter 40 reaches zero (the above set value is such that the time point when the count value of the counter reaches zero is α°), the one shot circuit 44 sends a signal to the thyristor conversion circuit (not shown). A gate pulse is output.

Here, the control angle α is given by the following equation.

α＝D〓× _s ／ _c ×360゜……(1) For example, count pulse _e is _e =1MHz, calculation data D〓 of control angle α is D〓=5000, power supply frequency _s of synchronous power supply 5 is _s =50Hz Then, the calculated value of the control angle α becomes α=90°.

The contents of the above operation are shown in the time chart of FIG. First, a count value _N1 corresponding to the calculation data D of the control angle α is set (D in the figure), and then the zero point detector 8 outputs a zero point detection pulse (B in the figure), and the counter 40 starts counting down. Then, when the count value of the counter 40 becomes zero (when the above equation (1) is satisfied), a gate pulse is outputted from the one-shot circuit 44 (FIG. 3C).
Also, the set value of the control angle α to the counter 40 is α>
When the value N ₂ is such that α _nax , the counter 40 counts down as shown in FIG _. One shot circuit 44
A gate pulse is output.

If the execution of the program is stopped due to a defect in the CPU hardware or software, (1) the thyristor firing pulse disappears (2) the output becomes constant, and (1) In case (2), if the thyristor is operating as an inverter, commutation failure will occur and damage the thyristor converter, and in case (2), the output voltage will remain constant, resulting in a dangerous situation such as runaway of the machine.

An object of the present invention is to provide a gate pulse generator that can safely operate or stop a thyristor converter even if generation of a control angle command becomes abnormal.

To achieve the above object, the present invention receives time data generated regarding the control angle of a thyristor, measures time using a reference pulse generated corresponding to a reference value of the control angle, and measures the measured time to match the time data. A main gate pulse generator that generates a gate pulse, a control angle command device that generates time data corresponding to the minimum and maximum values allowed as the control angle of the thyristor, and a control angle controller that measures time using the reference pulse. Generating a first backup gate pulse when the time coincides with the time data of the minimum value, and generating a second backup gate pulse when the measured time coincides with the time data of the maximum value; and a means for generating time data regarding the output pulse of the main gate pulse generator, the first backup gate pulse, and the control angle of the thyristor. a first gate means that outputs a gate pulse on the condition that the first gate means outputs a gate pulse; and a second gate means that outputs a gate pulse in response to at least one of the output pulse of the first gate means and the second backup gate pulse. , and a one-shot circuit that outputs a single gate pulse to the thyristor converter at a fixed time in response to the output pulse of the second gate means.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 5 is a block diagram showing the basic configuration of the gate pulse generator according to the present invention, which is characterized by being equipped with a backup gate pulse generator 52 constructed from hardware. During normal execution of the program, the digital gate pulse generator 50 operates under program control. When the execution becomes abnormal (an abnormality in the generated value of time data indicating the control angle), the switching circuit 54 switches to the backup gate pulse generator constituted by hardware to obtain the gate pulse output P _G corresponding to the control angle α. It will be done.

Next, FIG. 6 shows the operation of the gate pulse generator shown in FIG. 5. In this example, the control angle is α
= 60° to 70° and during normal operation, assume that for some reason the arithmetic unit that calculates the control angle α (means for generating time data specifying the control angle) stops (hardware stops). There is. In this case the control angle α
needs to be moved to the maximum value α _nax of the control angle α. As mentioned earlier, even if there is an abnormality, it is different if the load does not cause any problem even if the output is output at a constant control angle α, but normally the output of the thyristor converter must be reduced. It is. Furthermore, if the value of the control angle is incorrectly generated due to an abnormality in the execution of the program, various problems will occur. Therefore, it is necessary to transfer the control angle α to α _nax by backing up another hardware. The time chart in FIG. 6 shows an example of shifting to α _nax using a ramp function and an example of shifting to α nax using a step function.

FIG. 7 is a block diagram showing the configuration of the main parts of the gate pulse generator 52 according to the present invention which performs the operation shown in FIG. 6, and FIG. 8 shows the operation of the backup gate pulse generator 52 in FIG. This is a time chart to explain. In these figures, 70 is a counter as a main gate pulse generator that determines the output timing of gate pulses in a digital gate pulse generator whose control angle α is calculated by a program, and 52 is a backup gate configured by hardware. The gate pulse generator 52 is a pulse generator, and the gate pulse generator 52 outputs data of upper and lower limit values α _nax and α _nio of the control angle α, and a control angle command unit 80 that outputs data based on the data output from the control angle command unit 80. It consists of a counter 90 as a sub-gate pulse generator that determines the output timing of gate pulses. The data for the upper and lower limit values αmax and αmin of the control angle α takes into consideration the commutation overlap angle of the thyristor, and the data for the control angle α between 0° and αmin and between αmax and αmin.
It is set to a value that prevents the thyristor from being short-circuited due to commutation failure between 180° and 180°.

In response to a zero point detection pulse Pcs as a reference pulse generated corresponding to the reference value of the control angle, the counter 90 calculates α from the timing (α=α _MIN ) corresponding to the minimum value allowable as the control angle of the thyristor.
The first backup gate pulse Pα _nio is output until the timing when α = 180 _° , and the second It is designed to output a backup gate pulse Pα _nax . That is, in order to perform a counter operation in synchronization with the reference pulse, the counter 90 starts counting down and resets the count value in accordance with the zero point detection pulse Pcs. A switching circuit 54 and a one-shot circuit 110 are provided to output gate pulses to the thyristor converter only at timings corresponding to α=α _MIN to α=α _MAX .

The switching circuit 54 includes an AND gate 56 and an OR gate 58, with the AND gate 56 constituting first gate means and the OR gate 58 constituting second gate means.

In the above configuration, the counter 70 takes in the calculation data D〓 outputted from the calculation device (not shown) at the timing of the write pulse P _WR as described above, sets the data, and also outputs the data from the zero point detector (not shown). Zero point detection pulse output at the timing of α = 0° in the synchronous power supply output (Figure 8A)
P _cs starts counting down from the set value N (value corresponding to data D), and when the count reaches zero, a pulse signal P is output from terminal _C0 .

On the other hand, the counter 90 in the backup gate pulse generator 52 receives the zero point detection pulse P _cs
Data D〓 _nax , D〓 _nio indicating the upper and lower limit values α _nax , α _nio of the control angle α from the control angle command unit 80 at the time of falling of the control angle α
is taken in and set as data, and a down count is started (FIGS. 8B and 8C). When the count of the counter 90 reaches zero, pulse signals P〓 _nax and P〓 _nio are outputted from the terminals C ₁ and C ₂ .
That is, the counter 90 outputs a pulse signal P〓 _nax (terminal C ₁ ) that is at logic "1" level when the control angle α is within the range of α nax ≦α≦180°, and is at logic “1 _” level when the control angle α is within the range of α _nio ≦α≦180°. Two level pulse signals P〓 _nio (terminal C ₂ ) are output (D in the same figure).

Therefore, in the arithmetic unit of the digital gate pulse generator, the hardware is in a normal state and the software is being executed, but if there is an abnormality in the software such as an erroneous control angle value being generated, for example, as shown in FIG. As shown in F, even if a command such that α<α _nio is issued, the AND gate 56 outputs the output P of the counter 70, and the normal/abnormal signal 6 of the CPU in the arithmetic unit.
0 and the output _P〓nio of the counter 90, the gate pulse P _G is output from the one-shot circuit 110 only when α=α _nio . Here, the CPU normal/abnormal signal 60 becomes logic “0” as an abnormal signal only when the software stops.
It is assumed that a signal with a logic "1" level is output as a normal signal in other cases.

Incidentally, this normal/abnormal signal 60 is easily generated by a watchdog timer, an illegal address access signal, or the like.

Similarly, even if the software erroneously issues a command such that α>α _nax , the gate pulse P _G is output only when α=α _nax (G in the same figure).

On the other hand, when the program is running normally, a command is issued such that α _nio < α < α _nax ,
A gate pulse P _G as shown in FIG. 8E is output.

Furthermore, when the execution of the software is stopped due to an abnormality in the arithmetic unit and the generation of the control angle command is stopped, an abnormality signal 60 (logic "0" level) is output. In this case, the output P from the counter 70 is
is blocked by the AND gate 56, so the output _P〓nax of the counter 90 in the backup gate pulse generator 52 becomes valid in the OR gate 58. And it carries information about this control angle α _nax
P〓 _nax is controlled as shown in the timing chart shown in Fig. 6. In other words, when using a step function to shift α to α _nax at time T ₁ , the CPU
Counter 90 that simply satisfies α = α _nax in the event of an abnormality
It is sufficient to input the output P〓 _nax to the one-shot circuit 110. In addition, in order to shift the control angle α to α _nax in a ramp-like manner, the set value of the counter 90 is gradually changed to α _nax , <α _nax2 <...<α _naxo , using a counter provided in the control angle command device 80. It can be controlled by increasing the value to . Further, a counter for outputting such a command may be provided separately from the control angle command device 80. Note that after the first backup gate pulse Pα _nio is output, the second backup gate pulse is output.
Although it is possible to lower the first backup gate pulse Pα _nio at the time when Pα _nax occurs, if such a configuration is adopted, the gate pulse Pα _nax
It becomes necessary to provide a circuit for stopping the output of the gate pulse Pα _nio due to the output of the gate pulse Pα nio. Furthermore, even if the level of Pα _nio is “1” after α>α _MAX and the gate pulse is output from the AND gate 56,
Since only a single pulse in response to Pα _nax is output from the one-shot circuit 110, α=α _MIN to α=α _MAX can be changed without adopting the above-mentioned configuration.
A gate pulse can be generated only at the timing of .

As explained above, according to the present invention, even if a control angle command is generated by mistake, it is possible to output a gate pulse at a timing that is within the allowable value of the control angle, and the control angle command can be generated. When stopped, the gate pulse can be output at the timing corresponding to the maximum value of the control angle, so
Even if the control angle command becomes abnormal, the thyristor converter can be operated or stopped safely.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall configuration of a conventional gate pulse generator, Fig. 2 is a flowchart showing the operation of the gate pulse generator shown in Fig. 1, and Fig. 3 is the same as that shown in Fig. 1. A block diagram showing the specific configuration of the gate pulse generator constituting the gate pulse generator, FIG. 4 A to E are time charts for explaining the operation of the gate pulse generator shown in FIG. 3, and FIG. 5. 6 is a block diagram showing the basic configuration of the gate pulse generator according to the present invention, FIG. 6 is a time chart showing the operation of the gate pulse generator shown in FIG. 5, and FIG. FIGS. 8A to 8G, which are block diagrams showing a specific configuration of essential parts of the pulse generator, are time charts for explaining the operation of the backup gate pulse generator shown in FIG. 7. 50...Digital gate pulse generator, 5
2...Backup gate pulse generator, 54...
...Switching circuit, 110...One shot circuit.

Claims (1)

[Claims] 1 Main gate pulse generation that receives time data generated regarding the control angle of the thyristor, measures time using a reference pulse generated corresponding to the reference value of the control angle, and generates a gate pulse when this measured time matches the time data. a control angle command device that generates time data corresponding to the minimum and maximum values allowable as the control angle of the thyristor, and a control angle command device that measures time using the reference pulse and that the measured time coincides with the time data of the minimum value. a sub-gate pulse generator that generates a first backup gate pulse when the measured time coincides with the maximum value time data; and the first backup gate pulse and a normal signal indicating a normal state of the means for generating time data regarding the control angle of the thyristor, and output a gate pulse on the condition that all these signals are input. a gate means; a second gate means for outputting a gate pulse in response to at least one of the output pulse of the first gate means and the second backup gate pulse; A gate pulse generator having a one-shot circuit that outputs a single gate pulse to a thyristor converter at a fixed time.