JP2000114936A - Digital triangular wave form generation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove mutual interference between devices by switching the operation of a count-up operation with the matching signal of a first digital comparator to a count-down operation with the matching signal of a second digital comparator, generating a synchronous control signal with the matching signals of the both comparators and controlling the operation of an up/down counter with a synchronous control signal inputted from outside. SOLUTION: A digital triangular wave form generating device is provided with an up/down counter 70 which counts a source clock 80 and can change over a count-up operation and a count-down operation by a count direction switch signal 81 and a first register 71. The first register 71 can be rewritten by a micro computer and holes the maximum value of count-up. The digital triangular wave form generation device is provided with a first digital comparator 72. The first digital comparator 72 detects that the content of the up/down counter 70 is matched with '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital triangular waveform generator for a three-phase motor PWM controller in an AC servo controller or the like.

[0002]

2. Description of the Related Art In recent years, digitalization of motor control devices such as AC servo controllers has been advanced, and accordingly, a triangular waveform generator used for generating a PWM waveform in a PWM control device of a three-phase motor also supports digitalization. Means have been devised to do so.

FIG. 9 shows a typical example of a conventional digital triangular waveform generator. Hereinafter, the configuration will be described with reference to FIG.

As shown in FIG. 9, an up / down counter 70 capable of counting a source clock 80 and switching between a count-up operation and a count-down operation by a count direction switching signal 81, and a maximum value of count-up by a register rewritable by a microcomputer. Register 7 that holds
1 and a first digital comparator 72 for detecting that the content of the up / down counter 70 matches "0".
A second digital comparator 73 for detecting that the content of the up / down counter 70 matches the content of the first register 71; and a count direction switching signal 81 counting up by a match signal 83 of the first digital comparator 72. The count direction switching means 74 which switches to the countdown operation by the coincidence signal 84 of the second digital comparator 73; the coincidence signal 83 of the first digital comparator 72 and the coincidence signal 84 of the second digital comparator 73; OR element 7 that outputs the logical sum of
5 is comprised.

FIG. 10 is a diagram showing an outline of the operation shown in FIG. 9, in which the count direction switching signal 81 changes according to the output 83 of the first digital comparator 72 and the output 84 of the second digital comparator 73, and From the first register value to the first register value.

FIG. 11 shows an example of a configuration in which the digital triangular waveform generator shown in FIG. 9 is used for motor control of a three-phase motor. The control processing means 90 processes commands and feedback information for controlling the motor, A microcomputer 91 for calculating information from the processing means 90; a digital triangular waveform generator 92 having the configuration shown in FIG. 9; a three-phase PWM signal generating means 93; a switching means 94 for supplying power to a motor 96; It comprises current detection means 95 for detecting the current supplied to 96.

FIG. 12 shows an example of operation waveforms in FIG. 11, in which U command 101, V command 102, and W command 103 are commands input to the three-phase PWM signal generation means, COMPU, C
OMPV and COMPW are the U command 101, V command 10
2. W command 103 and digital triangular waveform generator 92
A waveform which is digitally compared in magnitude with the output 82 and becomes "H" when the command is larger or equal to the count data, and becomes "L" when the command is smaller than the count data, PWM
U104, PWMV105 and PWMW106 are the CO
Waveform obtained by adding a delay Td of a fixed time to the falling change of MPU, COMPV, COMPW, * PWMU1
07, * PWMV108 and * PWMW109 are the CO
This is a waveform obtained by logically inverting MPU, COMPV, and COMPW, and adding a delay Td of a fixed time to the fall of this signal.

At the signal detection timing 85, the vertex of the count data 82, that is, the value of the count data 82 is "0".
This signal is output when the value matches the value held by the register 71.
5, PWMW106 and * PWMU107, * PWM
V108 and * PWMW109 basically have a timing relationship in which signals do not overlap with signal changes.

In the feedback control of the three-phase motor, first, analog or digital information necessary for position, speed or current control is controlled by a signal detection timing 85 output from the digital triangular waveform generator 92 shown in FIG. 90, and a three-phase PWM based on an operation by the microcomputer 91 to supply power to the motor.
PWM command input to signal generating means 93 U command 10
1, a V command 102 and a W command 103, and a U command 10
1, V command 102, W command 103, and count data 82 output from the digital triangular waveform generator 92, PWM signals 104, PWMV1 and PWMV1 are output.
05, PWMW106 and * PWMU107, * PW
MV 108 and * PWMW 109 are generated, and power is supplied to the three-phase motor via switching means 94 for supplying power to the motor 96 based on this signal.
Thereafter, every time the signal detection timing 85 is output, control command information and feedback information are fetched and the above is repeated.

As described above, the signal detection timing 85 and P
PWMM104, PWMV105, PWM which are WM signals
MW106 and * PWMU107, * PWMV10
8, * The signal changes of the PWM 109 basically have a timing relationship in which the signals do not overlap. Therefore, the control processing means 90 for detecting various control signals is not affected by electric noise generated from the switching means 94 based on the PWM signal. Is considered.

[0011]

However, in the above-mentioned conventional configuration, the control processing means 90 for detecting various control signals in the range in which the control device of the electric motor is constituted by a single unit is PWM.
Although the configuration is such that it is not affected by the electrical noise generated from the switching means 94 based on the signal, if a plurality of control devices are configured, the control processing means 90 of another control device and the PWM signal of another control device, That is, since the timing relationship with the electrical noise generated from the switching means 94 is irrelevant, the electrical noise may be affected. In particular, in the case of the conversion processing from an analog voltage to a digital voltage, Noise may be erroneously detected and converted from analog to digital, resulting in malfunction of the motor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital triangular waveform generator and a digital triangular waveform generating system which do not cause mutual interference even when a plurality of devices are used simultaneously.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention counts a source clock oscillating at a constant frequency, and is capable of switching between a count-up operation and a count-down operation by a count direction switching signal and a count clear. An up / down counter capable of clearing the count content to 0 by a signal, a first register holding a maximum count-up value in a rewritable data register, and an up / down counter for checking that the content of the up / down counter matches 0. A first digital comparator for detecting, a second digital comparator for detecting that the content of the up / down counter matches the first register, and a coincidence signal of the first digital comparator for the count direction switching signal. In the count-up operation and the second
Counting direction switching means for switching to a countdown operation in accordance with the coincidence signal of the digital comparator, host processing means for generating a synchronization control signal from the coincidence signal of the first digital comparator and the coincidence signal of the second digital comparator, It is provided with slave processing means for controlling the operation of the up / down counter by a synchronization control signal input from the outside.

By the above means, even when a plurality of motor control devices are used, the timing of the triangular waveform in the digital triangular waveform generator can be synchronized between the plurality of devices, and the same use environment as that of a single device can be realized. it can.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the above-mentioned problems, the present invention counts a source clock oscillating at a fixed frequency, and can switch a count-up operation and a count-down operation by a count direction switching signal and a count clear signal by a count clear signal. An up / down counter capable of clearing the count to 0, a first register for holding a maximum count-up value in a rewritable data register, and a first register for detecting that the content of the up / down counter matches 0. 1
A digital comparator, a second digital comparator for detecting that the contents of the up / down counter match the contents of the first register, and counting up the count direction switching signal by a match signal of the first digital comparator. A counting direction switching means for switching to a countdown operation in response to the coincidence signal of the second digital comparator; and a synchronization control signal based on the coincidence signal of the first digital comparator and the coincidence signal of the second digital comparator. This is a digital triangular waveform generator having a host processing means for generating.

Further, the present invention is a digital triangular waveform generator having a host processing means for outputting either the coincidence signal of the first digital comparator or the coincidence signal of the second digital comparator as a synchronization control output signal.

Further, a second register for holding a match signal output selection value in a data rewritable register and a match signal of the first digital comparator or a match signal of the second digital comparator by the second register. A digital triangular waveform generator including a host processing means comprising a first selector for outputting one of them as a synchronization control output signal.

An up-down counter which counts a source clock oscillating at a constant frequency and can switch between a count-up operation and a count-down operation with a count direction switching signal and can clear the count content to 0 with a count clear signal; A first register for holding a maximum count-up value in a data rewritable register, a first digital comparator for detecting that the content of the up / down counter matches 0, and a content of the up / down counter. A second digital comparator for detecting a match with the first register;
Count direction switching means for switching the count direction switching signal to a count-up operation by a coincidence signal of the first digital comparator and a count-down operation by a coincidence signal of the second digital comparator;
The digital triangular waveform generator includes slave processing means for controlling the operation of the up / down counter by a synchronization control signal input from the outside.

The contents of the up / down counter are cleared to 0 by the match signal of the first digital comparator, and after the clear state is maintained for a certain period of time, the up / down counter is restarted or the first digital comparator matches. While the clear state of the up / down counter is being held by the signal, the up / down counter is restarted by the synchronization control signal input from the outside, or the content of the up / down counter is up to the set value and the synchronization control signal is input from the outside. This is a digital triangular waveform generator including slave processing means for performing one of the operations of the up-down counter after clearing the contents of the down counter to zero.

A third register for holding an input valid / invalid threshold value of a synchronization control input signal externally input by a rewritable data register; And a third digital comparator for detecting the coincidence with the signal, and when the up / down counter holds the "H" level by the coincidence signal of the third digital comparator during the countdown operation, and after the contents of the up / down counter are cleared to 0 When the counting operation is started, the first data holding means for holding the “L” level and the synchronization control input signal input from the outside during the period when the output of the first data holding means is the “H” level are “L”. From "H" to "H", the second data holding the "L" level temporarily to make the contents of the up / down counter zero. Holding means, a rewritable data register for holding a count stop count, a fourth register for counting a source clock oscillating at a constant frequency, and counting down by a count-down operation and a data preset signal. , A fourth digital comparator for detecting that the content of the presettable down counter is equal to 0, and a signal from “H” by a coincidence signal of the first digital comparator. It changes to and keeps at “L”, counts the number of source clocks by the presettable down counter by the number of stoppages of the count operation held in the fourth register, and changes the “H” level by the coincidence signal of the fourth digital comparator. A third data holding means for holding, and a second data holding means. The up-down counter the output of the output and the third data holding means data holding means is a digital triangle wave waveform generator having a slave processing means comprising clear signal generating means for outputting a count clear signal to zero.

The host processing means for generating a synchronization control signal from the coincidence signal of the first digital comparator and the coincidence signal of the second digital comparator, and the operation of the up / down counter is controlled by a synchronization control signal input from the outside. A digital triangular waveform generator and a digital triangular waveform in which a plurality of other slave processing units are connected in parallel to one host processing unit when a plurality of digital triangular waveform generators each having a slave processing unit for controlling are used. It is a generation system.

Further, a host processing means for generating a synchronization control signal from the coincidence signal of the first digital comparator and the coincidence signal of the second digital comparator, and the operation of the up / down counter is controlled by a synchronization control signal inputted from outside. When a plurality of digital triangular waveform generators each having a slave processing means for controlling are used at the same time, one host processing means is connected to another slave processing means and is paired with this slave processing means. A digital triangular waveform generator and a digital triangular waveform generating system in which the digital triangular waveform generator is connected in series so as to connect a host processing unit and one other slave processing unit.

As described above, the synchronization control signal can be obtained from the digital triangular waveform. Further, two types of synchronization control signals can be obtained from the digital triangular waveform.

Further, one of two types of synchronization control signals can be selected and output from the digital triangular wave waveform.

Also, a digital triangular waveform can be generated by a synchronization control signal input from the outside.

Also, the generation of the digital triangular wave is temporarily stopped when the triangular wave counter is set to "0" and the waveform is regenerated after a certain period of time, or the generation of the digital triangular wave is temporarily stopped when the triangular wave counter is set to "0". It is possible to regenerate a digital triangular waveform by the input synchronization control signal, or to regenerate the digital triangular waveform after setting the value of the triangular wave counter to “0” by the synchronization control signal input from the outside during the generation of the digital triangular wave. it can.

Further, after the value of the triangular wave counter is set to "0" by the synchronous control signal input from the outside during the generation of the digital triangular wave, the setting of the effective input range of the synchronous control signal when the digital triangular waveform is regenerated and The generation of the digital triangular wave is temporarily stopped when the triangular wave counter is set to the value "0", and the stop time when the waveform is regenerated after a certain period of time can be set.

Further, by connecting the digital triangular waveform generators in parallel, it is possible to simultaneously synchronize the timing of generating the triangular waveform among a plurality of digital triangular waveform generators.

Further, by connecting the digital triangular waveform generators in series, synchronization can be achieved while shifting the triangular waveform generation timing among a plurality.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a digital triangular waveform generator according to an embodiment of the present invention.

As shown in FIG. 1, an up / down counter 70 which counts a source clock 80 and can switch between a count up operation and a count down operation by a count direction switching signal 81, and a maximum value of count up by a register which can be rewritten by a microcomputer. Register 7 that holds
1 and a first digital comparator 72 for detecting that the content of the up / down counter 70 matches "0".
A second digital comparator 73 for detecting that the content of the up / down counter 70 matches the content of the first register 71; and a count direction switching signal 81 counting up by a match signal 83 of the first digital comparator 72. The count direction switching means 74 which switches to the countdown operation by the coincidence signal 84 of the second digital comparator 73; the coincidence signal 83 of the first digital comparator 72 and the coincidence signal 84 of the second digital comparator 73; OR element 7 that outputs the logical sum of
5, a coincidence signal 83 of the first digital comparator 72 having a register
A host processing means 1 for outputting a synchronization control output signal 11 from a coincidence signal 84 of the digital comparator 73, a synchronization control input signal 12 having a register which can be rewritten by a microcomputer, and a count direction switching signal 8
1 and the coincidence signal 83 of the first digital comparator 72
And the slave processing means 2 for outputting a count clear signal 13 for clearing the up / down counter 70 from the count data 82 of the up / down counter 70.

The host processing means 1 and the slave processing means 2 will be described below with reference to FIGS.

FIG. 2 is a diagram showing the configuration of the host processing means 1 in FIG. 1. A coincidence signal 83 of the first digital comparator 72 and a coincidence signal 84 of the second digital comparator 73 are switched by a register rewritable by a microcomputer. It comprises a second register 21 for holding the setting, and a first selector 22 for switching between a coincidence signal 83 of the first digital comparator 72 and a coincidence signal 84 of the second digital comparator 73 and outputting the synchronization control output signal 11. ing.

FIG. 3 is a diagram showing the configuration of the slave processing means 2 shown in FIG.
A third register 23 for holding an invalid threshold value, and a third digital comparator 2 for detecting that the content 82 of the up / down counter matches the third register.
4, when the up / down counter counts down by the count direction switching signal 81, the "H" level is held by the coincidence signal 41 of the third digital comparator, and the count operation is started after the contents of the up / down counter are cleared to 0. And the first data holding means 25 holding the "L" level, and the synchronous control input signal 12 inputted from the outside during the period when the output 42 of the first data holding means is at the "H" level. When it changes to "H", the content of the up / down counter is temporarily set to "L" to make it 0.
A second data holding means 26 for holding the level, a fourth register 28 for holding the number of stoppages of the count operation by a rewritable data register, and a countdown operation by counting a source clock 80 oscillating at a constant frequency. A presettable down counter 29 capable of presetting the content of the counter to the value of the fourth register by a data preset signal 44, and a fourth digital comparator 30 for detecting that the content 45 of the presettable down counter matches 0. Is changed from "H" to "L" by the coincidence signal 83 of the first digital comparator, and is held, and the source clock 80 is reset to the presettable down counter 29 by the number of stoppages of the count operation held in the fourth register 28. And the fourth digital comparator In order to set the up / down counter to 0 based on the third data holding means 27 holding the "H" level by the coincidence signal 46 of 30 and the output 43 of the second data holding means and the output 44 of the third data holding means. And a clear signal generating means 31 for outputting the count clear signal 13.

Next, the operations of the host processing means 1 and the slave processing means 2 will be described with reference to FIGS. 4, 5, 6, and 7.

FIG. 4 is a diagram showing the operation of the host processing means 1 and the relationship with the slave processing means 2, and is an operation example using two digital triangular waveform generators X and Y. X is the host side and Y is the slave side. On the X side, the content 82 of the up / down counter is 0 or the point of the maximum value, that is, the coincidence signal 83 of the first digital comparator 72 and the coincidence signal 84 of the second digital comparator 73. Is output by selecting the first selector 22 according to the setting held in the second register, and when the coincidence signal 83 of the first digital comparator 72 is selected.
(A) When the signal is output and the coincidence signal 84 of the second digital comparator 73 is selected, the 11 (b) signal is output.

On the other hand, on the Y side, the 11 (a) signal or 11 (b) signal output as the synchronization control output signal is used as the 12 (a) signal or 12
(B) Received as a signal, and when the 12 (a) signal is a synchronization control input signal via the slave processing means 2, the digital triangular wave waveform generation shown in the slave (a) is generated as shown in 12 (b).
When the signal is a synchronous control input signal, a digital triangular waveform shown in slave (b) is generated. In this way, the generation and synchronization of digital triangular waveforms are performed among a plurality.

Next, the operation of the slave processing means 2 will be described. FIG. 5 is an operation diagram when the synchronization control input signal 12 is not input at all or is not input within the input valid range in the slave processing means 2 of FIG. 3. In this case, the count data 82 of the up / down counter 70 becomes 0. This is an embodiment in which this state is held at a point in time and the counting operation is restarted again after the elapse of the waiting time held in the fourth register 28.

First, the third digital comparator 24
Detects the coincidence between the threshold value held in the third register 23 and the count data 82 of the up / down counter and outputs a coincidence signal 41. When the count direction switching signal 81 is at the "H" level, that is, at the time of the countdown operation, According to the coincidence signal 41, the synchronization control input signal is set to be valid and the first
Is held at the "H" level. When the counting operation is started after the content of the up / down counter becomes 0, the held “H” level is held at the “L” level, and thereafter, even if a synchronization control input signal is input, it is treated as invalid.

Next, in the second data holding means 26, since the synchronization control input signal 12 is not input even though the signal 42 indicating the validity of the synchronization control input is "H", the second data holding means 26 outputs “H” is held as 43.

Next, when the content of the up / down counter becomes 0, the coincidence signal 83 of the first digital comparator 72 is output.
Becomes "H", and this signal causes the output 44 of the third data holding means 27 to change from "H" to "L". At the same time, the presettable down counter 29 outputs the value held in the fourth register to the data. The operation is switched from the preset operation to the operation of counting the source clock 80.

At the same time, the clear signal generating means 31
From the output 43 of the data holding means 26 and the output 44 of the third data holding means 27, "L" is output as the count clear signal 13 of the up / down counter 70 to bring it into the clear state.

Next, when the count data 45 of the presettable down counter 29 becomes 0 and the fourth digital comparator detects a coincidence signal 46, the output 44 of the third data holding means 27 changes from "L" to "H". Then, the presettable down counter 29 switches from the count operation to the data preset operation.

At the same time, the clear signal generating means 31
From the output 43 of the data holding means 26 and the output 44 of the third data holding means 27, "H" is output as the count clear signal 13 of the up / down counter 70, and a count state is set.

In this way, when the externally input synchronous control input signal is not input, the content of the up / down counter is cleared to 0 by the coincidence signal of the first digital comparator, and after the clear state is held for a certain period, The digital triangular waveform is generated by re-operation of the up / down counter.

FIG. 6 is an operation diagram when the synchronous control input signal 12 is input while the up / down counter is kept clear in the slave processing means 2 of FIG. 3. In this case, the up / down counter 70 sets the count data 82 to 0. This is an embodiment in which this state is held at the point in time when the count operation is resumed, and the count operation is restarted by the synchronization control input signal.

First, in the same manner as in the operation of FIG. 5, the synchronous control input signal is validated by the third digital comparator 24, the third register 23, the count data 82 of the up / down counter, and the count direction switching signal 81 to make the first signal valid. Is held at the "H" level. Here, in the second data holding means 26, the synchronization control input signal 12 is not input even though the signal 42 indicating the validity of the synchronization control input is "H". “H” is held.

Next, when the content of the up / down counter becomes 0, the coincidence signal 83 of the first digital comparator 72 is output.
Becomes "H", and this signal causes the output 44 of the third data holding means 27 to change from "H" to "L". At the same time, the presettable down counter 29 outputs the value held in the fourth register to the data. The operation is switched from the preset operation to the operation of counting the source clock 80.

At the same time, the clear signal generating means 31
From the output 43 of the data holding means 26 and the output 44 of the third data holding means 27, "L" is output as the count clear signal 13 of the up / down counter 70 to bring it into the clear state.

Next, before the output 45 of the presettable down counter 29 becomes 0, the synchronous control input signal 12
Changes from "L" to "H", the second data holding means 26 temporarily holds the "L" level to set the contents of the up / down counter 70 to 0. At this time, the clear signal generating means 31 outputs the output 4 of the second data holding means 26.
From the third and the output 44 of the third data holding means 27, "H" is output as the count clear signal 13 to switch the operation of the up / down counter 70 from the holding of 0 to the counting operation, and the counting state is set.

In this way, the up / down counter is set to 0
When the synchronous control input signal is input from outside while the signal is held, the digital triangular wave waveform is generated by restarting the up / down counter when the synchronous control input signal is input.

FIG. 7 is an operation diagram in the case where the synchronization control input signal 12 is input within the effective input range of the synchronization control input signal in which the contents of the up / down counter 70 are held in the register in the slave processing means 2 of FIG. In this case, in this embodiment, the up / down counter 70 is cleared once when the synchronization control input signal is received, and the counting operation is restarted again.

First, in the same manner as in the operation of FIG. 5, the third digital comparator 24, the third register 23, the count data 82 of the up / down counter and the count direction switching signal 81 make the synchronous control input signal valid and the first Is held at the "H" level.

Next, if the synchronization control input signal 12 changes from "L" to "H" from outside before the content of the up / down counter becomes 0, the second data holding means 26 updates the content of the up / down counter 70. The level is temporarily held at "L" level to make it 0.

At this time, the clear signal generating means 31 temporarily outputs "L" as the count clear signal 13 of the up / down counter 70 from the output 43 of the second data holding means 26 and the output 44 of the third data holding means 27. After clearing the counter once, the counting operation is restarted.

When the synchronization control input signal is input within the effective input range of the synchronization control input signal in which the contents of the up / down counter are held in the register, the up / down counter is received when the synchronization control input signal is received. Is cleared once, the counting operation is restarted again, and a digital triangular waveform is generated.

FIG. 8 is a diagram showing a configuration of an embodiment in which a plurality of digital triangular waveform generators 60 according to the present invention are used as a control device 61 of a three-phase motor and are connected.

FIG. 8 (a) shows one digital triangular waveform generator 60 as a host and outputs a synchronous control output signal 11, and all the others are slaves and outputs a synchronous control output signal 11 from the host as a synchronous control input. This is an embodiment of the parallel connection used as the signal 12, and the digital triangular waveform generation is a system that performs generation synchronization at the same timing with reference to the host side.

FIG. 8B shows an embodiment in which a series connection is made with respect to FIG. 8A. In the digital triangular waveform generation, the timing is shifted little by little with respect to the digital triangular waveform generator located at the top. This is a system that performs generation synchronization.

[0061]

As is apparent from the above embodiment, according to the present invention, even when a plurality of motor control devices are used, the timing of the triangular waveform in the digital triangular waveform generator can be synchronized between the plurality of devices. The control processing means for detecting various control signals of analog information and digital information can realize signal detection which is not affected by mutual interference with electric noise generated from the switching means based on the PWM signal, and generates a digital triangular waveform. The reliability of the motor control device using the device can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital triangular waveform generator according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a host processing unit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a slave processing unit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of the operation of the host processing means according to the embodiment of the present invention;

FIG. 5 is an explanatory diagram of the operation of the slave processing means according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram of the operation of the slave processing means according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram of the operation of the slave processing means according to the embodiment of the present invention.

FIG. 8 is a connection configuration diagram of a digital triangular waveform generator according to an embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional digital triangular waveform generator.

FIG. 10 is a diagram illustrating the operation of a conventional digital triangular waveform generator.

FIG. 11 is a configuration diagram of a general three-phase motor control device.

FIG. 12 is a diagram illustrating the operation of a general three-phase motor control device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 host processing means 2 slave processing means 21 second register 22 first selector 23 third register 24 third digital comparator 25 first data holding means 26 second data holding means 27 third data holding means 28 fourth register 29 presettable down counter 30 fourth digital comparator 31 clear signal generation means 70 up / down counter 71 first register 72 first digital comparator 73 second digital comparator 74 count direction switching means 75 OR element Reference Signs List 90 control processing means 91 microcomputer 92 digital triangular waveform generator 93 three-phase PWM signal generation means 94 switching means 95 current detection means 96 three-phase motor

Continuation of front page (72) Inventor Yoshinori Isomura 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5H576 AA17 BB06 DD02 EE14 EE30 JJ03 JJ11 JJ12 JJ13 JJ17 JJ29

Claims (8)

[Claims] An up / down counter which counts a source clock oscillating at a constant frequency and can switch between a count-up operation and a count-down operation with a count direction switching signal and can clear the count content to 0 with a count clear signal; A first register for holding a maximum count-up value in a data rewritable register, a first digital comparator for detecting that the content of the up / down counter matches 0, and a content of the up / down counter. A second digital comparator for detecting coincidence with the first register; a count-up switching signal for a count-up operation by a coincidence signal of the first digital comparator;
Counting direction switching means for switching to a countdown operation in accordance with the coincidence signal of the digital comparator, and host processing means for generating a synchronization control signal from the coincidence signal of the first digital comparator and the coincidence signal of the second digital comparator. Digital triangular waveform generator. 2. The digital triangular waveform generator according to claim 1, further comprising a host processing means for outputting one of a coincidence signal of the first digital comparator and a coincidence signal of the second digital comparator as a synchronization control output signal. . 3. A match register of a first digital comparator or a match signal of a second digital comparator according to a second register for holding a match signal output selection value in a register whose data is rewritable, and the second register. 3. The digital triangular waveform generator according to claim 1, further comprising a host processing means comprising a first selector for outputting either one of them as a synchronization control output signal. 4. An up / down counter which counts a source clock oscillating at a constant frequency and can switch between a count-up operation and a count-down operation by a count direction switching signal and can clear the count content to 0 by a count clear signal. A first register for holding a maximum count-up value in a data rewritable register, a first digital comparator for detecting that the content of the up / down counter matches 0, and a content of the up / down counter. A second digital comparator for detecting coincidence with the first register; a count-up switching signal for a count-up operation by a coincidence signal of the first digital comparator;
A digital triangular waveform generator comprising: a counting direction switching means for switching to a countdown operation in response to a coincidence signal of the digital comparator; and a slave processing means for controlling the operation of the up / down counter by a synchronization control signal input from the outside. 5. The content of the up / down counter is cleared to 0 by a coincidence signal of the first digital comparator, and after the clear state is maintained for a certain period of time, the up / down counter is restarted or the first digital comparator coincides. While the clear state of the up / down counter is being held by the signal, the up / down counter is restarted by the synchronization control signal input from the outside, or the content of the up / down counter is up to the set value and it is up by the synchronization control signal input from the outside. 5. The digital triangular waveform generator according to claim 4, further comprising slave processing means for performing one of the operations of the up / down counter after clearing the contents of the down counter to zero. 6. A third register for holding a threshold value of validity / invalidity of a synchronization control input signal inputted from the outside, which is a rewritable data register, and the contents of an up / down counter are stored in the third register. And a third digital comparator for detecting the coincidence with the signal, and when the up / down counter holds the "H" level by the coincidence signal of the third digital comparator during the countdown operation, and after the contents of the up / down counter are cleared to 0 When the counting operation is started, the first data holding means for holding the “L” level and the synchronization control input signal input from the outside during the period when the output of the first data holding means is the “H” level are “L”. When the data is changed from "H" to "H", the second data holding means for temporarily holding "L" level to make the contents of the up / down counter zero. And a fourth register for holding the number of stoppages of the count operation by a register whose data is rewritable; a source clock oscillating at a constant frequency; A presettable down counter that can be preset to a register value, a fourth digital comparator that detects that the content of the presettable down counter matches 0, and “H” to “H” by a match signal of the first digital comparator. It changes to L and holds it, counts the number of source clocks by the presettable down counter for the number of stoppages of the count operation held in the fourth register, and holds "H" level by the coincidence signal of the fourth digital comparator. A third data holding means for storing 6. The digital processing device according to claim 4, further comprising slave processing means comprising clear signal generating means for outputting a count clear signal for setting an up / down counter to 0 based on the output of the means and the output of the third data holding means. Triangular waveform generator. 7. A host processing means for generating a synchronization control signal from a coincidence signal of the first digital comparator and a coincidence signal of the second digital comparator, and the operation of the up / down counter is controlled by a synchronization control signal input from the outside. 5. When using a plurality of digital triangular waveform generators each having a slave processing means for controlling, a plurality of other slave processing means are connected in parallel to one host processing means. , One of 5 and 6
The digital triangular waveform generator and the digital triangular waveform generator according to the above paragraph. 8. A host processing means for generating a synchronization control signal from a coincidence signal of the first digital comparator and a coincidence signal of the second digital comparator, and the operation of the up / down counter is controlled by a synchronization control signal input from the outside. When a plurality of digital triangular waveform generators each having a slave processing means for controlling are used at the same time, one host processing means is connected to another slave processing means and is paired with this slave processing means. The digital triangular waveform generator according to any one of claims 1, 2, 3, 4, 5, and 6, wherein the digital triangular waveform generator is connected in series so as to connect a host processing unit and one other slave processing unit. Triangular waveform generator and digital triangular waveform generator.