JP2002238264A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device capable of reducing system cost by using common wiring at a DC part of any of inverter units. SOLUTION: This inverter device 1 is constituted of a master inverter unit 5 and a slave inverter unit 5a. A gate signal generated at a master control substrate 13 is supplied to a slave control substrate 14 through an approach route side cable 21 to control main switching devices of the master inverter unit 5 and the slave inverter unit 5a by the common gate signal. The DC input sides of the master inverter unit 5 and slave inverter unit 5a are arranged in parallel to be connected to PV power source (DC power supply consisting of a solar panel) 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device in which a plurality of inverter units can operate in cooperation with each other, and more particularly to a system in which electric power generated by solar power is returned to a commercial power system and used. To a suitable inverter device.

[0002]

2. Description of the Related Art In recent years, photovoltaic power generation has attracted attention as clean energy and has been widely put to practical use. In this case, as long as a solar cell can be installed, power can be generated according to its area. Is an advantage. Therefore, conventionally, a method has been adopted in which solar cell panels are standardized into unit panels, and an arbitrary number of unit panels are grouped and installed according to the installation location, thereby easily expanding the applicable range. Can be achieved.

In such a photovoltaic power generation system, the power generated by the solar cell is temporarily supplied to a system power supply (commercial power system) except for a special case such as a small-scale system.
The method of supplying electricity to the customer by flowing it back to the grid and using the power flow of the system is a common use form from the viewpoint of stable power supply.In this case, the DC power generated by the solar cell is used. A device that converts AC power is indispensable.

Therefore, conventionally, a method has been adopted in which one inverter device is provided in a system and its AC output terminal is connected to a system power supply in cooperation therewith. In this case, however, the inverter device is installed in the system. It is customary to use an inverter device having a capacity corresponding to the output of the solar cell panel.

However, in this case, an inverter device having a different capacity is required according to the output of the solar cell panel.
In other words, in this case, for example, a system having a 1 KW solar cell panel requires an inverter device corresponding to 1 KW, and a system having a 10 KW solar cell panel requires an inverter device corresponding to 10 KW, for example. .

Therefore, in the case of a photovoltaic power generation system having a larger output, the grouped solar cell panels are further divided into several groups to form a plurality of subgroups, and one inverter device is provided for each subgroup. As a result, a method has been known in the related art in which each subgroup can be handled by an inverter device having the same capacity, and the cost can be reduced by sharing the capacity.

In the case of this prior art, for example, in a photovoltaic power generation system having a solar cell panel of 10 kW, the solar cell panel is divided into 10 subgroups of 1 kW, and an inverter device corresponding to 1 kW is provided for each subgroup. However, at this time, ten 1KW compatible inverter devices may be less expensive than 10KW compatible inverter devices because 1KW compatible inverter devices are widely used. As a result, the cost can be reduced.

[0008]

In the above prior art, no consideration is given to the parallel connection of the inverter devices.
There is a problem in that the power generation energy of each solar cell panel group is effectively used, and that there is a limit in cost reduction. In the case of the related art, if the inputs and outputs of a plurality of inverter devices are connected in parallel, a reflux occurs between the inverter devices, and an imbalance occurs in the output current.

Therefore, in the prior art, the DC inputs of the inverter devices cannot be connected in parallel, and are separated and independent. As a result, in the prior art, the operation coordination between the inverter devices is not achieved. If a failure occurs in the inverter device, the power generation energy of the solar cell panel group corresponding to the inverter device cannot be used effectively.

[0010] As a result, in the prior art, DC wiring from the solar cell panel to the inverter device is also required for the number of inverter devices, and the solar cell panel and the inverter device have switches. This is necessary for the number of inverter devices, so that the system cost increases.

Therefore, the problem to be solved by the present invention is, first of all, that even if a failure occurs in any of the inverter units, the energy of the solar cell panel can be utilized by a normal inverter without stagnation. It is intended to be able to reduce the system cost by making the DC section common wiring. Second, it is necessary to suppress a decrease in efficiency when the solar radiation is weak and the power obtained from the solar cell panel is small.

Thirdly, when a plurality of inverters fail, the output is shut off without affecting the normal inverters, and when the failure is released, the synchronous operation with the running inverter is restarted. It is to be able to continue stable operation without down. Therefore, an object of the present invention is to provide an inverter device that can solve these problems.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inverter device having an inverter main circuit divided into a plurality of units, in which the supply of a gate signal to a main switching element of the inverter unit is shared by all the inverter units. Thereby, the parallelization of the DC inputs of the plurality of inverter units is achieved. At this time, the above object can be achieved even if the supply of the gate signal can be arbitrarily stopped for at least one of the plurality of inverter units.

Similarly, at this time, the gate signal may be supplied in series via each inverter unit in order, and the gate signal may be supplied from a constant current source. The above objectives can be achieved, while
Even if the gate signal is supplied to each inverter unit in parallel, the above object can be achieved.

According to the present invention, there are provided a plurality of inverter units having a common DC terminal portion.
It is possible to provide an inverter device including a display operation panel device for monitoring the operation state of the inverter and controlling the operation and stop of the inverter.

Further, according to the present invention, a plurality of inverter units are provided in the inverter device, any one of which becomes a master unit inverter unit, and the other becomes a slave unit inverter unit. A master control board is provided in the master inverter unit, and the functions of this board are to synchronize the basic elements of the inverter, the power factor 1 control function, the maximum power function, the system link protection control function, and the main elements of each inverter unit. It has a gate signal output function for driving,
A slave control board can be provided in the slave unit inverter unit.

Here, the gate signal output from the master control board becomes a signal for driving the main switching element of the parent inverter unit and also a signal for driving the main signal element of the child inverter unit. The signal is passed to the slave control board of the next slave inverter unit, and is successively transmitted to the slave control board of the slave inverter unit.

Further, a mask circuit for a gate signal can be provided on the slave control board, and by operating this mask circuit, only the gate signal of the slave control board is masked while the other slave unit inverters are masked. The gate signal can be transmitted as it is.

Thus, it is possible to easily control whether this gate signal is supplied and the output of the slave unit is cut off. Further, a gate signal output from the master control board can be supplied from a constant current source, and stable gate control can be obtained even when the number of operating inverter units increases or decreases.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an inverter device according to the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 shows a first embodiment of an inverter device according to the present invention. An inverter device 1 according to this embodiment has an output terminal 3 and an input terminal 4, and a parent inverter unit 5 serving as a basic unit and an additional unit. And an output terminal 3 is connected to the system power supply 2.
, And the input terminal 4 is connected to a PV power supply 23 (a DC power supply composed of a solar cell panel).

The inverter device 1 further includes a system power supply voltage detector 6 for detecting the voltage of the system power supply 2, high-frequency filter units 9, 9a, a transformer 10 for matching input and output voltages, a system power supply An electromagnetic switch 11 for performing connection and disconnection between the inverter unit side and the inverter unit side, and a display operation panel unit 12 are provided.

First, the master inverter unit 5 includes an IPM (intelligent power module) including a main switching element for converting DC power into AC power.
15 and a master control board 13 are provided. The master control board 13 has a function of controlling the power factor to 1 at the time of inverter operation, a system cooperation protection control function, a maximum power function, and a function of outputting a gate signal for synchronously driving the main switching element of each inverter unit. ing.

Next, the slave unit inverter unit 5a has P
M15a and a slave control board 14 are provided.
Unlike the master control board 13, the slave control board 14 does not have a function of outputting a gate signal for synchronously driving the main switching element of the inverter unit, but has a function of inheriting a gate signal from the master. are doing.

Further, the inverter units 5, 5a
Are current detectors 7 and 7a for detecting their own output current states.
And IPMs 15 and 15a, DC / DC chopper power supply circuits 16 and 16a for control circuit operation, and backflow prevention diode 1
7 and 17a, smoothing capacitors 18 and 18a, and gate drive substrates 19 and 19a. At this time, the inverter unit 5 further includes a DC voltage detection circuit 8 for detecting a DC voltage state. I have.

At this time, the IPMs 15 and 15a provide a high-speed switching operation function and a self switching due to overcurrent and overheating inside the module to a main switching element composed of six sets of IGBTs in which high-speed diodes for flywheels are connected in parallel. It is composed of a module with an output cutoff function and an alarm signal output function.

Gate signals for driving the main switching elements of the IPMs 15 and 15a are output from the master control board 13, and the gate drive boards 19 and 19a are driven.
a, and the transmission path of the gate signal at this time is transmitted from the master control board 13 to the slave control board 14 through the outward cable 21, Return side cable 2
2 is a path for returning to the master control board 13 again.

Here, in order to increase the capacity of the inverter device 1, a slave unit inverter unit is further added. At this time, as shown in FIG. 2, the master control board 13 and each slave control board 14a, What is necessary is just to connect between 14b by the outbound path side cable 21 and 21a and the inbound path side cable 22 and 22a, respectively. FIG. 2 shows a case where the number of the added inverter units is one.
To that extent, the numbers indicating the respective constituent elements are indicated by adding a suffix a.

Further, at this time, as shown in the embodiment of FIG. 3, a step-up chopper device 24 is provided between the PV power supply 23 and the input terminal 4, whereby the transformer in the embodiment of FIGS. 10 may be removed. However, this is especially true when insulation isolation is required.

It should be noted that here, P made of a solar cell panel
When the DC output voltage of the V power supply 23 is higher than the AC voltage of the system power supply 2 (usually the opposite), the booster chopper device 24 is replaced with a step-down chopper device, and both voltages correspond to each other. In this case, neither the boost chopper device 24 nor the transformer 10 is required.

Next, the master control board 13, the slave control board 14a, and the gate drive boards 19, 19a will be described with reference to FIG. Here, mainly,
Only the supply path of the gate signal to the inverter units 15 and 15a will be described.
Except for 9a, details will be described later.

First, a gate signal output circuit section is mounted on the master control board 13, which includes a microprocessor 25, a failure hold circuit 44, a gate block control circuit 26, a constant current drive circuit 27, a non-inverting circuit. Output type buffer IC 28, non-inverted output type open collector transistor array 29, inverted output type driver IC 3
0, a gate signal output side connector 37, a gate signal input side connector 40, an internal stabilized power supply 41 of + 12V, a switching switch 62, and an external power supply input terminal 42 are provided. Is configured.

Next, on the slave control board 14a, a gate signal input side connector 38 for the forward path cable 21 is provided.
And a gate signal output side connector 39 for the return path cable 22. Then, the gate drive substrates 19, 1
9a, gate signal transmitting photocouplers 31 to 36,
31a to 36a are provided. Here, for each photocoupler, only the LED (light emitting diode) on the input side thereof is shown.

Here, each connector is connected by a cable, but the connection mode at this time differs depending on the number of inverter units installed.

First, when there is only one inverter unit, for example, in FIG. 1 to FIG. 3, if the slave unit inverter unit 5 a is not provided and only the master unit inverter unit 5 is used, Gate signal output side connector 37 and gate signal input side connector 40
They are connected as they are.

Next, when there are two inverter units, the gate signal output side connector 37 on the master control board side is connected to the gate signal input side connector 38 on the slave control board side, as shown in the figure. The gate signal output side connector 39 of the slave control board is connected to the gate signal input side connector 40 of the master control board. And
When there are two or more slave unit inverter units, they are sequentially connected in series. In this case,
The operation of this embodiment will be described. When the inverter device 1 is started, the microprocessor 25 confirms that there is no abnormality due to a failure or the like in the parent inverter unit 5 as described later, and when the operating condition is satisfied, the failure hold circuit 44 controls the gate block control. A gate drive power supply release signal is supplied to the circuit 26 to release the gate block.

At this time, the switching switch 62 has a function of selecting one of the internal stabilized power supply 41 and the external stabilized power supply 43 as a power supply for driving a gate signal. Where, now,
When the changeover switch 62 is connected to the internal stabilizing power supply 41, the driving power supply for the gate signal is
, And this is supplied to the constant current drive circuit 27 via the gate block control circuit 26.

On the other hand, the U +, U-, V +, V-, W +, and W- PWM signals for driving the main switching element are output as gate signals from the microprocessor 25, and are output to the open collector via the buffer IC 28. The signal is supplied to the transistor 29. At this time, while the gate signal is active, the output of the open collector transistor 29 is at H level and the output of the driver IC 30 is at L level.
It is set to be level.

As a result, when there is only one inverter unit, a constant current gate signal is output from the constant current drive circuit 27 as a constant current gate signal. Couplers 31-
After driving the 36 LEDs, they are directly sucked into the driver IC 30 via the connectors 37 and 40.

On the other hand, there are two inverter units, that is, as shown in FIGS.
In the case of operation by one of the slave unit inverter units 5a, the photocoupler 3
The constant current gate signals that drive the LEDs 1 to 36 are supplied from the connector 37 of the master control board 13 to the connector 38 of the slave control board 14 a via the cable 21.

The L of the photocouplers 31a to 36a on the gate drive board 19a of the slave control board 14a
After the ED is driven, it is supplied from the gate signal output side connector 39 to the gate signal input side connector 40 of the master control board 13 via the cable 22, and then sucked into the driver IC 30.

As a result, even when the number of the inverter units shown in FIG. 1 and the like is two, the gate signal of exactly the same timing is supplied to both the master unit inverter unit 5 and the slave unit inverter unit 5a. Therefore, it is possible to cause the master unit inverter unit 5 and the slave unit inverter unit 5a to perform switching operations that are completely synchronized.

As a result, there is no fear that a circulating current is generated between the parent inverter unit 5 and the child inverter unit 5a, although the input and the output are parallel to each other. According to one PV system
The power supply 23 can be handled by two inverter units.

By the way, in the embodiment of FIG. 4, the gate signal of the constant current driving the LED of each photocoupler is:
The driver IC 30 is finally sucked in. However, as shown in FIG. 5, instead of this, the output of the gate signal input side connector 40 of the master control board 13 is grounded (common potential point). Connect and LE of each photocoupler
The gate signal of the constant current driving D may be finally sucked into the ground which is the 0 V line, and the basic operation is the same even in this case.

Next, when further increasing the number of slave unit inverter units, as shown in FIG.
The connectors on each slave control board may be connected in series, starting from the gate signal output side connector. FIG. 6 shows a case where there are three slave unit inverter units. In this case, first, the gate signal output side connector OUT of the master control board 13 is connected to the first slave control board 14a by the cable 21. Connect to the gate signal input side connector IN. Note that, also in this case, the slave unit inverter units other than the slave unit inverter unit 5a are shown with subscripts b and c, respectively.

Next, the first slave control board 14
a for the gate signal output side connector OUT is a cable 2
1a, it is connected to the gate signal input side connector IN of the next second slave control board 14b. And
The gate signal output side connector OUT of the second slave control board 14b is expanded one after another by connecting the gate signal input side connector IN of the third slave control board 14c with the cable 21b. Connect in series.

The cable 22 connects the gate signal output side connector OUT of the last slave control board (in this case, the third slave control board 14 c) to the gate signal input side connector IN of the master control board 13. Once connected, the wiring will be completed.

Therefore, according to this embodiment, the number of slave unit inverter units can be arbitrarily increased,
The required number of inverter units can be connected in parallel to one PV power supply 23,
As a result, a solar cell panel having any power generation capacity can be easily handled by an inverter unit having the same capacity.

Further, according to this embodiment, the DC side of all the inverter units including the master unit inverter unit 15 can be connected in parallel, so that the DC unit wiring from the PV power source 23 composed of a solar cell panel to the inverter device 1 can be connected. And only one switch 4 is required, so that cost reduction can be easily obtained.

In this embodiment, the same number of photocoupler LEDs in each inverter unit are connected in series in accordance with the number of slave unit inverter units. The voltage of the gate signal is distributed according to each forward voltage of
There is a possibility that the driving may vary.

However, in this embodiment, since the gate signal is supplied from the constant current drive circuit 27, the gate signal is made to have a constant current, and therefore, the L signal is connected in series.
Even if the number of EDs is large, all are driven with the same current value, so that there is no risk of variation, and accurate switching control can always be obtained in all inverter units.

However, when the number of slave unit inverter units increases further, the added value of the forward voltage of the LED further increases, and the power supply voltage for producing the constant current source is set to +12 V provided in the master control board 13. Internal stabilized power supply 41
The voltage supplied from the power supply is insufficient, and there is a possibility that accurate driving cannot be performed.

Therefore, in this embodiment, the changeover switch 62 is provided so that the external stabilizing power supply 43 can be selected as necessary.
By preparing a device that generates a required voltage as 3, it is possible to easily cope with an increase in the number of additional slave unit inverter units.

Next, regarding the details of the slave control board,
This will be described with reference to FIG. Here, as a representative example,
Although the slave control board 14a will be described, the same applies to the other slave control boards 14b, 14c,.
In FIG. 7, the gate signal input side connector 38a, the gate signal output side connector 39a, the gate drive board 19a and the photocouplers 31a to 36
The LED a is the same as in FIGS. 4 and 5.

The U-phase and W-phase current values IU and IW of the slave unit inverter unit 15a detected by the current detector 7a are input to the input terminal 60, and are subjected to full-wave rectification by the maximum value selection circuit 46 and the maximum. The value is detected. Maximum value selection circuit 4
6 is compared with the overcurrent abnormality determination level value REF by the comparator CP. When the output exceeds the overcurrent abnormality level, the output of the comparator CP becomes H level, and the fault hold IC 4
7 is latched, and the occurrence of a failure is recorded.

On the other hand, a signal TRIP which becomes L level when an overcurrent and / or temperature abnormality occurs in the IPM 15a is input to the input terminal 61. And this input terminal 6
When the signal TRIP input to 1 becomes L level, the failure hold IC 48 is latched, and the occurrence of the failure is recorded similarly.

Therefore, when an abnormality occurs in the slave unit inverter unit 5a or the IPM 15a of the slave unit inverter unit, the level of the output Q of at least one of the failure holding ICs 47 and 48 becomes H, and the output Q
N goes to level L. Then, when the output Q of at least one of the failure hold ICs 47 and 48 becomes H level, the output of the failure determination logic circuit 49 becomes L level. As a result, the photocouplers 51 to 56 are turned on.

Here, these photocouplers 51 to 56
Are connected in parallel to the LEDs of the photocouplers 31a to 36a on the gate drive substrate 19a, respectively.
Is turned on, the LEDs of the photocouplers 31a to 36a
Are all short-circuited individually.

Then, the gate signal which has been flowing from the connector 38a to the connector 39a via the LEDs of the photocouplers 31a to 36a has been changed.
As a result, the photocouplers 31a to 36a are turned off irrespective of the gate signal, and the slave unit inverter unit 15a is in a gate block state and the output is cut off.

On the other hand, at this time, since the gate signal still flows from the connector 38a to the connector 39a via the photocouplers 51 to 56, the gate signal is transmitted from the master control board 13 of the master unit inverter unit 15 to another slave unit. The path of the gate signal returning via the inverter unit is not interrupted.

Therefore, according to this embodiment, the operation of the inverter unit in which an abnormality such as a failure has not occurred has been continued as it is, and only the inverter unit in which the abnormality has occurred is reliably stopped. Under sufficient protection against the occurrence of abnormalities, functional deterioration due to the occurrence of abnormalities is always minimized, and operation can be continued as it is.

At this time, the fault hold IC 47,
When at least one of the outputs QN of 48 becomes the level L, at least one of the photocouplers 57 and 59 is turned on. As a result, the slave control board 14a and the display operation panel device 12 (FIGS. 1 to 3) An inverter failure signal ALM is supplied to the display / operation panel device 12 via an input / output terminal 50a for connecting between them.

Then, the display operation panel unit 12 receives the inverter failure signal ALM, and
After a predetermined period of time, a failure release signal RS is generated, and the slave control board 1 is connected via the input / output terminal 50a.
4a. Then, the photo coupler 59 is turned on by the input of the failure release signal RS.

When the photocoupler 59 is turned on, a reset signal is supplied to the fault hold ICs 47 and 48, so that the fault hold by the fault hold ICs 47 and 48 is released here. Then, as a result, the photocouplers 51 to 56 are turned off, so that the gate signal flows again to the photocouplers 31a to 36a on the gate drive substrate side 19a.

Therefore, the abnormality which has occurred at this time is eliminated, and the set input S of the failure hold ICs 47 and 48 is set.
Is not at the level H, the operation of the slave unit inverter unit 5a is restarted. On the other hand, even when no abnormality has occurred in the slave unit inverter unit 5a, the on / off of the photocouplers 51 to 56 can be controlled by turning on and off the photocoupler 59 by inputting the failure release signal RS. Therefore, according to this embodiment, the operation of the inverter unit can be stopped arbitrarily.

Next, the interrelationship between the master control board 13, the slave control board 14a, and the display / operation panel device 12 will be described with reference to FIG. 8, taking as an example a case where three slave unit inverter units are provided. Here, the master control board 13
Is provided with the gate signal output section 64, the failure hold circuit 44, the gate block control circuit 26, and the like as described above, and the slave control board 14a
The exchange of information with the display operation panel device 12 is performed as follows.

First, the analog signal obtained from the transformer 6 for detecting the state of the system power supply voltage, the current detector 7 for detecting the output current state of the inverter unit, and the DC voltage detector 8 for insulatingly detecting the DC section voltage state Are a buffer amplifier 70, a sample hold IC 71, and a multiplexer I
The signal is supplied to an A / D converter 73 via C72 and a buffer amplifier 69.

After being converted into a digital signal by the A / D converter 73, the digital signal is transferred to the data bus line 68 via the buffer IC 74, and the detection data is taken into the microprocessor 25 under the control of the decoder 75. Here, the multiplexer 72 and the decoder 7
Reference numeral 5 functions to select various data and switch information output to the data bus line.

The microprocessor 25 executes processes necessary for basic control of the inverter, power factor 1 control, system coordination protection control, maximum power follow-up control, state monitoring, etc., based on these various types of information. At this time, the transmission and reception of the state monitoring state and other setting information between the microprocessor 25 of the master control board 13 and the microprocessor 80 of the display operation panel device 12 are performed by the communication driver IC 65a on the master control board 13 side. This is performed via the input / output terminal 75 by the communication driver IC 79 on the display operation panel device 12 side.

The microprocessor 80 fetching the information of the parent inverter unit 13 creates various monitor data based on the fetched information, and outputs the data to the data bus 81. This signal is processed by an LED driver 82 with a decoder function, and various monitor values such as system voltage, current, DC current and output power are displayed on a three-digit LED display 83.

The display operation panel unit 12 is provided with various setting buttons 84. The operation and stop of the whole system and various setting information input by these operations are transmitted via the microprocessor 80 and the communication driver IC 79. The operation of the inverter device 1 is controlled by the display operation panel device 12.

Here, if a hard error occurs in the watchdog timer of the microprocessor 25, control by communication cannot be performed. A photocoupler 66 is provided on the master control board 13 and the microprocessor 25
When a DT (watchdog timer error) signal is output, this signal is supplied to the display / operation panel device 12 via the input / output terminal 77.

After receiving the WDT signal, the microprocessor 80 of the display / operation panel device 12 sends a failure release signal RES to the master control board 13 after a predetermined time has elapsed. . As a result, on the master control board 13 side, the photocoupler 67 is turned on and the microcomputer initialization IC 63 is reset, so that the microprocessor 25 and the failure hold I
Initialization of C44 is performed.

As described above, FIG. 8 is an example in which there are three slave unit inverter units, and thus there are three slave control boards 14a, 14b and 14c. When an abnormality occurs due to a failure or the like, these slave control boards 14a, 14b, 14c
Generates an inverter failure signal ALM and supplies it to the display operation panel device 12.

The display / operation panel unit 12 generates a failure release signal RS and outputs the signal to each slave unit control board 14a, 14b.
b, 14c. At this time, the exchange of information between the display operation panel device 12 and each of the slave unit control boards 14a, 14b, 14c is performed by input / output terminals 50a, 50b, 50c.
c.

Here, as described above, the RS signal has a function as an operation command and a stop command even when there is no failure in each slave unit inverter unit. That is, RS
When the signal is at the L level, the gate signal can be masked and the output of the inverter unit can be cut off.

As a result, the operation of only the inverter unit to which the RS signal is given can be stopped regardless of the other inverter units in operation. When the RS signal is at the H level, the masking of the gate signal of the inverter unit is released, and the operation can be restarted by synchronizing with the other inverter unit in operation.

Therefore, according to this embodiment, the control information such as the output current command value and the output power command value generated from the master unit inverter unit 5 is transmitted from the master control board 13 to the display / operation panel device 12 by communication. When the output state of the main unit inverter unit 5 becomes close to 100%, it is possible to enable a control in which a command for starting the operation of the next sub unit inverter unit is generated from the display operation panel unit 12. .

As a result, the output status of the solar cell panel is
It is possible to predict by observing the operation state of the parent inverter unit, and to know the number of inverter units to be operated so as to optimize the power generation efficiency from the viewpoint of the entire system, and to instruct from the display operation panel unit 12 based on this. Will be possible.

Here, the switching loss due to the main switching element is substantially constant irrespective of its operation output. Therefore, when the inverter unit is operated with a light load, the efficiency generally decreases. Therefore, if the function of switching the number of operating units according to the present invention is used, the number of operating inverters can be limited according to the output of the solar cell panel, and the efficiency can be improved.

Next, another embodiment of the present invention will be described. Here, this embodiment is different from the above-described embodiment mainly in that a gate signal is supplied in parallel to each element rape control board, and a gate block control circuit is provided in each of the master control board and the slave control board. It is in the point provided.

First, FIG. 9 shows the master control board 13 and the slave control board 14a in this embodiment. In this embodiment, first, a constant current source circuit is used as a driving power supply for a gate signal. Instead, it is output as a constant voltage gate release signal via the transistor of the gate block control circuit 26.

Next, U +,
The gate signal for driving the main switching element, which is output as the PWM signal of U−, V +, V−, W +, W−, is transmitted through the buffer ICs 28 and 85. Here, the gate signal is In the active state, the output of the buffer IC 85 is set to L level.

Therefore, when the gate signal is in the active state, the gate drive circuit 1
A current flows through the LEDs of the nine photocouplers 31 to 36 and is sucked into the buffer IC 85 via the gate current adjusting resistor 95. The gate signal is supplied from the driver IC 30 to the gate signal output side connector 86 and transmitted to the slave unit inverter unit 5a via the gate signal cable 94.

On each slave unit inverter unit, the signal input via the gate signal cable 94 is passed to the gate signal input side connector 87 of the slave control board 14a. At this time, U +, U-, V +, V-, W
In addition to the + and W- PWM gate signals, a gate block signal and an OV line signal are transmitted together.

The PWM gate signal among these signals is supplied to the buffer IC 91 and becomes a signal for driving the LEDs of the photocouplers 31a to 36a on the gate drive board 19a of the slave unit inverter unit. Also,
The gate block signal is ANDed by the failure determination logic circuit 90 on the slave control board, and becomes a signal for controlling the gate block control circuit 89.

On the other hand, these gate signal input side connectors 8
Each terminal of 7 is directly connected to each terminal of the gate signal output side connector 88 as it is, and is transmitted to the gate signal input side connector 87 on the slave control board of the next slave unit inverter unit. .

Accordingly, in this embodiment, the number of slave unit inverter units is expanded, and for example, slave unit inverter units 5b and 5c are added to slave unit inverter units 5a.
In the case of adding a plurality of gate signal cables 94a and 9 as shown in FIG.
4b, the gate signal input side connector and the gate signal output side connector of the slave control board may be sequentially connected.

At this time, in the case of this embodiment, since all the signals are used in parallel in each inverter unit, there is no need to restore them. Thus, in the slave unit inverter unit 5c at the end of the last gate signal cable 94c, the switch 92 there is turned on, and all signals are grounded via the terminating resistor 93 here.

Next, FIG. 11 shows an example of the slave board 14a in this embodiment. For the slave control board 14a shown in FIG. 11, the same parts as those of the slave control board 14a shown in FIG. 7 will not be described, and only the differences will be described. First, FIG.
In the slave control board 14a, the output of the failure determination logic circuit 49 of the inverter unit itself is a drive signal for the photocouplers 51 to 56 for bypassing and masking the gate signal.

However, in the embodiment of FIG. 11, the gate block signal output from the failure hold circuit 44 of the master control board 13 is input to the failure determination circuit 49a via each signal cable, and the slave unit inverter unit itself is used. Is output from the failure determination circuit 49a to turn on and off the transistor of the gate block control circuit 89.

Here, the output of the failure judgment circuit 49a is set so as to be at the level H when an abnormality occurs. Therefore,
When the transistor of the gate block control circuit 89 is controlled to be turned on at the time of abnormality, the output signal GS becomes level L.
The LEDs 36a to 36a are always kept in the off state regardless of the state of the gate signal, and are controlled by the gate block.

[0092]

According to the present invention, when a plurality of system-coupling inverters are operated, it is possible to eliminate the stagnation of energy use of the solar cell panel when each inverter unit DC unit inverter fails. In addition, since the number of operating inverters is selected according to the amount of power generation energy of the solar panel, useless switching loss of the inverter main element is suppressed, and inverter efficiency is improved. In this case, it is possible to eliminate the suspension period of the system. Further, it is possible to reduce the cost of the inverter device by employing the master and slave control boards in the operation of a plurality of units and sharing the inverter unit body.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of an inverter device according to the present invention.

FIG. 2 is an overall configuration diagram for explaining expansion of an inverter unit according to an embodiment of the present invention.

FIG. 3 is an overall configuration diagram showing another embodiment of the inverter device according to the present invention.

FIG. 4 is a circuit diagram showing a connection state in an example of a master control board and a slave control board according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a connection state in another example of the master control board and the slave control board in one embodiment of the present invention.

FIG. 6 is an explanatory diagram of a method of adding an inverter unit according to an embodiment of the present invention.

FIG. 7 is a circuit diagram showing one embodiment of a slave control board according to the present invention.

FIG. 8 is a configuration diagram illustrating an example of an interface according to an embodiment of the present invention.

FIG. 9 is a circuit diagram showing a connection state in another example of the master control board and the slave control board in one embodiment of the present invention.

FIG. 10 is an explanatory diagram of a method of adding an inverter unit according to another embodiment of the present invention.

FIG. 11 is a circuit diagram showing another embodiment of the slave control board according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Inverter apparatus 2 System power supply 3 Output terminal part 4 Input terminal part 5 Main unit inverter unit 5a, 5b Slave unit inverter unit 6 System power supply voltage detector 7, 7a, 7b Current detector 8 DC voltage detector 9, 9a, 9b High frequency filter unit 10 Transformer 11 Electromagnetic switch 12 Display operation panel unit 13 Master control board 14, 14a, 14b Slave control board 15 IPM (Intelligent power module) 16 DC / DC chopper power circuit (switching regulator) 17 Backflow prevention Diode 18 Smoothing capacitor 19a, 19b, 19c Gate drive board 20, 21 Outgoing cable (going to gate signal line) 22 Incoming cable (going back to gate signal line) 23 PV power supply (DC power supply composed of solar cell panel) 24 Step-up chopper device 25 Microproceses A 26 Gate block control circuit 27 Constant current source circuit 28 Buffer IC (non-inversion output) 29 Open collector transistor array (non-inversion output) 30, 30a Driver IC (inversion output) 31, 31a Gate coupler photocoupler (U 32, 32a Photocoupler for gate driver (U-phase) 33, 33a Photocoupler for gate driver (for V-phase) 34, 34a Photocoupler for gate driver (V-phase) 35, 35a Gate Gate coupler photocoupler (for W phase +) 36, 36a Gate coupler bar photocoupler (for W phase-) 37 Gate signal line output side connector 38, 38a Gate signal line input side connector 39, 39a Gate signal line output side Connector 40 Gate signal line input side connector 41 Inside gate signal drive + 12V inside Stabilized power supply 42 External power supply input terminal 43 External stabilized power supply 44 Fault hold circuit 45 Control state monitoring IC 46 Maximum value selection circuit 47, 48 Fault hold IC 49, 49a Fault judgment logic circuit 50a, 50b, 50c Input / output terminal 51 Photocoupler (Gate-Doller Bar U-Phase Signal + Shunt) 52 Photocoupler (Gate-Doller Bar U-Phase Signal-Shunt) 53 Photocoupler (Gate-Doller Bar V-Phase Signal + Shunt) 54 Photocoupler (Gate Drabar part V-phase signal-for arrest 55 photocoupler (gate dorbar part W-phase signal-for arrest) 56 Photocoupler (gate dorbar part W-phase signal-for arrest) 57 Photocoupler (slave unit itself overcurrent protection) Alarm output) 58 Photocoupler (for output of IPM protection alarm of slave unit itself) 59 Slave unit failure release signal 6 INV output current detection signal input terminal 61 IPM protection trip signal input terminal 62 Changeover switch 63 Microcomputer initialization IC 64 Gate signal output section 65 Communication driver IC 66 Watchdog timer error output photocoupler 67 Microcomputer initialization input signal photo Coupler 68 Data bus line 69 Buffer amplifier 70 Buffer amplifier 71 Sample hold IC 72 Signal selection multiplexer IC 73 A / D converter 74 Three-state buffer IC 75 Decoder circuit 76 External communication terminal for display operation panel device 77 External input terminal for display operation panel device 79 Communication driver bar IC 80 Microprocessor 81 Data bus line 82 LED driver with decoder function 83 3-digit LED display (group) 84 Various setting buttons (group) 85 Driver IC 86 Connector for gate signal line output side 87 Connector for gate signal line input side 88 Connector for gate signal line output side 89 Gate block control circuit 90 Failure determination logic circuit 92 Termination resistor input switch 93 Termination resistors 94, 94a, 94b Gate Signal cable 95 Resistance for adjusting gate current A / B Address bus line D / B Data bus line A / D A / D converter CP comparator GS Gate block signal ALM Inverter failure signal RES, RS Failure release signal WDT Watchdog timer Error signal TX transmission RX reception U + U-phase upper gate signal U- U-phase lower gate signal V + V-phase upper gate signal V- V-phase lower gate signal W + W-phase upper gate signal w- W-phase lower gate signal MRS microcomputer Initialization signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroyuki Kazusa 7-1-1 Higashi Narashino, Narashino-shi, Chiba Inside Hitachi Keiyo Engineering Co., Ltd. (72) Inventor Satoshi Ibori 7-1-1 Higashi-Narashino, Narashino-shi, Chiba Stock 5H007 AA06 AA17 BB07 CA01 CB05 CC05 CC32 DB03 DB07 DB09 DC02 EA02 GA09 5H420 CC03 DD03 EA10 EA45 EA48 EB26 EB39 FF28 LL09

Claims (5)

[Claims] In an inverter device provided with an inverter main circuit divided into a plurality of units, supply of a gate signal to a main switching element of the inverter unit is made common to all the inverter units, so that a plurality of inverter units are provided. An inverter device configured to obtain parallel DC input. 2. The invention according to claim 1, wherein the supply of the gate signal is arbitrarily stopped for at least one of the plurality of inverter units. Features inverter device. 3. The inverter device according to claim 1, wherein the gate signal is supplied in series via each inverter unit in order. 4. The inverter device according to claim 1, wherein the gate signal is supplied to each inverter unit in parallel. 5. The inverter according to claim 3, wherein the gate signal is supplied from a constant current source.