JPH0250517A - Semiconductor device for delaying circuit - Google Patents

Abstract

PURPOSE:To make a hybrid IC monolithic to miniaturize and to attain low cost by providing plural serially connected inverters to generate a delay, a constant voltage circuit to drive the inverters and a gate circuit to generate a pulse equivalent to a prescribed delaying time from these inverters. CONSTITUTION:A pulse inputted to an input terminal 1 is shaped by a shaping inverter 2, inputted to an inverter 4 for delay and a prescribed delaying time is obtained. These inverters 4, 7 and 9 for delay are connected to a constant voltage circuit 11 to drive it. The constant voltage circuit 11 has a value at the room temperature of a prescribed delaying time from respective constants with the transistor size, impressed voltage and the temperature characteristic of the impressed voltage of the inverter for delay and a characteristic to change an impressed voltage V0 so that the delaying temperature cannot be changed even when the temperature is changed. Thus, since a hybrid IC is made monolithic and all the parts necessary for the delaying circuit are included on the board, and therefore, the decrease in cost as a board can be attained and the miniaturization of the device can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device for a delay circuit, and particularly to a semiconductor device for a delay circuit that can automatically adjust the delay time and can be miniaturized. It is.

[Conventional technology]

In a conventional semiconductor device for a delay circuit, a hybrid IC is assembled using an inductor and a capacitor as separate parts, and a predetermined delay time is generated by changing the values of L and C in each hybrid IC.

As is well known, methods for manufacturing hybrid ICs include methods using thin film elements and thick film elements.

The thin film element uses a thin film with a thickness of about 100 to several microns.

The substrate used is glass, grade ceramic, or an alumina substrate with an ultra-smooth surface. A vacuum evaporation method or a sputtering method is used to form a thin film, and a method through a metal mask or a photoetching method is used to form a pattern. As a capacitor, SiO by vacuum evaporation, SiO□ by AC sputtering, T
T a O obtained by electrolytically oxidizing the cathode sputtered film of a
A thin film of s is used. However, the above-mentioned capacitors are limited to small capacitance ones, and chip-shaped ceramic capacitors and Ta capacitors are used for large capacitance capacitors. The inductor is one that utilizes the stray inductance of a conductor, and is made of Cr-Au.

A conductor such as NiCr-Au or Ti-Pt-Au is formed into a multilayer structure of 2 to 3 layers.

On the other hand, thick film elements are relatively thick, with a film thickness of about 10 to 30 μm, and require high temperature firing.
Alumina substrates are mainly used. Both for conductors, resistors and dielectrics.

It is obtained by mixing metal powder, glass powder, etc. with an organic binder or an organic filler to form a paste, forming a pattern by screen printing, and baking the paste at 700 to 1000° C. in air or an inert atmosphere.

The conductor forming the inductance is Ag-Pd.

In addition to capital/waste threads such as Ag-Pt, Au-Pd, and Au-Pt, threads mainly made of Cu, Ni, W, etc. are also used.

In this way, conventional semiconductor devices for delay circuits.

It was created by combining an inductor and a capacitor, and in order to match the delay time, these inductors and capacitors were combined to create a hybrid. The hybrid IC is described, for example, in "Semiconductor Handbook (Second Edition)" published by Ohmsha Co., Ltd. on June 30, 1981, pp. 335-340.

[Problem to be solved by the invention]

Semiconductor devices for delay circuits are manufactured using hybrid ICs in which inductors and capacitors are made separately using these manufacturing methods.
Delay time was generated by changing the values of L and C. Therefore, it was not possible to move beyond the handmade stage, and the degree of automation was low. Furthermore, since the component costs of inductors and capacitors are high, even if attempts are made to reduce the cost of delay circuit semiconductor devices, there are limits to this.

Furthermore, since the conventional delay circuit device is a passive element with no power source, consisting only of an inductor and a capacitor, another element is required in order to restore the logic level. Therefore, not only the cost but also the space is considerably large, so it is impossible to downsize the device, and neither the cost nor the space can be satisfied.

The purpose of the present invention is to solve these conventional problems, to manufacture a board with all the necessary parts included, to make it easy to create an automated line, and to reduce the size and cost of the delay. An object of the present invention is to provide a circuit semiconductor device.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device for a delay circuit of the present invention includes a plurality of inverters connected in series to delay an input signal, and a semiconductor device for driving the inverters, and for controlling a predetermined value of the inverter according to a change in temperature. The present invention is characterized in that it includes a constant voltage circuit whose temperature characteristics are set such that the delay time of 1 does not change, and a gate circuit that generates a pulse corresponding to the predetermined delay time from the inverter.

[For production]

In the present invention, instead of using individual L and C elements, a "delay element" consisting of a plurality of inverters connected in series is used. In other words, a plurality of inverters connected in series that generate a delay and those inverters are used. It includes a constant voltage circuit for driving and a gate circuit that generates pulses corresponding to a predetermined delay time from these inverters.

This has made it possible to make the hybrid IC monolithic, making it smaller and lower in cost, and also making it possible to automatically adjust the delay time. Furthermore, if the semiconductor device of the present invention is made of CuO2, high performance operation can be achieved at low cost. Further, in a constant voltage circuit of a semiconductor device, in order to make the delay time and the temperature characteristics of the delay time constant, a circuit that adjusts the constant voltage output and its temperature characteristics can be provided.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a logic gate diagram of a semiconductor device for a delay circuit showing one embodiment of the present invention.

In FIG. 1, 1 is an input terminal for inputting a signal;
2, 4, 7, 9, 14, 16, 20, 22 are inverters, among which 2 is a shaping inverter, 4, 7.9 is a delay inverter which is the center of the present invention, and 14 , 20 and 22 are inverters for adjusting the pulse phase. Note that the number of delay inverters 4, 7.9 is not limited. 11 is a separately provided constant voltage circuit;
2 is a NOR circuit for creating the first pulse, and 18 is a NAND circuit for creating the second pulse. 1
7゜23, 24, and 25 are output terminals, respectively, for the positive polarity and negative polarity of the first pulse, the positive polarity of the second pulse,
This is a terminal that takes out negative polarity.

In FIG. 1, a separate power supply (constant voltage circuit 11) is used to adjust the delay time of the delay circuit (inverters 4, 7.9).
The first feature is that it is connected.

First, a pulse input to the input terminal 1 is shaped by the shaping inverter 2 and input to the delay inverter 4. A predetermined delay time is obtained by the delay inverters 4, 7.9. These delay inverters 4, 7.9 are connected to a constant voltage circuit 11 that drives them. Generally, the delay time T of an inverter. is expressed by the following formula (], ).

・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
- (1) P, etc. are all constants such as the size for manufacturing semiconductors such as transistors. Further, cout is the capacity of the load connected to the inverter.

In this way, the delay time T. is inversely proportional to the applied voltage v0, proportional to the output load capacitance CoIJ, and inversely proportional to the mobility. Therefore, in the present invention, the applied voltage v
By automatically changing 0, the delay time is made constant. That is, the constant voltage circuit 11 connected to the delay inverters 4, 7.9 is configured to operate at room temperature for a predetermined delay time based on the transistor size of the M extension inverter, the applied voltage, and the constants of the temperature characteristics of the applied voltage. and the applied voltage v so that the delay time does not change even if the temperature changes.
Give it the property of changing 0.

Generally, the applied voltage V is 5. In the case of about OV, the delay time of the inverter increases as the temperature increases, the mobility decreases and the threshold voltage also decreases, but the delay time increases due to the decrease in mobility, so the delay time of the inverter increases. Therefore, in order to keep the delay time constant, it is necessary to set the temperature characteristics of the constant voltage circuit 11 so that the constant voltage output v0 increases as the temperature rises. This allows the delay time of the delay circuit to be constant regardless of temperature.

Also, the applied voltage V is 2. If it is less than Ov, please refer to 5. above. Contrary to the Ov case, the threshold voltage decreases with increasing temperature, but the effect of this is greater than the effect of decreasing mobility.

In other words, rather than increasing the delay time due to a decrease in mobility,
Since the threshold voltage decreases more with increasing temperature, the delay time decreases with increasing temperature. Therefore, in order to keep the delay time constant regardless of temperature,
It is necessary to set the temperature characteristics of the constant voltage circuit 11 so that the output v0 of the constant voltage circuit 11 decreases as the temperature rises.

In this way, when the applied voltage v0 is about 5.0V and 2.
In the case of 0V or less, the temperature characteristics of the constant voltage circuit 11 must be set to be opposite characteristics. However, in FIG. 1, except for the delay inverters 4, 7.9, the logic level voltage 5. Since Ov is used, constant voltage circuit 1 of delay inverter 4, 7.9
1 needs to be set within a range where the logic level can be transmitted without a level shifter at a voltage of 5.0V or less.

Therefore, in order to cover the entire delay time with the semiconductor device of the present invention, in addition to setting the transistor size in the device, a central value of the delay time determined by the number of inverters is set, and then a constant voltage is set. It is necessary to finely adjust the delay time to the set value using the circuit 11.

FIG. 2 is a signal waveform diagram in FIG. 1.

The symbol attached to the left side of each signal waveform shown in Figure 2 is the first
Corresponds to the symbol of the signal line shown in the figure. The symbol attached to the right side of the waveform in FIG. 2 is the symbol of the corresponding signal waveform.

First, the input signal from the input terminal 1 is a rectangular wave as shown at 27 in FIG.

In delay inverters 4, 7.9, lines 26, 8 respectively
．． 10, signals with waveforms 29, 30°31 are output. Therefore, the NOR circuit 12 and the NAND circuit 18 have a waveform 28 that has passed through the line 3 and a waveform 3 that has passed through the line 10.
1 is input, the output line 13 of the NOR circuit 12
A waveform 32 is output to the output line 19 of the NAND circuit 18, and a waveform 33 is output to the output line 19 of the NAND circuit 18. Waveform 32 is inverted twice by inverters 14 and 16, so output terminal 17
In this case, a waveform 34 that is the same as the waveform 32 is obtained. Further, since the waveform 32 is inverted only once by the inverter 14, a waveform 35 which is an inverted version of the waveform 32 is obtained at the output terminal 23. Also.

Since the waveform 33 is inverted twice by the inverters 20 and 22, a waveform 37 which is the same as the waveform 33 is obtained at the output terminal 24. Furthermore, the waveform 33 is converted to 1 by the inverter 20.
Since the waveform 33 is inverted twice, a waveform 36 which is an inverted version of the waveform 33 is obtained at the output terminal 25.

FIG. 3 is an illustration of laser trimming used in accordance with the present invention.

In the present invention, as described above, the delay inverter 4
, 7.9, the delay circuit of the present invention is a semiconductor monolithic circuit, so it is necessary to set it within a range where the logic level can be transmitted at a voltage of 5.0 V or less without a level shifter. , constant voltage settings are made using each signal waveform 34 of the output terminals 17, 23, 24, and 25 in FIG.
While monitoring 35°37.36, it is possible to reach a predetermined value relatively easily. That is, the constant voltage can be easily set by using laser trimming or the like.

That is, as shown in FIG. 3, the reference voltage Rf and the constant voltage V provided with a plurality of cutting protrusions 28 to 31 in the middle of the bleeder resistor are input to the comparator 27,
After setting the output to IV etc.

While monitoring the output of the comparator 27, the protrusions 28 to 31 are cut one by one with a laser so that the delay time of both becomes the set value. If the laser trimming is finished when the delay time of the output of the comparator 27 reaches the set value, the voltage by the dividing resistor at that time will be the constant voltage V1. applied to the delay inverter. It is.

If the delay circuit according to this embodiment is adopted, even if the expected operation does not occur due to changes in design capacitance etc. when assembling a board, a delay circuit suitable for the board can be created according to this embodiment. , it is possible to perform a predetermined operation without changing the board. In addition, with conventional off-the-shelf delay circuits, it was difficult to obtain the desired delay because of the large steps, but in this embodiment, the steps can be made smaller and can respond to any request.

〔Effect of the invention〕

As explained above, according to the present invention, the hybrid I
Since C is made monolithic and all the components necessary for the delay circuit are included on the board, the cost of the board can be reduced, the device can be made smaller, and it is easier to create an automated line.

Automation can further reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram of a delay circuit semiconductor device showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part in FIG. 1,
FIG. 3 is an illustration of laser trimming used in accordance with the present invention. 2: Shaping inverter, 4, 7, 9: Delay inverter,
11: Constant voltage circuit, 12: NOR circuit, 14°16
．． 20: Phase inversion inverter, 18: NAND circuit,
17, 23, 24, 25: output terminal, 27: comparator, 28-31 cutting protrusion of nib reader resistor. Figure 2-1-37

Claims (1)

[Claims] (1) A plurality of inverters are connected in series to delay an input signal, and temperature characteristics are set so that the inverters are driven and a predetermined delay time by the inverters does not change due to changes in temperature. A semiconductor device for a delay circuit, comprising a constant voltage circuit and a gate circuit for generating a pulse corresponding to a predetermined delay time from the inverter.