JPH08330187A - Composite electronic device - Google Patents

Composite electronic device

Info

Publication number
JPH08330187A
JPH08330187A JP7152713A JP15271395A JPH08330187A JP H08330187 A JPH08330187 A JP H08330187A JP 7152713 A JP7152713 A JP 7152713A JP 15271395 A JP15271395 A JP 15271395A JP H08330187 A JPH08330187 A JP H08330187A
Authority
JP
Japan
Prior art keywords
dielectric
capacitors
electronic component
composite electronic
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7152713A
Other languages
Japanese (ja)
Other versions
JP3092693B2 (en
Inventor
Minoru Takatani
稔 高谷
Toshiichi Endo
敏一 遠藤
Nobunori Mochizuki
宣典 望月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP07152713A priority Critical patent/JP3092693B2/en
Publication of JPH08330187A publication Critical patent/JPH08330187A/en
Application granted granted Critical
Publication of JP3092693B2 publication Critical patent/JP3092693B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE: To provide a thin miniature composite electronic device including a plurality of capacitors having significantly different capacity employing a dielectric of different permittivity. CONSTITUTION: Dielectrics 12, 13, 14 of different permittivity are arranged in a same layer. Capacitors 3, 4, 5 are arranged such that the dielectrics 12, 13, 14 of different permittivity are interposed between the inner electrodes 9a and 9b, 10a and 10b, and 11a and 11b of different capacitors 3, 4, 5. Consequently, a plurality of capacitors 3, 4, 5 having significantly different capacity are formed in a same layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、誘電体材料を用いて複
数のコンデンサあるいは複数のコンデンサと共振器やイ
ンダクタ等を内蔵した複合電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite electronic component using a dielectric material and having a plurality of capacitors or a plurality of capacitors and a resonator, an inductor or the like built therein.

【0002】[0002]

【従来の技術】印刷法やシート法等の厚膜形成法を用い
てセラミック誘電体材料内に複数のコンデンサ等を内蔵
して形成する場合、従来は単一材質の誘電体により構成
するのが一般的である。特殊なものとしては、特開平3
−35515号公報に記載のように、同一層に形成され
るコンデンサ間に、低誘電率の誘電体を介在させて横並
びに隣接するコンデンサ間の容量結合を軽減させたもの
がある。また、特公平5−25399号公報には、誘電
率の異なる2種類あるいはそれ以上の誘電体を縦に重ね
合わせて周波数が大幅に異なるコンデンサを1つのチッ
プとして構成したものが開示されている。
2. Description of the Related Art When a plurality of capacitors or the like are built in a ceramic dielectric material by using a thick film forming method such as a printing method or a sheet method, it is conventionally constituted by a single material dielectric. It is common. As a special one, JP-A-3
As described in JP-A-35515, there is a capacitor in which a dielectric having a low dielectric constant is interposed between capacitors formed in the same layer to reduce capacitive coupling between adjacent capacitors in a lateral direction. Further, Japanese Patent Publication No. 5-25399 discloses a structure in which two or more types of dielectrics having different permittivities are vertically stacked and a capacitor having a significantly different frequency is configured as one chip.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、1つの
チップ(基板として用いられる場合を含む)を1種の誘
電率の誘電体材料によって複数のコンデンサを構成する
場合、あるいは特開平3−35515号公報に記載のよ
うに、隣接コンデンサ間に低誘電率材料を配設した場合
には、大幅に容量が異なる様々な容量のコンデンサを内
蔵して形成することができなかった。このため、容量の
大きなコンデンサは別部品として構成し、これをマザー
基板に半田付けするか、あるいは複合電子部品を基板と
して該基板に搭載することが行われており、このような
別部品として構成するコンデンサが多くなると、製造工
程が複雑化する上、全体として占有スペースが大になる
という問題点もあった。
However, when one chip (including the case where it is used as a substrate) is composed of a plurality of capacitors with a dielectric material having one dielectric constant, or Japanese Patent Laid-Open No. 3-35515. As described in (3), when a low dielectric constant material is arranged between adjacent capacitors, capacitors with various capacities having significantly different capacities cannot be built in. For this reason, a capacitor with a large capacitance is configured as a separate component, and this is soldered to a mother board or a composite electronic component is mounted on the board as a substrate. When the number of capacitors used increases, the manufacturing process becomes complicated, and the occupied space as a whole becomes large.

【0004】一方、特公平5−25399号公報に記載
のように、積層方向について異なる誘電率の誘電体を配
設して容量が大幅に異なるコンデンサを実現する場合に
は、厚みが大となるので、近年における薄型化の要求に
応えることは困難である。特に、例えば携帯電話の電圧
制御発振器等のような携帯機器等に内蔵する素子内蔵基
板のように、コンデンサ以外に共振器を一体に重畳し形
成しようとする場合には、積層体の厚みが大となり、薄
型化の要求に応えることがますます困難になる。また、
積層方向について誘電率の異なる誘電体を重ねて容量が
大幅に異なる複数のコンデンサを実現する場合におい
て、薄型化を達成するために、仮に、チップの面積を広
くしてコンデンサの層数を少なくしたとすると、印刷法
やシート法を用いて積層、乾燥工程を繰り返し、この繰
り返し工程の途中で容量値を測定し、途中の容量値に応
じてその後の積層工程における誘電体厚みや電極面積等
を調整することにより、焼成前のものについてある容量
値を適正な範囲内に抑えようとする場合、積層数が少な
い場合にはこの容量調整が困難となり、容量値がばらつ
き、歩留りが悪くなってしまうという問題点がある。
On the other hand, as described in Japanese Patent Publication No. 5-25399, when a dielectric material having different permittivities in the stacking direction is provided to realize a capacitor having a significantly different capacitance, the thickness becomes large. Therefore, it is difficult to meet the recent demand for thinning. In particular, when a resonator other than a capacitor is to be integrally superimposed and formed as in a device-embedded substrate such as a voltage-controlled oscillator of a mobile phone, which is built in a portable device, the thickness of the laminated body is large. Therefore, it becomes more and more difficult to meet the demand for thinning. Also,
In the case of realizing multiple capacitors that have significantly different capacitances by stacking dielectrics with different dielectric constants in the stacking direction, the area of the chip was tentatively increased to reduce the number of capacitor layers in order to achieve thinning. Then, the stacking and drying steps are repeated by using the printing method or the sheet method, the capacitance value is measured in the middle of this repeating step, and the dielectric thickness and the electrode area in the subsequent stacking step are determined according to the capacitance value in the middle. When trying to suppress a certain capacitance value before firing by adjusting the capacitance value, when the number of laminated layers is small, this capacitance adjustment becomes difficult, the capacitance value varies, and the yield deteriorates. There is a problem.

【0005】本発明は、上記した問題点に鑑み、容量が
大幅に異なる複数のコンデンサを含む複合電子部品を異
なる誘電率の誘電体を用いて構成する場合において、小
型化、薄型化が可能な構造のものを提供することを目的
とする。
In view of the above-mentioned problems, the present invention enables miniaturization and thinning when a composite electronic component including a plurality of capacitors having greatly different capacities is formed by using dielectrics having different permittivities. The purpose is to provide a structure.

【0006】[0006]

【課題を解決するための手段】この目的を達成するた
め、本発明の複合電子部品は、同一層内に異なる誘電率
の誘電体を配設し、これらの異なる誘電率の誘電体がそ
れぞれ異なるコンデンサの内部電極間に介在するように
コンデンサを配設することにより、同一層に容量が大幅
に異なる複数のコンデンサを形成したことを特徴とす
る。本発明において、隣接コンデンサ間の結合を軽減す
るため、コンデンサをそれぞれ形成した異なる誘電率の
誘電体の間および複合電子部品の外被部に、これらの誘
電体の誘電率より低い誘電体を一体に配設する構造が採
用される。また、前記複数のコンデンサを配設した積層
部に対して一体にストリップライン共振器を重畳する場
合、該ストリップライン共振器の周囲に該グランド電極
間の誘電体より低い誘電率の誘電体を配設することが好
ましい。本発明は、同一層内に異なる誘電率の誘電体を
形成する場合、異なる誘電率の誘電体を交互に印刷する
ことにより、異なる誘電率の誘電体層を同一層に容易に
形成できる。また、前記複合電子部品が一体焼成でなる
ことにより、信頼性の高いものが得られる。また、本発
明は、単にチップ状の複合電子部品として構成するのみ
ならず、複合電子部品を構成する積層体の表面に導体お
よび厚膜抵抗を印刷して基板とし、該基板に電子部品を
搭載した構造も実現される。
In order to achieve this object, the composite electronic component of the present invention has dielectrics having different permittivities arranged in the same layer, and the dielectrics having different permittivities are different from each other. By arranging the capacitors so as to be interposed between the internal electrodes of the capacitors, a plurality of capacitors having significantly different capacities are formed in the same layer. In the present invention, in order to reduce the coupling between adjacent capacitors, a dielectric having a dielectric constant lower than those of these dielectrics is integrated between the dielectrics having different dielectric constants forming the capacitors and in the outer cover portion of the composite electronic component. The structure of arranging is adopted. When the stripline resonator is integrally superimposed on the laminated portion in which the plurality of capacitors are arranged, a dielectric material having a lower dielectric constant than the dielectric material between the ground electrodes is arranged around the stripline resonator. It is preferable to install it. In the present invention, when dielectrics having different dielectric constants are formed in the same layer, dielectric layers having different dielectric constants can be easily formed in the same layer by alternately printing dielectrics having different dielectric constants. Further, since the composite electronic component is integrally fired, a highly reliable component can be obtained. In addition, the present invention is not only configured as a chip-shaped composite electronic component, but a conductor and a thick film resistor are printed on the surface of a laminate forming the composite electronic component to form a substrate, and the electronic component is mounted on the substrate. The structure is also realized.

【0007】[0007]

【作用】本発明は、異なる誘電率の誘電体を同一層に配
設すると共に、それぞれ異なるコンデンサの内部電極間
に、前記異なる誘電率の誘電体が介在するように配設し
たので、容量の大幅に異なるコンデンサが1つのチップ
内に形成される。また、容量の大小に応じた誘電率の誘
電体が横並びに形成されるから、チップ全体としての積
層数が少なくて済み、薄型化が達成される。また、容量
の大きなコンデンサも従来の印刷法等の製造ラインを用
いて、別部品でなく、チップ内に一体化して内蔵される
ので、小型化が達成できる。
According to the present invention, the dielectrics having different dielectric constants are arranged in the same layer, and the dielectrics having different dielectric constants are interposed between the internal electrodes of different capacitors. Significantly different capacitors are formed within one chip. Further, since the dielectrics having the dielectric constants corresponding to the magnitude of the capacitance are formed side by side, the number of laminated layers of the entire chip can be small, and thinning can be achieved. Further, a capacitor having a large capacity is also integrated into a chip by using a conventional production line such as a printing method, not as a separate component, so that miniaturization can be achieved.

【0008】[0008]

【実施例】図1(A)は本発明による複合電子部品の一
実施例を示す斜視図、(B)は(A)のE−E断面図、
図2は該複合電子部品の素材を製造方法にも関連させて
説明する分解斜視図である。1は印刷法あるいはシート
法により製造される積層体であり、図1(B)に示すよ
うに、内部にストリップライン共振器2が内蔵されると
共に、該共振器2に重畳して一体に、複数のコンデンサ
3、4、5が同一層に横並びに形成される。共振器2の
グランド電極6a、6bとストリップ導体7a、7bと
の間の誘電体8と、各コンデンサ3、4、5のそれぞれ
内部電極9aと9b、10aと10b、11aと11b
との間の誘電体12、13、14は、それぞれ異なる誘
電率の誘電体により構成される。また、これらの共振器
2間、およびコンデンサ3、4、5の間、および積層体
1の外被部の誘電体15は、共振器2やコンデンサ3、
4、5の誘電体8、12、13、14の誘電率より低い
誘電体により構成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a perspective view showing an embodiment of a composite electronic component according to the present invention, FIG. 1B is a sectional view taken along line EE of FIG.
FIG. 2 is an exploded perspective view for explaining the material of the composite electronic component in relation to the manufacturing method as well. Reference numeral 1 denotes a laminated body manufactured by a printing method or a sheet method. As shown in FIG. 1 (B), a stripline resonator 2 is built therein, and the resonator is superposed on the resonator 2 and integrally formed. A plurality of capacitors 3, 4, 5 are formed side by side on the same layer. The dielectric 8 between the ground electrodes 6a and 6b of the resonator 2 and the strip conductors 7a and 7b, and the internal electrodes 9a and 9b, 10a and 10b, 11a and 11b of the capacitors 3, 4, and 5, respectively.
The dielectrics 12, 13, and 14 between and are composed of dielectrics having different permittivities. The dielectric 15 between the resonators 2 and between the capacitors 3, 4, and 5 and the outer cover 15 of the laminated body 1 includes the resonator 2 and the capacitors 3,
It is composed of a dielectric material having a dielectric constant lower than that of the dielectric materials 4, 12, 13, and 14.

【0009】一例をあげれば、例えば共振器2の誘電体
8として比誘電率が30程度のチタン酸亜鉛セラミック
を用い、コンデンサ3の誘電体12として比誘電率が2
0程度のチタン酸マグネシウム系またはチタン酸亜鉛系
等のセラミックを用い、コンデンサ4の誘電体13とし
て比誘電率が200程度のチタン酸ストロンチウム系セ
ラミックを用い、コンデンサ5の誘電体14として比誘
電率が100程度の酸化チタン系セラミックを用い、周
囲や共振器2やコンデンサ3〜5間の低誘電率の誘電体
として比誘電率が5程度のアルミナ系セラミックを用い
る。
As an example, for example, a zinc titanate ceramic having a relative permittivity of about 30 is used as the dielectric 8 of the resonator 2, and a relative permittivity of 2 is used as the dielectric 12 of the capacitor 3.
A magnesium titanate-based or zinc titanate-based ceramic of about 0 is used, a strontium titanate-based ceramic having a relative dielectric constant of about 200 is used as the dielectric 13 of the capacitor 4, and a dielectric constant of 14 is used as the dielectric 14 of the capacitor 5. Is about 100, and an alumina ceramic with a relative permittivity of about 5 is used as a low-dielectric-constant dielectric around the resonator 2 and between the capacitors 3 and 5.

【0010】17は積層体1の表面部に形成した厚膜抵
抗、18は導体である。また、図1(A)において、1
9〜23は該積層体1を基板として用いて該基板に搭載
したトランジスタ、ダイオードや容量のさらに大きなコ
ンデンサあるいは抵抗あるいはインダクタであり、構成
する回路によって変わる電子部品である。25〜42は
該積層体1でなるチップの側面に設けられた端子電極で
あり、内蔵コンデンサ3〜5や共振器2間あるいはこれ
らと搭載電子部品19〜23や厚膜抵抗17間の接続あ
るいは外部回路との接続の為に設けられるものである。
Reference numeral 17 is a thick film resistor formed on the surface of the laminate 1, and 18 is a conductor. In addition, in FIG.
Reference numerals 9 to 23 are transistors, diodes, capacitors or resistors or inductors having a larger capacitance, which are mounted on the substrate by using the laminated body 1 as the substrate, and are electronic parts which vary depending on the circuit to be configured. Numerals 25 to 42 are terminal electrodes provided on the side surface of the chip made of the laminated body 1 and connected between the built-in capacitors 3 to 5 and the resonator 2 or between these and the mounted electronic components 19 to 23 and the thick film resistor 17, or It is provided for connection with an external circuit.

【0011】この複合電子部品の製造について図2によ
り説明する。図2は多数個取りする場合の1個の複合電
子部品について示すもので、(A)に示すように、最下
層の低誘電体層15aとなる誘電体ペーストを、所定の
厚みになるように所定回数印刷し、乾燥する工程を繰り
返した後、その上に銀あるいは銀−パラジウムを導体と
したグランド電極6aとなる導体ペーストを印刷し、そ
の上に、(B)に示すように、グランド電極6aとスト
リップ導体7a、7bとの間の部分について、共振器2
の周囲の低誘電率の誘電体層15bを形成する誘電体ペ
ーストと、共振器2内の誘電体8aを形成する誘電体ペ
ーストとを、交互に所定回数印刷する。その上に(C)
に示すように、ストリップ導体7a、7bを形成する導
体ペーストを印刷する。その上に(D)に示すように、
ストリップ導体7a、7b上の共振器2内の誘電体8b
を形成する誘電体ペーストと、その周囲の低誘電率の誘
電体15cを形成するペーストとを、交互に所定回数印
刷する。そしてその上に(E)に示すように、グランド
電極6bとなる導体ペーストを印刷する。
The manufacture of this composite electronic component will be described with reference to FIG. FIG. 2 shows one composite electronic component when a large number are taken. As shown in FIG. 2A, the dielectric paste to be the lowest low dielectric layer 15a is adjusted to have a predetermined thickness. After repeating the steps of printing a predetermined number of times and drying, a conductor paste to be the ground electrode 6a having silver or silver-palladium as a conductor is printed thereon, and as shown in FIG. 6a and the strip conductors 7a and 7b, the resonator 2
The dielectric paste forming the low-dielectric-constant dielectric layer 15b around and the dielectric paste forming the dielectric 8a in the resonator 2 are alternately printed a predetermined number of times. On top of that (C)
As shown in, the conductor paste forming the strip conductors 7a and 7b is printed. On top of that, as shown in (D),
Dielectric 8b in resonator 2 on strip conductors 7a, 7b
And the paste forming the low dielectric constant dielectric material 15c around it are alternately printed a predetermined number of times. Then, as shown in (E), a conductor paste to be the ground electrode 6b is printed thereon.

【0012】次に(F)に示すように、共振器2とコン
デンサ3〜5との間の低誘電率の誘電体15dとなる誘
電体ペーストを所定の厚みになるように所定回数印刷
後、各コンデンサ3、4、5の一方の内部電極9a、1
0a、11aとなる導体ペーストを印刷する。
Next, as shown in (F), after the dielectric paste which becomes the dielectric 15d having a low dielectric constant between the resonator 2 and the capacitors 3 to 5 is printed a predetermined number of times so as to have a predetermined thickness, One internal electrode 9a, 1 of each capacitor 3, 4, 5
The conductor paste to be 0a and 11a is printed.

【0013】次に(G)に示すように、それぞれコンデ
ンサ3、4、5を構成する異なる誘電率の誘電体12、
13、14となる誘電体ペーストと、その周囲の低誘電
率の誘電体15eとなる誘電体ペーストとを、例えば誘
電体15eのぺーストを印刷した後に誘電体12のペー
ストを印刷し、その後に誘電体13のペーストを印刷
し、その後に誘電体14のペーストを印刷し、必要なら
ばこれらの印刷工程を1回以上繰り返す。次に(H)に
示すように、コンデンサ3、4、5の各他方の内部電極
9b、10b、11bとなる導体ペーストを印刷する。
このような(F)の導体ペーストの印刷工程〜(H)の
工程を、コンデンサ3、4、5の内部電極の対数に相当
する回数だけ繰り返す。次に(I)に示すように、コン
デンサ3、4、5の上層の低い誘電率の誘電体15fと
なる誘電体ペーストを所定回数印刷する。その後、図1
(B)に示した厚膜抵抗17や導体18を印刷後、各チ
ップ毎に切断して焼成するか、あるいは焼成後に切断
し、端子電極25〜42を焼き付けやメッキ等により設
ける。
Next, as shown in (G), dielectrics 12 having different permittivities respectively forming capacitors 3, 4 and 5,
The dielectric pastes 13 and 14 and the dielectric paste to be the low-dielectric constant dielectric 15e around the dielectric paste are printed, for example, after the paste of the dielectric 15e is printed, and then the paste of the dielectric 12 is printed. The dielectric 13 paste is printed, then the dielectric 14 paste is printed, and if necessary, these printing steps are repeated one or more times. Next, as shown in (H), a conductor paste to be the inner electrodes 9b, 10b, 11b on the other side of the capacitors 3, 4, 5 is printed.
The printing process of the conductor paste of (F) to the process of (H) are repeated as many times as the number of pairs of the internal electrodes of the capacitors 3, 4, and 5. Next, as shown in (I), a dielectric paste to be the dielectric 15f having a low dielectric constant on the upper layers of the capacitors 3, 4, and 5 is printed a predetermined number of times. Then, Figure 1
After printing the thick film resistor 17 and the conductor 18 shown in (B), each chip is cut and baked, or cut after baking and the terminal electrodes 25 to 42 are provided by baking or plating.

【0014】図2に示すように、グランド電極6a、6
bにはチップ側面への引き出し部a、b、c、d、e、
f、g、hが形成され、これらのチップ側面への露出部
にはそれぞれ図1(A)の端子電極25、29、30、
33、34、38、39、42が接続される。また、ス
トリップ導体7aの両端にはそれぞれ端子電極26、3
7が接続され、ストリップ導体7bの両端にはそれぞれ
端子電極28、35が接続される。また、コンデンサ
3、4、5の各一方の内部電極9a、10a、11aの
引き出し部i、j、kにはそれぞれ端子電極40、3
6、32が接続され、対をなす他方の内部電極9b、1
0b、11bの引き出し部m、n、oにはそれぞれ端子
電極41、27、31が接続される。
As shown in FIG. 2, ground electrodes 6a, 6
In b, lead-out portions a, b, c, d, e,
f, g, and h are formed, and the terminal electrodes 25, 29, 30 of FIG.
33, 34, 38, 39, 42 are connected. Further, the terminal electrodes 26 and 3 are provided on both ends of the strip conductor 7a, respectively.
7 is connected, and terminal electrodes 28 and 35 are connected to both ends of the strip conductor 7b, respectively. Further, the terminal electrodes 40, 3 are respectively provided on the lead-out portions i, j, k of the internal electrodes 9a, 10a, 11a of the capacitors 3, 4, 5 respectively.
6, 32 are connected to each other, and the other inner electrode 9b, 1
Terminal electrodes 41, 27 and 31 are connected to the lead-out portions m, n and o of 0b and 11b, respectively.

【0015】このように、同一層内に異なる誘電率の誘
電体12、13、14を配設し、これらの異なる誘電率
の誘電体12、13、14がそれぞれコンデンサ3、
4、5の内部電極9aと9b、10aと10b、11a
と11bとの間に介在するようにコンデンサ電極を設け
ることにより、同一層に容量が大幅に異なる複数のコン
デンサを形成できる。このようにコンデンサ3、4、5
を横並びに形成すれば、誘電率の異なる誘電体を重ねる
ことによって容量が大幅に異なるコンデンサを縦並びに
形成する場合に比較して薄型化が達成できる。特に共振
器2もコンデンサ3、4、5と一体に形成する場合に
は、全体としての厚みを増大させないという意味で重要
な効果を奏する。また、容量の異なるコンデンサを縦並
びに配設する場合のように、薄型化のために層数を減少
させる必要がないから、各層の厚さを計測しながら印刷
工程を調整して誘電体や導体を印刷することによって、
容量値が所定範囲内に納められた歩留りのよい複合電子
部品の製造が可能となる。また、容量の大きなコンデン
サも従来の印刷法等の製造ラインを用いて、別部品でな
く、チップ内に一体化して内蔵されるので、小型化と製
造工程の簡略化が達成できる。また、コンデンサ3、
4、5の厚さが異なる場合、最大厚さのコンデンサに合
わせて不足分を低誘電率の誘電体で補充する構成とする
こともできる。
Thus, the dielectrics 12, 13, and 14 having different permittivities are arranged in the same layer, and the dielectrics 12, 13, and 14 having different permittivities are respectively the capacitors 3 and
4, 5 internal electrodes 9a and 9b, 10a and 10b, 11a
By providing the capacitor electrodes so as to be interposed between the capacitors 11b and 11b, it is possible to form a plurality of capacitors having significantly different capacitances in the same layer. In this way capacitors 3, 4, 5
If the capacitors are formed side by side, it is possible to reduce the thickness as compared with the case where capacitors having significantly different capacities are formed vertically by stacking dielectrics having different dielectric constants. In particular, when the resonator 2 is also formed integrally with the capacitors 3, 4, and 5, it has an important effect in that the thickness as a whole is not increased. In addition, since it is not necessary to reduce the number of layers in order to reduce the thickness, as in the case of vertically arranging capacitors having different capacities, the printing process is adjusted while measuring the thickness of each layer to adjust the dielectric or conductor. By printing
It is possible to manufacture a composite electronic component having a capacity value within a predetermined range and having a high yield. Further, since a large-capacity capacitor is also integrated into a chip by using a conventional manufacturing line such as a printing method, instead of being a separate component, miniaturization and simplification of the manufacturing process can be achieved. Also, the capacitor 3,
When the thicknesses of 4 and 5 are different, the shortage can be supplemented with a dielectric having a low dielectric constant according to the maximum thickness of the capacitor.

【0016】また、隣接コンデンサ3、4、5間の誘電
体15を低誘電率の誘電体としたことにより、コンデン
サ3、4、5間の容量結合を軽減すると共に、コンデン
サ3、4、5の外部すなわち積層体1の周囲の誘電体も
低誘電率としたことにより、端子電極25〜42間の容
量結合も軽減され、コンデンサ3、4、5間の容量結合
による信号伝播等の悪影響を軽減でき、コンデンサ3、
4、5の設計が容易となる。また、各コンデンサ3、
4、5の容量結合を軽減できるので、各コンデンサ3、
4、5を近接配置でき、小型化にも寄与する。
Further, by making the dielectric material 15 between the adjacent capacitors 3, 4, 5 a dielectric material having a low dielectric constant, the capacitive coupling between the capacitors 3, 4, 5 is reduced, and at the same time, the capacitors 3, 4, 5 are provided. Also, since the dielectric outside the body, that is, around the laminated body 1 is also made to have a low dielectric constant, the capacitive coupling between the terminal electrodes 25 to 42 is reduced, and the adverse effect such as signal propagation due to the capacitive coupling between the capacitors 3, 4, and 5 is adversely affected. Can be reduced, capacitor 3,
4, 5 design becomes easy. Also, each capacitor 3,
Capacitor coupling of 4 and 5 can be reduced, so each capacitor 3,
4, 5 can be arranged close to each other, which contributes to downsizing.

【0017】ストリップライン共振器2の周囲にグラン
ド電極6a、6b間の誘電体8より低い誘電率の誘電体
15を配設したので、共振器2とコンデンサ3、4、5
との間の容量結合も軽減でき、共振器2とコンデンサ
3、4、5との間の干渉等の悪影響を防止できる。また
前記のような積層体1はシート法によっても製造可能で
あるが、上記実施例で示すような印刷法によれば、誘電
率の異なる誘電体ペーストを、異なる誘電率の誘電体ペ
ーストを印刷しなかった領域に交互に印刷するだけで実
現できるので、製造が容易となる。また、本発明は、前
記複合電子部品が一体焼成でなることにより、信頼性の
高いものが得られる。また、異なる誘電率の誘電体を実
現する構造は接着等の方法によっても実現できるが、全
体を一体に焼成することにより、信頼性の高い複合電子
部品が実現できる。また、積層体1の表面に導体18お
よび厚膜抵抗17を印刷して基板とし利用可能とし、該
基板1に電子部品19〜23を搭載した構造とすること
により、全体として小型の混成集積回路部品が構成でき
る。
Since the dielectric 15 having a lower dielectric constant than the dielectric 8 between the ground electrodes 6a and 6b is arranged around the stripline resonator 2, the resonator 2 and the capacitors 3, 4, 5 are provided.
It is also possible to reduce the capacitive coupling between and, and prevent adverse effects such as interference between the resonator 2 and the capacitors 3, 4, and 5. The laminated body 1 as described above can also be manufactured by a sheet method. However, according to the printing method as shown in the above embodiment, dielectric pastes having different dielectric constants are printed, and dielectric pastes having different dielectric constants are printed. Since it can be realized only by alternately printing in the areas that have not been formed, manufacturing becomes easy. Further, according to the present invention, since the composite electronic component is integrally fired, a highly reliable one can be obtained. Further, although a structure for realizing dielectrics having different permittivities can be realized by a method such as bonding, a highly reliable composite electronic component can be realized by integrally firing the whole. Further, the conductor 18 and the thick film resistor 17 are printed on the surface of the laminated body 1 so that it can be used as a substrate, and the electronic components 19 to 23 are mounted on the substrate 1, so that the overall size of the hybrid integrated circuit is small. Parts can be configured.

【0018】図3(A)は本発明による複合電子部品の
他の実施例を示す斜視図、(B)はそのF−F断面図、
図4は図3は該複合電子部品の素材を製造方法にも関連
させて説明する分解斜視図である。本実施例の複合電子
部品は、異なる誘電率の誘電体50、51と内部電極5
2aと52b、53aと53bとからなるコンデンサ5
4、55を同一層に形成すると共に、これらのコンデン
サ54、55の間および外部に低誘電率の誘電体15を
配置し、さらにこれらのコンデンサ54、55と異なる
層に重ねて別の誘電率からなる誘電体56と内部電極5
7a、57bからなるコンデンサ58と設け、該コンデ
ンサ58と前記コンデンサ54、55との間およびコン
デンサ58の外部にも低誘電率の誘電体15を配設した
ものである。
FIG. 3A is a perspective view showing another embodiment of the composite electronic component according to the present invention, and FIG. 3B is its FF sectional view.
FIG. 4 is an exploded perspective view for explaining the material of the composite electronic component in relation to the manufacturing method. The composite electronic component of this embodiment includes dielectrics 50, 51 and internal electrodes 5 having different dielectric constants.
Capacitor 5 consisting of 2a and 52b, 53a and 53b
4, 55 are formed on the same layer, a low dielectric constant dielectric material 15 is arranged between these capacitors 54, 55 and outside, and further, they are stacked on different layers from these capacitors 54, 55 and have different dielectric constants. Dielectric 56 and internal electrode 5
A capacitor 58 composed of 7a and 57b is provided, and the dielectric 15 having a low dielectric constant is provided between the capacitor 58 and the capacitors 54 and 55 and outside the capacitor 58.

【0019】この複合電子部品は、図4(A)に示すよ
うに、下層の低誘電率の誘電体15fとなる誘電体ペー
ストを所定回数印刷後、各コンデンサ54、55の一方
の内部電極52a、53aとなる導体ペーストを印刷す
る。次に(B)に示すように、それぞれコンデンサ5
4、55を構成する異なる誘電率の誘電体50、51と
なる誘電体ペーストと、その周囲の低誘電率の誘電体1
5gとなる誘電体ペーストとを、例えば誘電体15gの
ペーストを印刷した後にコンデンサ54の誘電体50の
ペーストを印刷し、その後にコンデンサ55の誘電体5
1のペーストを印刷し、必要ならばこれらの工程を1回
以上繰り返す。次に(C)に示すように、コンデンサ5
4、55の各他方の内部電極52b、53bとなる導体
ペーストを印刷する。このような(A)の内部電極印刷
工程〜(C)の工程を、コンデンサ54、55の内部電
極52aと52b、53aと53bの各対数に相当する
回数だけ繰り返す。
In this composite electronic component, as shown in FIG. 4A, one of the internal electrodes 52a of one of the capacitors 54 and 55 is printed after the dielectric paste, which is the lower dielectric 15f having a low dielectric constant, is printed a predetermined number of times. , 53a is printed. Next, as shown in FIG.
4 and 55, the dielectric pastes to be the dielectrics 50 and 51 having different dielectric constants, and the dielectric 1 having a low dielectric constant around them.
The dielectric paste of 5 g, for example, the paste of the dielectric 15 g is printed, then the paste of the dielectric 50 of the capacitor 54 is printed, and then the dielectric 5 of the capacitor 55 is printed.
Print 1 paste and repeat these steps one or more times if necessary. Next, as shown in FIG.
The conductor paste to be the inner electrodes 52b and 53b on the other side of Nos. 4 and 55 is printed. The internal electrode printing step (A) to the step (C) are repeated as many times as the number of logarithms of the internal electrodes 52a and 52b and 53a and 53b of the capacitors 54 and 55.

【0020】次に(D)に示すように、コンデンサ5
4、55の上層の低い誘電率の誘電体層15hを所定回
数印刷する。その後コンデンサ58の一方の内部電極5
7aとなる導体ペーストを印刷する。次に(E)に示す
ように、コンデンサ58を構成する誘電体56となる誘
電体ペーストと、その周囲の低誘電率の誘電体15iと
なる誘電体ペーストとを、例えば誘電体15iのペース
トを印刷した後に誘電体56のペーストを印刷し、必要
ならばこれらの工程を1回以上繰り返す。次に(F)に
示すように、コンデンサ58の他方の内部電極57bと
なる導体ペーストを印刷する。このような(D)の内部
電極印刷工程〜(F)の工程を、コンデンサ58の内部
電極57a、57bの対数に相当する回数だけ繰り返
す。
Next, as shown in FIG.
The low dielectric constant dielectric layer 15h, which is the upper layer of the layers 4 and 55, is printed a predetermined number of times. After that, one internal electrode 5 of the capacitor 58
The conductor paste to be 7a is printed. Next, as shown in (E), a dielectric paste serving as the dielectric 56 that forms the capacitor 58 and a dielectric paste serving as the dielectric 15i having a low dielectric constant around the dielectric paste are, for example, the paste of the dielectric 15i. After printing, the dielectric 56 paste is printed, and if necessary, these steps are repeated one or more times. Next, as shown in (F), a conductor paste to be the other internal electrode 57b of the capacitor 58 is printed. The internal electrode printing step (D) to the step (F) are repeated as many times as the number of logarithms of the internal electrodes 57a and 57b of the capacitor 58.

【0021】次に(G)に示すように、コンデンサ58
の上層の低い誘電率の誘電体15jとなる誘電体ペース
トを所定回数印刷する。その後の処理は前記の通りであ
る。図4に示す内部電極52a、52b、53a、53
b、57a、57bの各引き出し部p、r、q、s、
t、uはそれぞれ図3(A)に示す積層体1Aの側面の
端子電極61、62、63、64、65、66に接続さ
れる。
Next, as shown in FIG.
The dielectric paste to be the upper dielectric layer 15j having a low dielectric constant is printed a predetermined number of times. Subsequent processing is as described above. Internal electrodes 52a, 52b, 53a, 53 shown in FIG.
b, 57a, 57b, and lead-out parts p, r, q, s,
t and u are connected to the terminal electrodes 61, 62, 63, 64, 65, 66 on the side surface of the laminated body 1A shown in FIG. 3A, respectively.

【0022】本発明において、異なる誘電率の誘電体に
それぞれ異なるコンデンサが内蔵され、そのうちのある
同一誘電率の誘電体については、回路の設計の都合上、
2つ以上の異なるコンデンサが横並びに、あるいは縦並
び(積層方向に)隣接して設けられる場合もある。その
他、上記実施例以外に、コンデンサにインダクタを一体
に重畳したもの等、種々の変更、付加が可能である。
In the present invention, different capacitors are built in dielectrics having different dielectric constants, and one of them has the same dielectric constant.
In some cases, two or more different capacitors are provided side by side or side by side (in the stacking direction). Other than the above embodiments, various modifications and additions such as a capacitor integrally superposed with an inductor can be made.

【0023】[0023]

【発明の効果】請求項1によれば、積層体における同一
層内に異なる誘電率の誘電体を配設しそれぞれコンデン
サを構成したので、同一層に容量が大幅に異なる複数の
コンデンサを形成できる。そして、このように誘電率を
変えて容量が大幅に異なるコンデンサを横並びに形成す
れば、誘電率の異なる誘電体を重ねることによって容量
が大幅に異なるコンデンサを縦並びに形成する場合に比
較して薄型化が達成できる。また、容量の異なるコンデ
ンサを縦並びに配設する場合のように、薄型化のために
層数を減少させる必要がないから、容量値を計測しなが
ら印刷工程を調整して誘電体や導体を印刷することによ
って、容量値が所定範囲内に納められた歩留りのよい複
合電子部品の製造が可能となる。また、容量の大きなコ
ンデンサも従来の印刷法等の製造ラインを用いて、別部
品でなく、チップ内に一体化して内蔵されるので、小型
化と製造工程の簡略化が達成できる。
According to the first aspect of the present invention, since the dielectrics having different permittivities are arranged in the same layer in the laminated body to form the respective capacitors, a plurality of capacitors having significantly different capacitances can be formed in the same layer. . If capacitors with greatly different capacities are formed side by side by changing the dielectric constants in this way, it is possible to reduce the thickness compared to the case where capacitors with significantly different capacities are formed vertically by stacking dielectrics with different dielectric constants. Can be achieved. In addition, because it is not necessary to reduce the number of layers in order to reduce the thickness, as in the case where capacitors with different capacities are arranged vertically, the printing process is adjusted while measuring the capacitance value to print the dielectric or conductor. By doing so, it is possible to manufacture a composite electronic component having a capacitance value within a predetermined range and having a high yield. Further, since a large-capacity capacitor is also integrated into a chip by using a conventional manufacturing line such as a printing method, instead of being a separate component, miniaturization and simplification of the manufacturing process can be achieved.

【0024】請求項2によれば、隣接コンデンサ間の誘
電体を低誘電率の誘電体としたことにより、各コンデン
サ間の容量結合を軽減できると共に、コンデンサの外部
すなわち積層体の周囲の誘電体も低誘電率としたことに
より、コンデンサの端子電極間の容量結合も軽減され、
コンデンサ間の容量結合による信号伝播等の悪影響を軽
減でき、コンデンサの設計が容易となる。また、各コン
デンサの容量結合を軽減できるので、各コンデンサを近
接配置でき、小型化にも寄与する。
According to the second aspect of the present invention, since the dielectric between the adjacent capacitors is a dielectric having a low dielectric constant, the capacitive coupling between the capacitors can be reduced, and the dielectric outside the capacitors, that is, around the laminated body, can be reduced. The low dielectric constant also reduces capacitive coupling between the capacitor terminal electrodes,
The adverse effects such as signal propagation due to capacitive coupling between capacitors can be reduced, and the capacitors can be easily designed. Further, since the capacitive coupling of each capacitor can be reduced, the capacitors can be arranged close to each other, which contributes to downsizing.

【0025】請求項3によれば、ストリップライン共振
器もコンデンサと一体に形成したので、全体としての厚
みを増大させず、携帯電話や移動式無線通信機器等に搭
載する電圧制御発振器等に本発明の部品を使用する場
合、実装が容易となるという重要な効果を奏する。ま
た、ストリップライン共振器のストリップ導体が貫通す
るグランド電極間の誘電体の部分の周囲に該グランド電
極間の誘電体より低い誘電率の誘電体を配設したので、
共振器とコンデンサとの結合も軽減でき、共振器とコン
デンサとの間の干渉や特性の相互の悪影響を防止でき
る。
According to the present invention, since the stripline resonator is also formed integrally with the capacitor, the thickness as a whole is not increased, and the stripline resonator is applied to a voltage controlled oscillator or the like mounted on a mobile phone, a mobile wireless communication device or the like. When the component of the invention is used, it has an important effect of facilitating mounting. Further, since the dielectric having a lower dielectric constant than the dielectric between the ground electrodes is arranged around the portion of the dielectric between the ground electrodes through which the strip conductor of the stripline resonator penetrates,
The coupling between the resonator and the capacitor can also be reduced, and interference between the resonator and the capacitor and mutual adverse effects of the characteristics can be prevented.

【0026】請求項4によれば、誘電率の異なる誘電体
ペーストを、異なる誘電率の誘電体ペーストを印刷しな
かった領域に交互に印刷するだけで実現できるので、製
造が容易となる。
According to the fourth aspect, the dielectric pastes having different permittivities can be realized by merely printing them alternately on the areas where the dielectric pastes having different permittivity are not printed, which facilitates the manufacturing.

【0027】請求項5によれば、複合電子部品が一体焼
成でなることにより、信頼性の高い複合電子部品が得ら
れる。
According to the fifth aspect, since the composite electronic component is integrally fired, a highly reliable composite electronic component can be obtained.

【0028】請求項6によれば積層体の表面に導体およ
び厚膜抵抗を印刷して基板とし利用可能とし、該基板に
電子部品を搭載した構造としたので、全体として小型の
混成集積回路部品が構成できる。
According to the sixth aspect of the present invention, since the conductor and the thick film resistor are printed on the surface of the laminated body so that it can be used as a substrate, and the electronic components are mounted on the substrate, the overall size of the hybrid integrated circuit component is small. Can be configured.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は本発明による複合電子部品の一実施例
を示す斜視図、(B)は(A)のE−E断面図である。
1A is a perspective view showing an embodiment of a composite electronic component according to the present invention, and FIG. 1B is a sectional view taken along line EE of FIG.

【図2】本実施例の構成を示す分解斜視図である。FIG. 2 is an exploded perspective view showing the configuration of the present embodiment.

【図3】(A)は本発明による複合電子部品の他の実施
例を示す斜視図、(B)は(A)のF−F断面図であ
る。
3A is a perspective view showing another embodiment of the composite electronic component according to the present invention, and FIG. 3B is a sectional view taken along line FF of FIG.

【図4】図3の実施例の構成を示す分解斜視図である。FIG. 4 is an exploded perspective view showing the configuration of the embodiment shown in FIG.

【符号の説明】[Explanation of symbols]

1、1A:積層体、2:共振器、3〜5、54、55、
58:コンデンサ、6a、6b:グランド電極、7a、
7b:ストリップ導体、8、12、13、14、50、
51、56:誘電体、9a、9b、10a、10b、1
1a、11b、52a、52b、53a、53b、57
a、57b:内部電極、25〜42、61〜66:端子
電極
1, 1A: laminated body, 2: resonator, 3 to 5, 54, 55,
58: capacitor, 6a, 6b: ground electrode, 7a,
7b: strip conductor, 8, 12, 13, 14, 50,
51, 56: Dielectrics, 9a, 9b, 10a, 10b, 1
1a, 11b, 52a, 52b, 53a, 53b, 57
a, 57b: internal electrodes, 25-42, 61-66: terminal electrodes

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】同一層内に異なる誘電率の誘電体を配設
し、これらの異なる誘電率の誘電体がそれぞれ異なるコ
ンデンサの内部電極間に介在するようにコンデンサを配
設することにより、同一層に容量が大幅に異なる複数の
コンデンサを形成したことを特徴とする複合電子部品。
Claims: 1. By arranging dielectrics having different dielectric constants in the same layer and arranging the capacitors so that the dielectrics having different dielectric constants are interposed between the internal electrodes of the respective capacitors, A composite electronic component characterized by forming multiple capacitors with significantly different capacities.
【請求項2】請求項1において、前記複数のコンデンサ
をそれぞれ形成した異なる誘電率の誘電体の間および複
合電子部品の外被部に、これらの誘電体の誘電率より低
い誘電体を一体に配設したことを特徴とする複合電子部
品。
2. The dielectric material having a dielectric constant lower than those of the dielectric materials is integrally formed between the dielectric materials having different dielectric constants respectively forming the plurality of capacitors and in the outer cover portion of the composite electronic component. A composite electronic component characterized by being provided.
【請求項3】請求項1または2において、前記複数のコ
ンデンサを配設した積層部に対して一体にストリップラ
イン共振器を重畳し、該共振器の周囲に、該共振器のグ
ランド電極間の誘電体より低い誘電率の誘電体を配設し
たことを特徴とする複合電子部品。
3. The stripline resonator according to claim 1 or 2, wherein a stripline resonator is integrally superposed on a laminated portion in which the plurality of capacitors are arranged, and a ground electrode of the resonator is provided around the resonator. A composite electronic component comprising a dielectric having a dielectric constant lower than that of the dielectric.
【請求項4】請求項1から3までのいずれかにおいて、
同一層内に、異なる誘電率の誘電体を交互に印刷するこ
とにより、異なる誘電率の誘電体層を同一層に形成した
ことを特徴とする複合電子部品。
4. The method according to any one of claims 1 to 3,
A composite electronic component, wherein dielectric layers having different dielectric constants are formed in the same layer by alternately printing dielectrics having different dielectric constants in the same layer.
【請求項5】請求項1から4までのいずれかにおいて、
前記複合電子部品が一体焼成により得られたものでなる
ことを特徴とする複合電子部品。
5. The method according to any one of claims 1 to 4,
A composite electronic component, wherein the composite electronic component is obtained by integral firing.
【請求項6】請求項1から5までのいずれかにおいて、
複合電子部品を構成する積層体の表面に導体および厚膜
抵抗を印刷して基板とし、該基板に電子部品を搭載した
ことを特徴とする複合電子部品。
6. The method according to any one of claims 1 to 5,
A composite electronic component, wherein a conductor and a thick film resistor are printed on a surface of a laminate constituting the composite electronic component to form a substrate, and the electronic component is mounted on the substrate.
JP07152713A 1995-05-26 1995-05-26 Composite electronic components Expired - Fee Related JP3092693B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07152713A JP3092693B2 (en) 1995-05-26 1995-05-26 Composite electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07152713A JP3092693B2 (en) 1995-05-26 1995-05-26 Composite electronic components

Publications (2)

Publication Number Publication Date
JPH08330187A true JPH08330187A (en) 1996-12-13
JP3092693B2 JP3092693B2 (en) 2000-09-25

Family

ID=15546535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07152713A Expired - Fee Related JP3092693B2 (en) 1995-05-26 1995-05-26 Composite electronic components

Country Status (1)

Country Link
JP (1) JP3092693B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0910163A1 (en) * 1997-09-08 1999-04-21 Murata Manufacturing Co., Ltd. Oscillator module
EP1010543A1 (en) * 1996-12-27 2000-06-21 Rohm Co., Ltd. Card mounted with circuit chip and circuit chip module
US7263764B2 (en) 2001-09-05 2007-09-04 Avx Corporation Method for adjusting performance characteristics of a multilayer component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1010543A1 (en) * 1996-12-27 2000-06-21 Rohm Co., Ltd. Card mounted with circuit chip and circuit chip module
EP1010543A4 (en) * 1996-12-27 2005-06-01 Rohm Co Ltd Card mounted with circuit chip and circuit chip module
EP0910163A1 (en) * 1997-09-08 1999-04-21 Murata Manufacturing Co., Ltd. Oscillator module
US7263764B2 (en) 2001-09-05 2007-09-04 Avx Corporation Method for adjusting performance characteristics of a multilayer component

Also Published As

Publication number Publication date
JP3092693B2 (en) 2000-09-25

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