JPH0250448A - Semiconductor integrated circuit measuring apparatus - Google Patents

Semiconductor integrated circuit measuring apparatus

Info

Publication number
JPH0250448A
JPH0250448A JP63201202A JP20120288A JPH0250448A JP H0250448 A JPH0250448 A JP H0250448A JP 63201202 A JP63201202 A JP 63201202A JP 20120288 A JP20120288 A JP 20120288A JP H0250448 A JPH0250448 A JP H0250448A
Authority
JP
Japan
Prior art keywords
wafers
measured
wafer
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63201202A
Other languages
Japanese (ja)
Other versions
JP2752642B2 (en
Inventor
Kenichi Nagatome
永留 賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP63201202A priority Critical patent/JP2752642B2/en
Publication of JPH0250448A publication Critical patent/JPH0250448A/en
Application granted granted Critical
Publication of JP2752642B2 publication Critical patent/JP2752642B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the time for changing lots and improve the process capability for one IC tester by a method wherein the program names of products stored in the order of measurement are successively selected by comparing wafer END signals from a prober with the number of wafers wherein the types of wafers are to be changed and the wafers are continuously measured. CONSTITUTION:A measuring apparatus which judges a semiconductor integrated circuit to be acceptable or not has a register 11 in which the program names of products to be measured continuously are stored, a selecting circuit 12 which selects the program names stored in the register and a timing circuit 15 which counts wafer END signals outputted from a wafer prober 2 and outputs timings wherein different types of wafers are to be measured. Therefore, in order to measure two or more types of wafers continuously, the number of the wafers and the program names of the respective types are registered in the order of measurement and the END signal of the one type of the wafers outputted from the wafer prober 2 are counted and, when the counts reach the number of the wafers to be measured, the program name of the type to be measured next is selected. With this constitution, the continuous and different programs under the same measurement conditions can be started.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のウェハ状態での電気的特性試
験において、異なる品種のウェハを連続的に特性試験を
可能とする半導体集積回路測定装置(以下ICテスタと
呼ぶ)に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a semiconductor integrated circuit measuring device that enables continuous characteristic testing of different types of wafers in electrical characteristic testing of semiconductor integrated circuits in wafer state. (hereinafter referred to as an IC tester).

〔従来の技術〕[Conventional technology]

従来この種の特性試験は同一品種のウェハのみしか連続
的に特性試験を行うことができず、異品種のウェハを測
定するときは例え治工具が同一であったとしても再プロ
グラム入力等の段取りを行い測定を行っていた。
Conventionally, this type of characteristic test could only be performed continuously on wafers of the same type, and when measuring wafers of different types, even if the jigs and tools were the same, preparations such as reprogramming were required. and measurements were carried out.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

一近年ICの発達は目ざましいものがあり、ウニへ当り
の歩留り向上あるいはユーザからの特別注文による生産
(一般品でないため他ユーザへは販売できない)等の理
由により同一ロットにおける投入枚数は減少の方向にあ
るため、段取回数が増大し、単位設備あたりの生産量が
減少してきている。
In recent years, the development of ICs has been remarkable, and the number of ICs input in the same lot is decreasing due to reasons such as improved yield for sea urchins and production based on special orders from users (as they are not general products, they cannot be sold to other users). As a result, the number of setups has increased and the production volume per unit of equipment has decreased.

このような特別注文のICは一般的に1チツプマイコン
、ゲートアレーで代表されるごとく、回路構成は大部分
は共通であるにもかかわらず、−部ROM部等で異なる
ため、異品種扱いをしている。又測定プログラムも大部
分は共通で一部異なるのみである。
These custom-made ICs are generally represented by one-chip microcontrollers and gate arrays, and although most of the circuit configurations are the same, they differ in the ROM part, etc., so they cannot be treated as different types. are doing. Also, most of the measurement programs are common, with only some differences.

従って、少量多品種の生産が今後益々増大する傾向にあ
り、現状の測定方式においては多大なフローアと設備投
資が必要となる欠点がある。
Therefore, the production of a wide variety of products in small quantities is likely to increase more and more in the future, and the current measurement method has the drawback of requiring a large amount of floor space and capital investment.

本発明の目的は前記課題を解決した半導体集積回路測定
装置を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit measuring device that solves the above problems.

〔発明の従来技術に対する相違点〕[Differences between the invention and the prior art]

上述した従来の1品種しか測定できないICテスタに対
し、本発明は2品種以上の連続して測定するための同−
品種内の測定枚数及びそのプログラム名を測定順に登録
することにより、ウェハブロービング装置(以下プロー
バと呼ぶ)からのウェハ単位のEND信号をカウントし
、測定枚数に達したら次の測定品種のプログラム名を選
択することで同一測定条件における連続して異なる品種
のプログラムをスタートさせることができるという相違
点を有する。
In contrast to the above-mentioned conventional IC tester that can only measure one type of IC tester, the present invention provides an IC tester that can continuously measure two or more types of IC testers.
By registering the number of wafers to be measured within a product type and its program name in the order of measurement, the END signal for each wafer from the wafer probing device (hereinafter referred to as a prober) is counted, and when the number of wafers to be measured is reached, the program name for the next product to be measured is registered. The difference is that by selecting , programs for different products can be started consecutively under the same measurement conditions.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明は半導体集積回路の良
・不良を判定する測定装置において、連続して測定する
製品のプログラム名を格納するレジスタと、該レジスタ
に格納されているプログラム名を選択する選択回路と、
ウェハ・プロービング装置からのウェハ・エンド信号を
カウントし、異品種のウェハを測定するタイミングを前
記選択回路に出力するタイミング回路とを有するもので
ある。
In order to achieve the above object, the present invention provides a measuring device for determining whether a semiconductor integrated circuit is good or bad, which includes a register for storing program names of products to be continuously measured, and a method for selecting a program name stored in the register. a selection circuit to
The apparatus includes a timing circuit that counts wafer end signals from a wafer probing device and outputs timing for measuring different types of wafers to the selection circuit.

〔実施例〕〔Example〕

以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

図において、1はICテスタ本体であり、該ICテスタ
本体1はDC,BS発生器3、タイミング発生器4、パ
ターン発生器5、CPU6、cpUメモリ7、パターン
メモリ8、信号発生回路9、ピンカード10、品名レジ
スタ11、品名レジスタ選択回路12、品種切替ウェハ
枚数レジスタ13、ウェハ測定枚数カウンタ14、一致
回路15、外部接続インターフェース16を含む、2は
ブローバであり、該プローバ2はプローバ・10一ビン
グ回路17、ブローバ・コントロール回路18、ブロー
バ・ローダ・アンローダ回FI!119を含む。
In the figure, 1 is an IC tester main body, and the IC tester main body 1 includes a DC, BS generator 3, a timing generator 4, a pattern generator 5, a CPU 6, a cpU memory 7, a pattern memory 8, a signal generation circuit 9, and a pin. It includes a card 10, a product name register 11, a product name register selection circuit 12, a product type switching wafer number register 13, a wafer measurement number counter 14, a coincidence circuit 15, and an external connection interface 16. 2 is a blower; Bing circuit 17, blower control circuit 18, blower loader/unloader times FI! 119 included.

被測定ウェハのプログラムはCPU6を介し周辺機器よ
りCP’Uメモリ7へ格納され、そのとき必要な数本の
パターンはパターンメモリ8へ格納される。これを連続
した異なる晶・種分全てのプログラム及びパターンを該
当メモリへ格納する。
The program for the wafer to be measured is stored in the CPU'U memory 7 from peripheral equipment via the CPU 6, and several patterns required at that time are stored in the pattern memory 8. The programs and patterns for all consecutive different crystals and species are stored in the corresponding memory.

次に測定するウェハの品種毎のプログラム名のみを測定
順通りに品名レジスタ11へ登録し、更に品種が変わる
ウェハの番号を品種切替ウェハ枚数レジスタ13へ登録
しておく。
Next, only the program name for each type of wafer to be measured is registered in the product name register 11 in the order of measurement, and furthermore, the number of the wafer whose type changes is registered in the type switching wafer number register 13.

ICテスタ本体1をスタートさせることにより異なる品
種のウェハが1枚ずつ10−バ・ローダ・アンローダ1
9よりブロービング回路17へ運ばれ、ウェハ上のベレ
ットをICテスタの各種回路を使用し、測定される。
By starting the IC tester body 1, 10-bar loader/unloader 1 loads different types of wafers one by one.
9 to the probing circuit 17, and the pellet on the wafer is measured using various circuits of the IC tester.

ウェハ1枚測定終了するごとに、ブローバ2のプローバ
・コントロール回路18よりICテスタ1の外部接続イ
ンタフェース回路16ヘウエハ・エンド信号が送られ、
その信号をカウントすることにより現測定枚数をチエツ
クし一致回路15で判定し、次の測定ウェハが異なる品
種のウェハに該当するならば、既に設定された次の品種
のプログラム名が品名レジスタ11より選ばれて異なる
品種を連続的に測定することが可能となる。
Every time one wafer is measured, a wafer end signal is sent from the prober control circuit 18 of the blower 2 to the external connection interface circuit 16 of the IC tester 1.
By counting the signal, the current number of measured wafers is checked and determined by the coincidence circuit 15. If the next measured wafer corresponds to a different type of wafer, the already set program name of the next type is read from the product name register 11. It becomes possible to continuously measure different selected varieties.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は測定順に格納された製品の
プログラム名をプローバからのウェハ・エンド信号と品
種切替ウェハ枚数を比軟することにより、順次選択し、
連続した異品種のウェハをICテスタを停止させること
なく、連続的に測定することによりロット切替時間を短
縮させ、ICテスタ1台あたりの処理能力を向上させる
効果がある。
As explained above, the present invention sequentially selects the program names of products stored in the measurement order by comparing the wafer end signal from the prober and the number of wafers to be changed.
Continuously measuring wafers of different types without stopping the IC tester has the effect of shortening the lot changeover time and improving the throughput per IC tester.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図である。 1・・・ICテスタ本体  2・・・プローバ3・・・
DC,BS発生器 4・・・タイミング発生器5・・・
パターン発生器  6・・・CPU7・・・CPUメモ
リ   8・・・パターンメモリ9・・・信号発生回路
   10・・・ピンカード11・・・品名レジスタ 12・・・品名レジスタ選択回路 13・・・品種切替ウェハ枚数レジスタ14・・・ウェ
ハ測定枚数カウンタ 15・・・−数回路 16・・・外部接続インターフェース
FIG. 1 is a block diagram showing one embodiment of the present invention. 1...IC tester body 2...Prober 3...
DC, BS generator 4...timing generator 5...
Pattern generator 6...CPU7...CPU memory 8...Pattern memory 9...Signal generation circuit 10...Pin card 11...Product name register 12...Product name register selection circuit 13... Type switching wafer number register 14...Wafer measurement number counter 15...-number circuit 16...External connection interface

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路の良・不良を判定する測定装置に
おいて、連続して測定する製品のプログラム名を格納す
るレジスタと、該レジスタに格納されているプログラム
名を選択する選択回路と、ウェハ・プロービング装置か
らのウェハ・エンド信号をカウントし、異品種のウェハ
を測定するタイミングを前記選択回路に出力するタイミ
ング回路とを有することを特徴とする半導体集積回路測
定装置。
(1) A measuring device for determining whether semiconductor integrated circuits are good or bad includes a register that stores program names of products to be continuously measured, a selection circuit that selects the program name stored in the register, and a wafer A semiconductor integrated circuit measuring device comprising: a timing circuit that counts wafer end signals from a probing device and outputs timing for measuring different types of wafers to the selection circuit.
JP63201202A 1988-08-12 1988-08-12 Semiconductor integrated circuit measuring device Expired - Lifetime JP2752642B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63201202A JP2752642B2 (en) 1988-08-12 1988-08-12 Semiconductor integrated circuit measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63201202A JP2752642B2 (en) 1988-08-12 1988-08-12 Semiconductor integrated circuit measuring device

Publications (2)

Publication Number Publication Date
JPH0250448A true JPH0250448A (en) 1990-02-20
JP2752642B2 JP2752642B2 (en) 1998-05-18

Family

ID=16437040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63201202A Expired - Lifetime JP2752642B2 (en) 1988-08-12 1988-08-12 Semiconductor integrated circuit measuring device

Country Status (1)

Country Link
JP (1) JP2752642B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072239A (en) * 1983-09-28 1985-04-24 Fujitsu Ltd Testing method for semiconductor device
JPS63179267A (en) * 1987-01-21 1988-07-23 Tokyo Electron Ltd Measuring instrument for many kinds of articles

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072239A (en) * 1983-09-28 1985-04-24 Fujitsu Ltd Testing method for semiconductor device
JPS63179267A (en) * 1987-01-21 1988-07-23 Tokyo Electron Ltd Measuring instrument for many kinds of articles

Also Published As

Publication number Publication date
JP2752642B2 (en) 1998-05-18

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