JPH0250396A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the load of a main word line and to contrive high speed by linking a sub-word line constituting each sub-memory array through a sub- word line driving circuit such as a correspondingly provided inverter line to a main word line. CONSTITUTION:A memory array MARY of a clocked static type RAM is divided into 32 sub-memory arrays SM 0 to SM 31 corresponding to each bit of memory data, and made into units. These sub-memory arrays SM 0 to SM 31 include orthogonally arranged sub-word lines and complementary data lines, and memory cells arranged in a grating condition at their intersections. The sub-word lines of the respective sub-memory arrays are respectively linked through a CMOS inverter circuit to inverted main word lines. Thus, the loads for the respective inverted main word lines are decreased, and driving ability of each sub-word line can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
On-chip clocked static RAM (Random Access Memory) installed in logic integrated circuits
This article relates to techniques that are particularly effective when used for such purposes.

[Conventional technology]

The memory array and peripheral circuits are 0MO3 (complementary MO3).
There is a CMOS static RAM configured according to 3), which achieves both high-speed operation and low power consumption. In addition, such CMOS static type RAM
There is a clocked static RAM which has a basic configuration of 1, and further reduces power consumption by making the peripheral circuitry dynamic. Furthermore, there are logic integrated circuits such as ASIC memories equipped with such locked static RAMs.

For clocked static RAM, for example,
It is described in JP-A-61-134985 and the like.

[Problem to be solved by the invention]

In logic integrated circuits and the like equipped with the above-mentioned clocked static RAM, memory speeds and capacities are increasing, and at the same time, so-called multi-bit design, in which multiple bits of stored data are simultaneously input and output, is being implemented. In such a logic integrated circuit, the memory array of the clocked static RAM includes a plurality of sub-memory arrays provided corresponding to each bit of storage data that is simultaneously input/output. The sub-word lines constituting each sub-memory array, each including a plurality of sub-word lines and data lines arranged in the form of a grid, and a plurality of memory cells arranged in a lattice at the intersections of these sub-word lines and data lines, are The main word line is directly coupled to the main word line arranged parallel to the sub word line of and passing through each sub memory array, and is selectively selected by the X address decoder.

However, it has become clear that the clocked static type RAM has the following problems. That is, in the above-mentioned clocked static RAM, the memory array is constituted by a plurality of sub-memory arrays, as described above, and the plurality of sub-word lines constituting each sub-memory array are directly coupled to the main word line. . Therefore, as the number of bits in clocked static RAMs increases, the number of sub-word lines coupled to a main word line increases, and the load on each main word line increases. This limits the speeding up of clocked static RAMs, and together with the miniaturization of word lines, increases the possibility of wire breakage due to electro-migration silencing, reducing its reliability.

In addition, when standardizing the design of memory arrays, the driving capacity of the main word line must be increased to accommodate the maximum focus configuration, resulting in higher integration and lower cost of clocked static RAM. This limits the flexibility of its bit configuration.

An object of the present invention is to provide a semiconductor memory device such as a clocked static RAM that reduces the load on the main word line and increases the speed of operation. Another object of the present invention is to reduce the cost of a semiconductor memory device such as a clocked static RAM and to increase flexibility in bit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory array such as a clocked static RAM is divided into a plurality of sub-memory arrays that are unitized according to the focus configuration, and the sub-word lines forming each sub-memory array are connected to corresponding inverter circuits. It is connected to the main word line through a sub-word line drive circuit such as.

[For production]

According to the above-mentioned means, it is possible to reduce the load on the main word line and increase the driving ability of each sub-word line, so it is possible to increase the speed of clocked static RAM and to reduce its cost. , it is also possible to increase flexibility regarding the focus configuration.

〔Example〕

FIG. 1 shows a circuit block diagram of an embodiment of a clocked static RAM to which the present invention is applied. Further, FIG. 2 shows a circuit diagram of an embodiment of the sense amplifier SA of the clocked static RAM shown in FIG. 1. An overview of the configuration and operation of the clocked static RAM of this embodiment, as well as its characteristics, will be described with reference to these figures. The clocked static RAM of this embodiment is a so-called on-chip RAM mounted on a logic integrated circuit, and the circuit elements constituting each circuit element and each block shown in FIGS. 1 and 2 are as follows. Together with other circuit elements (not shown) of a logic integrated circuit, it is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon. In the diagram below,
MO with an arrow added to the channel (back gate) part
The SFET is a P-channel type, and is distinguished from the N-channel MO5FET, which is not marked with an arrow. Furthermore, explanations of the configurations and operations of blocks other than the clocked static RAM of the logic integrated circuit will be omitted.

The clock static type RAM of this embodiment is a so-called multi-pint RAM that simultaneously inputs and outputs 32-bit Elf'-data, although this is not particularly limited. Therefore, the clocked static RAM memory array MARY is divided and unitized into 32 sub-memory arrays SMO to 5M31 provided corresponding to each bit of the storage data. These sub-memory arrays are
As will be described later, each sub-memory array in this embodiment includes sub-word lines and complementary data lines arranged orthogonally, and memory cells arranged in a grid at the intersections of these sub-word lines and complementary data lines. The sub-word lines are respectively coupled to corresponding inverted main word lines via corresponding word line drive circuits, that is, CMOS inverter circuits. As a result, in the clocked static RAM of this embodiment, the load on each inverted main word line is reduced, and the driving capability of each sub-word line is increased.

In the clocked static RAM of this embodiment, the column switch C8W and Y address decoder YAD that constitute the column selection circuit are 32 sub-column switches ss provided corresponding to the sub-memory arrays SMO to SM31.

~SS31 and sub address decoder 5YDO~5
Divided and unitized into YD31. These sub-column switches and sub-address decoders, together with the sub-memory arrays SMO to 5M31, are added or deleted as appropriate in accordance with the bit configuration of the clocked static RAM. As a result, the clocked static RAM of this embodiment has increased flexibility regarding the bit configuration, that is, the system configuration.

Furthermore, the clocked static type RAM of this embodiment
In this case, a complementary common data line for reading and a complementary common data line for writing are provided separately.

Among these, the complementary common data line for reading is a P-channel type switch MO provided in column switch C8W.
It is selectively connected to a designated complementary data line via a 5FET. And clocked static RAM
When the line is in a non-selected state, it is precharged to a high level similar to the power supply voltage of the circuit, similarly to the complementary data line. On the other hand, the complementary common data line for writing is an N-channel switch MOS provided in the column switch C8W.
It is selectively connected to a designated complementary data line via a FET. When the clocked static type RAM is brought into a non-selected state, it is precharged to a low level such as the ground potential of the circuit. from these things,
In the clocked static RAM of this embodiment, the readout circuit including the P-channel switch MOSFET is replaced by the N-channel switch MOSFET.
Since it can be optimally designed separately from the write circuit including T, the read operation can be speeded up. Further, by precharging the complementary common data line for hot weather to a low level, the precharge level of the complementary data line is canceled out during a write operation, so that the write operation can be speeded up.

In FIG. 1, sub-memory arrays SMO to 5M31 constituting memory array MARY are parallel in the vertical direction to m+1 sub-word lines SWO to SWm arranged in parallel in the horizontal direction in the figure, although not particularly limited. n+1 sets of complementary data lines DO, DO to Dn-Dn arranged as a line, and (m+1) x (n+1) static memory cells MC arranged at the intersections of these word lines and complementary data lines, respectively. include.

Each memory cell MC constituting sub-memory arrays SMO to SM31 includes, but is not particularly limited to, a P-channel MOSFETQ5, an N-channel MO5FETQ21, and a P-channel MOSFETQ21, as exemplarily shown in FIG.
These CMOS inverter circuits consist of SFETQ6 and N-channel MOSFETQ22.
The MOS inverter circuit has its input terminals and output terminals cross-connected to each other, thereby forming a latch that serves as a storage element of a clock-to-state RAM. Further, the commonly coupled input terminals and output terminals of these CMOS inverter circuits are used as input/output nodes of each launch.

The input/output nodes of the latches of m+1 memory cells MC arranged in the same column of sub-memory arrays SMO to SM31 are connected to the corresponding complementary data lines DO and DO through N-channel type transmission gate MOSFETs Q23 and Q24.
Dn - Dn, respectively, are commonly bonded. Further, f arranged in the same row of sub-memory arrays SMO to SM31
The above transmission gate MOSFE of i+1 memory cells MC
The gates of TQ23 and Q24 are commonly coupled to corresponding sub-word lines SWO to SWm, respectively.

The memory array MARY further passes through the sub-memory arrays SMO to 5M31 and connects to the sub-word line SW.
It includes m+1 inverted main word lines WO to Wm arranged in parallel to O to SWm. Although not particularly limited, these inverted main word lines can be connected to CMs provided correspondingly.
The corresponding sub-word line SWO of each sub-memory array is connected via the OS inverter circuits N1-N2 or N3-N4.
The 0-inverted main word lines Wτ to W, which are respectively commonly coupled to S W m, are coupled to the X address decoder XAD on the other hand, and are alternatively set to a selected state of low level.

By the way, the clocked static type RA of this embodiment
At M, the ground potential supply point of each memory cell MC, that is, M
The sources of OSFETs Q21 and Q22 are commonly coupled to corresponding ground potential supply lines VSO to VSm, respectively.

These ground potential supply lines are arranged parallel to the corresponding inverted main word lines WO to Wm. Also, all are commonly coupled at one end, and further P channel MOS
FETQI 1 and N channel/IzMOSFETQ2
9 to the circuit ground potential. MOSFE
The TQII is always turned on by having its gate coupled to the ground potential of the circuit. Also, MO5FETQ
The internal control signal rm is supplied to the gate of 29 from the timing generation circuit TG. Here, internal control signal rm
is selectively set to a high level when the clocked state ink type RAM is in a selected state in the read mode.

For these reasons, the ground potential for the memory cell MC is set to the ground potential of the circuit when the clocked static RAM is in the read mode, and is set to the ground potential of the circuit when the clocked static RAM is in the non-selected state or in the write mode. When in the selected state, it is set to an intermediate level higher than the ground potential of the circuit by the threshold voltage of MOSFETQll. Thereby, it is possible to promote lower power consumption of the clock-to-state RAM without affecting the read operation.

The X address decoder XAD has an X address buffer
Complementary internal address signal axQ- of t+1 bits from AB
axi (here, for example, non-inverted internal address signal axQ
and the inverted internal address signal axO are collectively expressed as a complementary internal address signal axQ (hereinafter the same) is supplied,
Timing signal φca is supplied from timing generator circuit TO. Here, the timing signal φce is set to a high level at a predetermined timing when the clocked static type RAM is brought into a selected state. In addition, although there are no particular limitations, black 7 cluster type 1'? AM is brought into a selected state in the read mode, and when the sense amplifier SA finishes amplifying the read signal and the logic level of its output signal is determined, it is forcibly returned to the low level.

The X address decoder XAD receives the timing signal φc
By setting e to a high level, it is selectively put into an operating state. In this operating state, the X address decoder
D decodes the complementary internal address flt xo to axi, and selectively sets the corresponding inverted main word lines WO to Wm of the memory array MARY to a selected state of low level. Needless to say, when the above-mentioned inverted main word lines WO to Wm are set to a selected state of low level, the corresponding sub word lines SWO to SWm of each sub memory array
are simultaneously set to a high level selection state.

As described above, when the amplification operation of the read signal by the sense amplifier SA is completed and the timing signal φCe is set to a low level, the operation of the X address decoder XAD is stopped. As a result, the X address decoder XAD is kept in an operating state for the minimum necessary period, and the clocked static type 1? Lower power consumption of AM will be promoted.

The X address buffer XAB is connected to the address input terminal AXO.
It takes in the l+l focused X address signal AXO to AXi supplied via AXi and holds it. Also, based on these X address signals AXO to AXI, the complementary internal address signals axQ to axi are formed and supplied to the X address decoder XAD.

On the other hand, sub memory array SMO of memory array MARY
~ Complementary data lines DO/DO ~ Dn- configuring SM31
Dn is not particularly limited, but on the other hand, the corresponding P-channel precharge MOSFET QI.
It is coupled to the power supply voltage of the circuit via Q2 to Q3 and Q4,
On the other hand, the corresponding switch MOS FETQ of the sub-column switch SSO~5831 corresponding to the column switch C8W? - Connected to Q25 and Q8/Q26 or Q9/Q27 and QIO/Q28, respectively.

The above-mentioned timing signal φco is commonly supplied from the timing generation circuit TG to the gates of the precharge MO5FETs QI.Q2 to Q3.Q4.

The MOSFETs QI-Q2 to Q3-Q4 are selectively turned on when the clocked static RAM is de-selected and the timing signal φee is set to low level, and the corresponding complementary data lines are turned on. D.O.
- Precharge the non-inverted signal line and inverted signal line of DO-Dn-Dn to a high level like the power supply voltage of the circuit.

When the clocked static RAM is selected and the timing signal φco is set to a high level, all of these precharge MOSFETs are turned on.

As described above, column switch C8W includes 32 sub-column switches SSO-5S31 provided corresponding to sub-memory arrays SMO-SM31.These sub-column switches include, but are not particularly limited to, complementary data lines DO・Provided corresponding to π1~Dn・Dn (n+
1) Pair of complementary switch MOSFETs Q7, Q25 and Q
One of these switch MOSFETs, including 8.Q26 to Q9.Q27 and QIO.Q28, respectively, is coupled to the corresponding complementary data line DO.DO.about.Dn-Dn of the corresponding sub-memory array SMO.about.SM31, respectively. , and the other are commonly coupled to the corresponding complementary common data line for reading or complementary common data line for writing, respectively. In other words, P-channel type switch MO5FETQ7・Q8~Q9・QI of each sub-column switch
The other side of O is the corresponding complementary common data line CR for reading.
O to CR31 (here, for example, non-inverted common data line CR
0 and the inverted common data line CRO are collectively expressed as a complementary common data line for reading CRO.

(the same applies hereafter) are commonly connected to each other. Similarly, N-channel type switch MOSFETQ25・Q26~Q2
The other terminals of 7 and Q2B are commonly coupled to the corresponding write complementary common data line -Ω-WO-CW31.

P-channel type switch MO of each sub-column switch
5FETQ? - The gates of Q8 to Q9 and QIG are commonly coupled, and corresponding inverted data line selection signals YRO to YRn are supplied from corresponding sub address decoders 5YDO to 5YD31 of Y address decoder YAD, respectively.

Similarly, N-channel type switch MOSFETQ25
- The gates of Q26 to Q27 and Q28 are commonly coupled, and corresponding data line selection signals YWO to YWn are supplied from corresponding sub-address decoders 5YDO to 5YD31 of Y address decoder YAD, respectively.

P-channel type switch MOSFETQ of sub-column switch SSO~5S31?・Q8～Q9・QIO is
When the clocked static RAM is set to read mode, the corresponding inverted data line selection signal YRO=
When YRn is alternatively set to a low level, it becomes an on state, and selects the corresponding complementary data lines DO/Do to Dn-Dn of sub-memory arrays SMO to 5M31 and the corresponding complementary common data lines for reading CRO to CR31. Connect to. As a result, a total of 32 memory cells MC, one from each sub-memory array, are selected at the same time, and the sub-column switches SSO to 5S31 are connected to the corresponding unit circuits of the sense amplifier SA. N-channel type switch MO5FETQ25/Q26~Q
27 and Q28 are turned on when the clocked static RAM is set to the write mode, when the corresponding data line selection signal YW O" Y W n is alternatively set to a high level, and the submemory Array SMO
~Corresponding complementary data line DO/DO~Dn- of SM31
Complementary common data lines CWO to C for writing corresponding to Dn
W31 is selectively connected.

As a result, 1 ? from each sub-memory array. A total of 32 memory cells MC are selected at the same time in increments of if, and connected to the corresponding unit circuits of the write amplifier WA.

In the clocked static RAM of this embodiment, as described above, the read system circuit and the write system circuit are provided separately, so that the P-channel type switch MOSFET Q7, Q8 to Q9, QI included in the read system circuit is
The size of O can be limited to the minimum necessary size. In addition, N-channel type switch MOSFETQ25/Q26, which is included in the write system circuit and requires a relatively large size,
~Q27 and Q28 are complementary common data lines for reading
Therefore, the load on the read complementary common data lines -CRO to CR31 is reduced, and the read operation of the clock static RAM is further accelerated.

Sub address decoder 5Y of Y address decoder YAD
DO to 5YD31 are commonly supplied with j+l bits of complementary internal address signals yO to ayj from the Y address buffer YAB, although this is not particularly limited. Further, the timing signal φce described above is output from the timing generation circuit TG.
and internal control signal rm are commonly supplied.

Sub address decoder 5Y of Y address decoder YAD
DO to 5YD31 are selectively brought into operation when the timing signal φCS is set to a high level. In this operating state, clocked static RAM
is in the write mode and the internal control signal rm is at a low level, sub address decoders 5YDO to 5YD
31 decodes the complementary internal address signal yO-ayj to generate the corresponding data line selection signal yw o -y
Wn is alternatively set to high level. On the other hand, in the above operating state, when the clocked static type RAM is in the read mode and the internal control signal rm is at a high level, the sub address decoder 5YDON5YD31 of the Y address decoder YAD outputs the complementary internal address signal a.
yO to ayj are decoded, and the corresponding inverted data line selection signals YRO to YRn are alternatively set to low level.

At this time, when the amplification operation of the read signal by the sense amplifier SA is completed and the timing signal φce is set to a low level, the operations of the sub-address decoders 5YDO to 5YD31 are forcibly stopped. As a result, the power consumption of the clocked static RAM can be further reduced.

The complementary common data for writing HAcwo to W31 are respectively coupled to the output terminals of the corresponding unit circuits of the write amplifier WA. The input terminal of each unit circuit of write amplifier WA is coupled to the output terminal of the corresponding unit circuit of data input buffer DIB. Data input buffer D
The input terminals of each unit circuit of IB are further coupled to corresponding data input/output terminals DO to D31, respectively. Although not particularly limited, the write amplifier WA is supplied with the above-mentioned timing signal φce and timing signal φwe from the timing generation circuit TG. Here, the timing signal φwe is temporarily set to a high level at a predetermined timing when the clocked static type RAM is brought into a selected state in a write operation mode.

The data input buffer DIR includes 32 unit circuits provided corresponding to the write complementary common data lines CWG to CW31. 32-bit write data supplied from the outside via data input/output terminals DO to D31 is taken in and transmitted to the corresponding unit circuit of the write amplifier WA.

Similarly, the write amplifier WA includes 32 unit circuits provided corresponding to the complementary common data for writing 1jlcWO to CW31. By setting it to the level, it is selectively put into an operating state. In this operating state, the light amplifier WA
Each unit circuit uses the write data transmitted via the data input buffer DIB as a complementary write signal,
Corresponding complementary common data lines for writing WO to W31
is supplied to selected memory cells MC of sub-memory arrays 5M0-3M31. Timing signal φW6
is set to a low level, the output of each unit circuit of the write amplifier WA is set to a high impedance state.

In the clocked static RAM of this embodiment, each unit circuit of the write amplifier WA is provided between the non-inverted signal line and the inverted signal line of the write complementary common data lines WO to CW31 and the ground potential of the circuit. An inverted signal of the timing signal -C6 is commonly supplied to the gates of these precharge MOSFETs including the N-channel precharge MOSFET. As a result, the writing complementary common data lines CWO to CW31 are
When the quad static type RAM is brought into a non-selected state and the timing signal φCe is set to a low level, it is precharged to a low level such as the ground potential of the circuit. As mentioned above, the complementary data lines DO and DO~ that constitute the sub memory array SMO~5M31 of the memory array MARY
Dn-Dn is precharged to a high level similar to the power supply voltage of the circuit when the clocked static RAM is in a non-selected state. Clocked static type R
When AM is selected in the write mode and the designated complementary data lines Do-DO to Dn-Dn and the complementary common data lines for writing WO to W31 are connected, these complementary data lines and the writing The precharge levels of the complementary common data lines are canceled and become an intermediate level.

As a result, the levels of the complementary data line and the write complementary common data line are quickly fully swung according to the write data. This further speeds up the writing operation of the clocked static RAM.

On the other hand, the complementary common data lines for reading CRO to C-R31
are respectively coupled to the input terminals of the corresponding unit circuits of the sense amplifier SA. The output terminal of each unit circuit of the sense amplifier SA is coupled to the input terminal of the corresponding unit circuit of the data output cover 7-FA DOB. The output terminals of each unit circuit of the data output buffer DOB are further commonly coupled to the corresponding data input/output terminals DO to D31.The sense amplifier SA includes a timing generation circuit T.
The above-mentioned timing signal φce and timing signal -sa are supplied from G, and the timing signal -〇〇 is supplied to the data output cover DOB. Here, the timing signals φSa and φoe are used when the clocked static RAM is in the selected state in the read mode.
Each is set to a high level at a predetermined timing. The timing signal φ3a, like the timing signal φce,
When the sense amplifier SA finishes amplifying the read signal and the logic level of the output signal is determined, the output signal is forced to a low level.

The sense amplifier SA includes, but is not particularly limited to, 32 unit circuits, that is, unit sense amplifiers USAO to USA31, provided corresponding to the complementary common data lines RO to R31 for reading, as shown in FIG. , unit sense amplifiers USAO to USA31 include, but are not particularly limited to, a precharge circuit PC, a level shift circuit LS, a sense circuit SC, and an output latch OL, as represented by the unit sense amplifiers USAO and USA31, respectively.

The precharge circuit PC of the unit sense amplifier tJsAo~USA31 is provided between the non-inverted signal line and the inverted signal line of the read complementary common data line CRO~-Ω-R31 and the power supply voltage of the circuit, although it is not particularly limited. The gates of these precharge MOSFETs including P-channel type precharge MOSFETs Q12 and Q13 are all commonly coupled, and the timing signal φce is supplied from the timing generation circuit TO. As a result, the precharge MOSFETs QI2 and Q13 are selectively turned on when the clocked static RAM is in a non-selected state and the timing signal φcs is set to a low level, and the corresponding complementary common data lines CRO to CR31 for reading are turned on. The non-inverted signal line and the inverted signal line are precharged to a high level such as the power supply voltage of the circuit.

The level shift circuit LS of the unit sense amplifiers USAO to υ5A31 includes, but is not particularly limited to, a pair of N-channel MOSFETs Q30 and Q31 in a differential configuration, and another pair of N-channel MOSFETs Q32 and Q33 provided on the source side of these MOSFETs. including
The drains of MOSFETs Q30 and Q31 are coupled to the circuit power supply voltage, and the commonly coupled sources of MOSFETs Q32 and Q33 are connected to the N-channel drive MOSFET.
It is coupled to the circuit ground potential via ETQ34. M.O.
The gates of the 5FETs Q30 and Q31 are respectively coupled to the non-inverted signal line and the inverted signal line of the corresponding read complementary common data lines RO-R31. MOSFETQ
The gate of 32 is coupled to its drain and further connected to the MO
Commonly coupled to the gates of S F ETQ 33. As a result, MOSFETs Q32 and Q33 are placed in a current mirror configuration. The gate of IItMO5FETQ34 receives the timing signal φ3 from the timing generation circuit TG.
a is commonly supplied. MO5FETQ3G and Q31
The source potential of is the complementary read signal 3dO-sdo~5
The signals d31 and 5d31 are supplied to the corresponding sense circuits SC.

The level shift circuits LS of the unit sense amplifiers USAO to USA31 are selectively brought into operation when the clocked static RAM is brought into a selected state in the read mode and the timing signal φSa is brought to a high level. At this time, MOSFETQ3 of the level shift circuit LS
A predetermined voltage is applied to the gates of 0 and Q31 from the selected memory cell MC of the corresponding sub-memory array SMO to 5M31 of the memory array MARY via the corresponding complementary common data line for reading -Ω-RO to -Ω, R31. A readout signal is supplied. As described above, when the clocked static RAM is in the non-selected state, the complementary data lines DO/DO to Dn-Dn of each sub-memory array and the complementary common data lines fRo to DanR31 for reading are connected to the circuit power supply. It is precharged to a high level like voltage.

Therefore, since the read signal has its center level at a relatively high level close to the power supply voltage of the circuit, both MOSFETs Q30 and Q31 of the level shift circuit LS are turned on. This allows MOSFETQ30
and the source potential of Q31, that is, the complementary read signal sd
o ・sdo~5ti31 ・5d31 are MOSFE
TQ30 and Q32 or MOSFETQ31 and Q33
It changes in phase with the readout signal, centering on a predetermined bias level determined by the conductance ratio of .

That is, in this embodiment, the read signal transmitted via the read complementary common data lines CRO to CR31 has its DC level shifted to the lower voltage side by the corresponding level shift circuit LS, so that the read signal is transferred to the sense circuit SC.
It is assumed that the effective bias level is such that the sensitivity is maximized.

Sense circuit S of unit sense amplifier υSAO~USA31
C is not particularly uniform, but has two pairs of N that are in differential form.
Channel MOSFET Q35 and Q37 and Q3
6 and Q38, and three P-channel MOSFETs QI 4~ provided on the drain side of these MOSFETs.
Including Q16.

The sources of MOSFETQI4 to Q16 are coupled to the power supply voltage of the circuit, and an N-channel drive MOSFETQ39 is provided between the commonly coupled sources of MOSFETQ35 to Q38 and the ground potential of the circuit.
The gate of ETQI 5 is coupled to its drain, which is further coupled to the gates of MOSFETs Q14 and QlB. As a result, MOSFETs QI 5 and Q14 and MOSFETs Q15 and QlB are configured as current mirrors, respectively.The gates of 0M03FETs Q35 and Q36 receive non-inverted output signals of the corresponding level shift circuits LS, that is, non-inverted read signals 3dO to 5d31, respectively. Supplied. Also, MOSFETQ37 and Q3
8, the inverted output signal of the corresponding level shift circuit LS, that is, the inverted readout signal sdO~3d3
1 is supplied respectively. The gate terminal of MOSFET Q39 is supplied with the timing signal φ3a.

The drain of MOSFET Q35 is further coupled to the input terminal of CMOS inverter circuit N5.

A P-channel type preset MOSFET Q17, which receives the timing signal φsa at its gate, is provided between the input terminal of the inverter circuit N5 and the power supply voltage of the circuit. The output signals of the inverter circuit N5 are non-inverted internal output signals dpo to dp31, respectively. Similarly, the drain of MOSFETQ38 is further connected to CMOS
It is coupled to the input terminal of inverter circuit N6. A P-channel type preset MOSFET Q18, which receives the timing signal φsa at its gate, is provided between the input terminal of the inverter circuit N6 and the power supply voltage of the circuit. The output signals of the inverter circuit N6 are non-inverted internal output signals dnO to dn31, respectively.

When the clocked static RAM is in a non-selected state or in a write mode, the timing signal φsa is applied.
is set to low level, the drive MO of the sense circuit SC
SFETQ39 is in the off state and the preset MOSF
ETQI 7 and QlB are turned on. Therefore, the sense circuit SC is rendered inactive, and the MOSFETQ
The drain potentials of 35 and Q38, that is, the inverted internal output signals apo-dp31 and dno-dn31, both tend to reach uncertain levels. However, as mentioned above, Precent MO5FETQI? and QlB are turned off, all of these inverted internal output signals are preset to a high level similar to the power supply voltage of the circuit. As a result, the output signals of inverter circuits N5 and N6, that is, non-inverted internal output signals dpo-dp31 and dnO
~dn31 are all determined to be low level.

When the clocked static RAM is selected in the read mode and the timing signal φ3a is set to high level, the drive MOSFET Q39 is turned on.
Bricent MOSFET Q17 and QlB are turned off. However, at 9, the sense circuit SC is activated,
An amplification operation of the read signal is performed. As a result, the levels of the inverted internal outputs nO to dn31 are changed in phase according to the corresponding complementary read signals 3dO and 3dO to ad31 and 5d31. That is, the corresponding complementary readout signals sdQ.
When it is set lower than d31, the corresponding inverted internal output signals dpQ to dp31 are set to high level, and the corresponding inverted internal output signals dnO to dn31 are set to low level.

As a result, the non-inverted internal output signals dpQ to dp31 are set to low level, and the non-inverted internal output signal dn.

~dn31 is set to high level. On the other hand, when the corresponding complementary read signals sdQ, sdO to 3d31, and 5d31 are set to logic "L" and the non-inverted signals sdO to 3d31 are made higher than the inverted signals sdO to ad31, the corresponding inverted internal output signals dpQ to dp31 become It is set to low level, and the corresponding inverted internal output signal dnO-dn31 is set to high level.

As a result, the non-inverted internal output signals dpQ to dp31 are set to high level, and the non-inverted internal output signals dn0 to dn31 are set to high level.
is considered to be low level.

Output latch O of unit sense amplifier USAO to USA31
The basic configuration of L is a latch formed by cross-connecting two CMOS inverter circuits N7 and N8. A commonly coupled node between the input terminal of the inverter circuit N7 and the output terminal of the inverter circuit N8 is used as an inverting input/output node of the output latch OL, and is coupled to the power supply voltage or ground potential of the circuit through N-channel MOSFETs Q40 and Q42, respectively. be done. The output signal of the inverter circuit N6, that is, the non-inverted internal output signals dnO to dn31 are respectively supplied to the gate of the MOSFET Q40, and the MOSFET
The output signal of the inverter circuit N5, that is, the non-inverted internal output signals dpO to dp31 are supplied to the gate of TQ42, respectively.

Similarly, the commonly coupled node of the output terminal of the inverter circuit N7 and the input terminal of the inverter circuit N8 is a non-inverting input/output node of the output latch OL, and
It is coupled to the circuit's power supply voltage or ground potential via SFETs Q41 and Q43, respectively. The gate of the MOSFET Q41 is supplied with the output signal of the inverter circuit N5, that is, the non-inverted internal output signals dpO to dp31, and the gate of the MOSFET Q43 is supplied with the output signal of the inverter circuit N6, that is, the non-inverted internal output signal dn.
Q to dn31 are respectively supplied. The potential of the non-inverting input/output node of the output lunch OL is the non-inverting internal output signal rd.
O''rd31 are supplied to the corresponding unit circuits of the data output buffer DOB.

Output latch O of unit sense amplifier USAO to USA31
L is not particularly limited, but may also be an OR gate circuit OG.
One input terminal of these OR gate circuits including I~OG2 receives the corresponding non-inverted internal output signal dpO~
dp31 are respectively supplied, and the corresponding non-inverted internal output signals dno to dn31 are supplied to the other input terminals, respectively. The output signals of the OR gate circuits 0GI-OG2 are respectively supplied to corresponding input terminals of the AND gate circuit AGI as internal signals dso-ds31. The output signal of the AND gate circuit AGI is supplied to the timing generation circuit TG as an internal control signal ads.

When the clocked static RAM is in a non-selected state or in a write mode, the inverter circuit N
5 output signal, that is, the non-inverted internal output signal dpo-dp
31 and the output signals of the inverter circuit N6, that is, the non-inverted internal output signals dnO to dn31, as described above,
Both are fixed at low level. Therefore, M.O.S.
FETs Q40-Q43 are all turned off, and the output latch OL continues to maintain its previous state. At this time, the output signals of the OR gate circuits oG1 to OG2, that is, the internal signals dsQ to ds31, are all set to a low level, so that the output signal of the AND gate circuit AGI, that is, the internal control signal ads is set to a low level. On the other hand, when the clocked static RAM is selected in the read mode, the output signal of the inverter circuit N5, that is, the non-inverted internal output signals ctp□ to dp31, is as described above.
The output signal of the inverter circuit N6, that is, the non-inverted internal output signal dno to dn31, is selectively set to high level on the condition that the corresponding read signal is logic "11".
is selectively set to high level on the condition that the corresponding read signal is logic "0". As a result, the corresponding output launch OL is forced into the cent or reset state. At this time, the non-inverted internal output signals dpo to dp
31 or dno to dn31 are selectively set to high level, the output signals of OR gate circuits oG1 to OG2, that is, internal signals dso to ds31 are set to high level all at once. Therefore, the output signal of the AND gate circuit AGI, that is, the internal control signal ad s is set to high level.

In other words, the clocked static type RAM of this embodiment
, the internal control signal ads is selectively set to high level when the clocked static RAM is selected in the read mode and the logic levels of the output signals of all unit sense amplifiers USAO to USA31 are determined. be done.

When the internal control signal ad3 is set to a high level, the timing generation circuit TO forcibly returns the timing signals φco and -aa, which were previously set to a high level, to a low level. As a result, the unit sense amplifier of the sense amplifier SA The operations of the level shift circuits LS and sense circuits SC of USAO to USA31 are stopped, and the operations of the X address decoders XAD and Y address decoders YAD are also stopped. Further, the precharge operation of the complementary common data lines CRO to CR31 for reading by the precharge circuit PC of the unit sense amplifiers USAO to υ5A31 of the sense amplifier SA is started, and the memory array M
A precharging operation of complementary data lines DO/Dθ~[)n-[)n of submemory arrays SMO~5M31 of ARY is started. This speeds up the recovery time of each read complementary common data line and complementary data line, speeds up the read operation of the clocked static RAM, and promotes lower power consumption.

Although not particularly limited, the data output buffer yDOB is a unit sense amplifier USAO to USA3 of the sense amplifier SA.
These unit circuits, including 32 unit circuits provided corresponding to 1, are selectively put into an operating state by setting the timing signal φ06 to a high level. In this operating state, each unit circuit of the data output sofa DOB has a corresponding unit sense amplifier U of the sense amplifier SA.
Output signals are formed according to non-inverted internal output signals rdo-rd31 output from SAO-USA31, and outputted via corresponding data input/output terminals DO-D31. Although not particularly limited, when the timing signal φos is set to a low level, the output of each unit circuit of the data output buffer sofa DOB is set to a zero impedance state.

The timing generation circuit TG receives a chip pull signal GE and a write enable signal W supplied as an m control signal.
Based on E, the various timing signals mentioned above are formed and supplied to each circuit. Further, when the internal control signal ad3 supplied from the sense amplifier SA is set to high level, -
The above-mentioned timing signals φas and φ are set to high level once.
Forcibly return sm to low level.

Figure 3 shows the clocked static RAM of Figure 1.
A timing diagram for one embodiment is shown. In the same figure,
The case where the clocked static type RAM is in the read mode is shown by a solid line, and the case where it is in the write mode is shown by a dotted line.

The outline of the operation and characteristics of the clocked static RAM of this embodiment will be explained with reference to FIG. fi3 and FIGS. 1 and 2 above.

In FIG. 3, the clocked static RAM is
Although not particularly limited, the selected state is achieved by changing the startup clock signal, that is, the chimbu enable signal CE, from a high level to a low level. Prior to this change of chimble enable signal CE to low level, write enable signal WE is set to high level or low level, and read mode or write mode is selectively designated.

Address input terminals AXO to AXI are supplied with X address large signals AXO-AXi in a combination specifying a row address rat-, and address input terminals AYO to AYJ are supplied with Y address signals AYO to AYj in a combination specifying a column address ca.
Supplied in combinations that specify. Further, when the clocked static type RAM is in the write mode, 32-bit write data is supplied to the data input/output terminals DO to D31.

By the way, when the chip enable signal 100 is set to high level, the clocked static type RAM is set to a non-selected state, and the timing signals φce and φsa are set to low level. Therefore, the ground potential supply line VSO~VS
m is set to an intermediate level, and inverted main word lines WO to Wm
is set to a high level non-selected state. Furthermore, in the memory array MARY, sense amplifier SA, and write amplifier WA, all precharge MO5FETs are turned on. Therefore, the sub-memory arrays SMO to SMO and the complementary common data lines for reading CRO to CR31 are both precharged to a high level similar to the circuit Li power supply voltage, and the complementary common data lines for writing WO to W31 are precharged to the high level of the circuit. is precharged to a low level similar to the ground potential of . Furthermore, in the output lunch OL of each unit sense amplifier of the sense amplifier SA, the preset MO5FETQ1? and QlB are in the on state, so the internal control signal ads
is considered to be low level.

When the chip enable signal CE is changed from a high level to a low level, in the clocked static RAM, the timing signal φco is first set to a high level. At this time, when the write enable signal WE is at a high level, the internal control signal rm is set at a high level, and the timing signals φsa and φos are sequentially set at a high level with a little delay. At this time, when the write enable signal WE is at a low level, the internal control signal rm is kept at a low level, and the timing signal φWe is temporarily set at a high level with a slight delay.

By setting the timing signal φC6 to high level, the complementary data lines Do and DOxDn-D of each sub-memory array
The precharge operation of n is stopped. In addition, the X address decoder XAD is activated, and the row address r
One inverted main word line W1 to W5 corresponding to a is alternatively set to a selected state of low level. As a result, in sub-memory arrays SMO-SM31, corresponding sub-word lines SWO-SW31 are alternatively set to a high-level selected state.

Here, when the clocked static RAM is in the write mode and the internal control signal rm is set to a low level, the ground potential supply line vso-vSm remains at an intermediate level. Furthermore, by setting the timing signal φce to a high level, the Y address decoder YAD enters the operating state, and the sub address decoders 5YDO to 5YD31
, data line selection signals YWO to YWn corresponding to column address ca are alternatively set to high level. As a result, a total of 32 memory cells MC are selected, one from each sub-memory array of memory array MARY, and the corresponding complementary common data line CWO-C for writing is selected.
The respective unit circuits of the write amplifier WA are connected via W31.

In each unit circuit of the write amplifier WA, the timing signal φ
By setting co to a high level, first, the precharging operation of the write complementary common data lines CWO to CW31 is stopped. Further, by setting the timing signal φwe to a high level, the complementary write signal corresponding to the write data supplied via the data input/output terminal Do-D31 is transmitted from each unit circuit of the write amplifier WA to the corresponding write complementary write signal. It is transmitted to the selected memory cell MC via common data lines CWO to CW31.

On the other hand, when the clocked static RAM is in the read mode and the internal filJ control signal rm is set to a high level, the ground potential supply lines SO to VSm are set to the ground potential of the circuit. In addition, by setting the timing signal φce to a high level, the Y address decoder YAD enters the operating state, and the sub address decoders 5YDO to 5Y
At D31, inverted data line selection signals YRO to YRn corresponding to column address ca are alternatively set to low level. As a result, a total of 32 memory cells MC are selected, one from each sub-memory array of the memory array MARY, and the corresponding unit sense of the sense amplifier SA is selected via the corresponding complementary common data lines CRO to CR31 for reading. The amplifiers USAO to USA31 are connected to each other.

As a result, the level of the non-inverted signal line or the inverted signal line of the complementary data lines DO-DO to Dn-Dτ and the complementary common data line flRO-flR31 for reading is selectively changed according to the data stored in the selected memory cell MC. be lowered.

These level changes are transmitted as read signals for each memory cell MC to the corresponding unit sense amplifiers USAO to USA31 of the sense amplifier SA.

Unit of sense amplifier SA Sense amplifier USAO~USA
31, the timing signal φCa is set to a high level, so that the complementary common data lines for reading are first RO to R.
31 is stopped and the timing signal φ3a is set to high level, so that the level shift circuit LS and the sense circuit SC are put into an operating state. The read signal transmitted via the read complementary common data lines CRO to flR31 is transmitted to the corresponding level shift circuit LS.
After their DC levels are shifted by the respective sense circuits SC, they are amplified by the corresponding sense circuits SC. the result,
Internal output signals rdO to rd31 are selectively set to high or low level depending on the logic level of the read signal of the corresponding memory cell MC. Also, the amplification operations of all unit sense amplifiers USAO to USA31 are completed,
When the logic level of the output signal is established, the internal control signal ads is set to high level.

In the timing generation circuit TG, the internal control signal ads
By setting the timing signals φce and φ3a to a high level, the timing signals φce and φ3a are forcibly returned to a low level. For this reason,
X address decoder XAD and Y address decoder YA
At the same time, the operation of level shift circuit LS and sense circuit SC in each unit sense amplifier of sense amplifier SA is stopped. Further, the precharging operation of the complementary data lines DO・■1 to Dn-Dn and the complementary common data lines for reading CRO to CR31 is started, and the internal output nodes dpO to dp31 and dnQ are started.
~dn31 preset operation is started. As a result, the recovery time of the complementary data line and the complementary common data line for reading of the clocked static RAM is shortened, and the speed of the read operation is increased.

The read data transmitted from the output lunch OL of each unit sense amplifier to the corresponding unit circuit of the data output buffer DOB as internal output signals rdQ to rd31 is transferred to the corresponding data input by setting the timing signal φoe to high level. It is output from output terminals DO to D31.

As described above, the clocked static type RAM of this embodiment is a so-called multi-bit RAM that inputs and outputs 32-bit storage data simultaneously. Therefore, the clocked static RAM memory array MARY
is 3 provided corresponding to each bit of the above storage data.
Two sub-memory arrays SMO-5M31 are provided, and a column switch C3W and a Y address decoder YAD are provided with 32 sub-column switches SSO-5S31 and sub-address decoders 5YDO-5YD31 provided corresponding to the sub-memory arrays. Each of the sub-memory arrays SMO to 5M31 includes a plurality of sub-word lines and complementary data lines arranged orthogonally to each other, and a plurality of memory cells arranged in a lattice at the intersections of these sub-word lines and complementary data lines. These sub-word lines are connected to word line drive circuits provided correspondingly, that is, CM
It is coupled to a corresponding inverted main word line via an OS inverter circuit. Further, these sub-memory arrays, sub-column switches, and sub-address decoders are unitized and selectively added or removed depending on the focus configuration of the clocked static RAM. For these reasons, in the clocked static RAM of this embodiment, the load on each inverted main word line is reduced, and drive circuits are provided for each sub-word line, thereby speeding up its operation. , disconnection of the main word line due to electro-migration can be prevented. Further, by unitizing the sub memory array, sub column switch, and sub address decoder, flexibility in focus configuration, that is, system configuration is increased.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a clocked static RAM having a multi-bit configuration, the following effects can be obtained. In other words, (a memory array such as a 17-clock static RAM is divided into a plurality of sub-memory arrays that are unitized according to the bit configuration, and sub-word lines constituting each sub-memory array are provided correspondingly. By coupling to the main word line via a sub-word line drive circuit such as an inverter circuit, the load on the main word line can be reduced.
The effect of increasing the driving ability of each sub-word line can be obtained.

(2) Item (1) above provides the effect of speeding up the word line selection operation of a clocked static RAM or the like.

(3) According to the above item (1), disconnection of the main word line due to electro-migration silane can be prevented, and reliability of clocked static RAM and the like can be improved.

(4 In item (1) above, the designated complementary data line is connected to the complementary common data line for reading selectively via the P-channel type switch MOSFET, and the designated complementary data line is connected to the N-channel type complementary common data line. switch MOSFE
By separately providing a complementary common data line for writing that is selectively connected via T, the size of the P-channel type switch MOSFET included in the read-related circuit can be made smaller than the size of the N-channel type switch MOSFET included in the write-related circuit. Since the size can be reduced without being affected by the type of switch MOS FET, it is possible to achieve the effect of further speeding up the read operation of a clocked static type RAM or the like.

(5) In item (4) above, when the clocked static RAM, etc. is in a non-selected state, the complementary data line is precharged to high level and the complementary common data line for writing is precharged to low level. Since the level changes of the complementary data line and the complementary common data line for writing in the write operation mode can be made faster, it is possible to further speed up the write operation of a clocked static type RAM or the like.

(6) In items (1) to (5) above, the level of the ground potential supply point of the memory cell is set to an intermediate level when the clocked static RAM, etc. is in a non-selected state or in write mode. This has the effect of promoting lower power consumption of clocked static RAMs and the like.

(η The above (11) to (6) have the effect of speeding up the operation of clocked static RAM, reducing power consumption, and increasing the flexibility of the bit configuration, that is, the system configuration. is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, inverted main word lines WO to Wm and each sub-word line S
The sub-word line drive circuit provided between W O and W m may be, for example, two inverter circuits connected in series. In this case, the main word line is set to a high level in the selected state. It is necessary to A clocked static type RAM is a memory array M shown in FIG.
The memory cell MC may include a plurality of memory arrays similar to ARY, or the memory cell MC may be a static memory cell with a high resistance load. In FIG. is logic “1” or logic “
The internal control signal ads may be set to a high level after determining that read data has been taken into each output launch. .

Furthermore, the clocked static type R shown in FIG.
AM block configuration and sense amplifier S shown in Figure 2
Various embodiments may be adopted, such as combinations of the specific circuit configuration of A and the control signals shown in FIG.

In the above description, the invention made by the present inventor was mainly applied to an on-chip clocked static RAM, which is the field of application for which the invention was made, but the present invention is not limited to this, for example, It can also be used in various semiconductor memory devices such as those used alone as clocked static RAM and ordinary CMOS static RAM.

(Effects of the Invention) The effects obtained by the typical inventions disclosed in this application are as follows.In other words, the effects obtained by the typical inventions disclosed in this application are as follows. The sub-word lines forming each sub-memory array are connected to the main word line via a correspondingly provided sub-word line drive circuit such as an inverter circuit. By doing so, it is possible to reduce the load on the main word line and increase the drive capability of each sub-word line.This allows clocked static RAM to operate faster and reduce power consumption. In addition, it is possible to increase the flexibility of the focus configuration of clocked static RAM, etc., and prevent disconnection of the main word line due to electromigration, thereby increasing the reliability of clocked static RAM, etc. .

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of a clocked static type RAM to which the present invention is applied. FIG. 2 is a circuit diagram showing an embodiment of a sense amplifier of the clocked static type RAM of FIG. 1. Figure 3 is the first
FIG. 3 is a timing diagram showing an embodiment of the clocked static RAM shown in FIG. MARY...Memory array, SMO~5M31...
Sub memory array, MC...memory cell, CSW...
・Column switch, SSO~5S31...Sub column switch, XAD...X address decoder, YAD・
・・Y address decoder, 5YDO~5YD31...
Sub address decoder, XAB...X address buffer, YAB...Y address buffer, SA...Sense amplifier, WA...Write amplifier, DOB...Data output buffer, DIB...Data input cover sofa, T
O...Timing generation circuit. USAO~USA31...Unit sense amplifier, PC/
...Precharge circuit, LS...level shift circuit,
SC...Sense circuit, OL...Output launch. Q1 to Q18...P channel MO5FET. Q21-Q43...N-channel MOSFET. N1-N3...CMOS inverter circuit, AGl...
・AND gate circuit, OGI~OG2...OR gate circuit.

Claims (1)

[Claims] 1. A plurality of sub-word lines and data lines arranged orthogonally to each other, and memory cells arranged in a lattice at the intersections of these sub-word lines and data lines, in the direction of the extension line of the sub-word lines. a plurality of sub-memory arrays arranged in series; a plurality of main word lines arranged parallel to the sub-word lines and penetrating the plurality of sub-memory arrays;
A semiconductor memory device comprising: a plurality of sub-word line drive circuits respectively provided between the sub-word lines and the corresponding main word lines. 2. The semiconductor memory device further includes a reading common data line to which the designated data line is selectively connected via a P-channel switch MOSFET and precharged to a high level when not selected; The specified data line is an N-channel type switch MOSF
2. The semiconductor memory device according to claim 1, further comprising a write common data line that is selectively connected via an ET and precharged to a low level when not selected. 3. The semiconductor memory device is an on-chip clocked static RAM mounted on a logic integrated circuit, and includes a read common data line, a write common data line, and a column system selector that correspond to the sub-memory array. 3. The semiconductor memory device according to claim 1, wherein the circuit is unitized in accordance with the bit configuration of the clocked static RAM.