JPH0287393A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain high-speed access by dividing plural transistors connected to a word line into plural groups and connecting a subword line to be commonly connected for each group through an inverter to a main word line. CONSTITUTION:For plural transistors composed of transistors connected to a main word line 3, they are divided into plural groups 16-1 and 16-2, and subword lines 7-1 and 7-2 connected commonly for respective groups are connected through inverters 17-1 and 17-2 to the main word line 3. Consequently, a buffer 14 of the main word line 3 is sufficient to have an output capacity for driving only prescribed one group. The inverters 17-1 and 17-2 are sufficient to be small for driving only the total of the memory cells. Thus, the access time can be shortened.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor storage device that can shorten access time, and provides a semi-quadramid storage device that allows high-speed access by simply changing the configuration by adding a few elements. The gate electrodes of the plurality of transistors are commonly connected to a main word line, the source electrodes of the transistors are connected to respective separate bit lines, and the bit lines are commonly connected to the source electrodes of other transistors. In a semiconductor memory device in which information is read and written by selecting a predetermined transistor cell using a word line and a bit line, a plurality of transistors consisting of transistors connected to a word line are divided into a plurality of groups. , the sub-word lines commonly connected for each group are connected to the main word line via an inverter.

[Industrial Application Field] The present invention relates to a semiconductor device that can shorten access time.

Semiconductor memory devices are increasingly required to shorten access time. In particular, in a format in which an n-channel transistor is used as a memory cell, it is difficult to meet the above-mentioned requirements due to the word line bumper, and it has become necessary to develop a new technology.

[Prior art] Current semiconductor memory devices are ROM type and R type using FET.
AM type is the mainstream. An example of one cell of a RAM type storage device is shown in FIG. 4, and a ROM type storage device is shown in FIG. In FIG. 4, l-], , l-2 are n-channel FETs, 1-3 .
1-4 indicates an n-channel FET, and 2-1.2-2 indicates an n-channel FET. 1-1 to 1-4 and 2-12-2 are connected as shown in the figure to form one cell.

Further, 3 indicates a word line, 4-1 a bit line, 4-2 a bit line, 5 a power supply, and 6 a ground. In the semiconductor memory device, the aforementioned cells are arranged in a matrix, and word line 3 and bit lines 4-1 and 4-2 are selected by data obtained by decoding an address instructed by a host computer (not shown). The host computer then performs predetermined read/write processing on the selected cell. FET2-1.2 is called the transmission gate of a memory cell.
=2 and n channels are used because high-speed operation is intended. This is because n-channel FET0 has a larger carrier mobility μ than that of n-channel FET.

In Fig. 5, 3, 4.6 are word lines as in Fig. 4;
Bit line, indicating ground. 2 is an n-channel FET, and 8 indicates whether or not the FET 7 is connected to the bit line 4 by a computer program, and the presence or absence of connection is made to correspond to "0" and "1".

Therefore, in order to read this memory cell, address decoding is performed on the word line and bit line, and when addressing is performed, signals corresponding to "1" and "0" are obtained.
The purpose of using an n-channel FET in the M-type cell is to achieve high speed.

FIG. 6 is a diagram showing a word line decoder as an address decoding circuit. In FIG. 6, reference numerals 11 and 12 are address decoder application terminals to which, for example, a and ao are applied. 13 is a predecoder, 14 is a buffer for each word line, and 15 is a memory cell as a whole. Generally, when there are n address data application terminals, the data is decoded into 2n predecode lines by the predecoder 13. Then, it is further decoded into 2'' word lines by the address decoder. FIG. 6 shows the case where n=2, and the predecoder 13 decodes it into 4 word lines.

A word line filter 14 is provided for each word line, and drives FETs of memory cells connected to the word line in parallel. Therefore, the transistors constituting the buffer require a sufficiently large output capacitance. The output capacitance is also related to the wiring capacitance of the word line. That is, the number of bits is b
, the number of column selections is C, then the number of main transistors to be driven by one word line is bXc.

For example, if b-32 bits and c=8, 256 transistors and a wiring load approximately equal to the chimp size must be operated.

As mentioned above, in the memory cell, the FET connected to the word line uses an n-channel, so in order to select the memory cell, it is necessary to set the word line to "H" level. As shown in Fig. 7, when a CMO5 type is used as the inverter in the final stage of the buffer 14, it is sufficient to control the n-channel FET 14-1 to turn on, and to flow the drive current shown by the arrow 15. FET14-2 is completely off.When the word line is not selected, n-channel FET14-1 is off and n-channel FET14-2 is on, but only leakage current flows and the power consumption is low. Very small amount.

[Problems to be Solved by the Invention] The final stage of the word line buffer shown in FIGS. 6 and 7 needs to have a large output capacitance. At this time, in order to reduce the load on the FET in the final stage of the buffer, there is a way to make the FET connected to the word line smaller, but when it is small, it has the disadvantage that the access time to the memory cell is delayed, so it is difficult to make the size smaller. It's not a good idea. Also FE
Since the gain constant β of T is proportional to the mobility, the p-channel FET in the circuit using the CMO3 type is replaced by the n-channel FE.
It had the disadvantage that its driving capacity was smaller than that of the T.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and provide a semiconductor memory device that can be accessed at high speed by simply changing the structure by adding a few elements.

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 3 is the main word line, 7-1, 7-2... are sub-word lines, 14 is the final stage of the buffer, 16-1, 16-2 is the grouped memory cells (transistors), 17 -1
．． 17-2~ indicates impark.

A plurality of transistors 2-1. - have their gate electrodes commonly connected to the main word line 3, and the transistors 2-1. ... are connected to respective bit lines 4, and the bit lines 4 are commonly connected to the source electrodes of other transistors, and a predetermined transistor cell is selected by the word line 3 and the bit line 4. In a semiconductor memory device for reading and writing information, the present invention has the following configuration. That is, a plurality of transistors connected to the main word line 3 are divided into a plurality of groups 15.
-1. Sub-words vA7-1, 7-2=-, which are divided into 15-2- and commonly connected for each group, are connected to the inverter 1.
It is configured by connecting to the main word vA3 via 6-1.16-2-.

[Since a plurality of transistors constituting an active co-memory cell are collectively divided into a plurality of groups 16-1, 16-2-, the buffer 14 of the main word line 3 is divided into a plurality of groups 16-1, 16-2-.
It is sufficient to have the output capacity to drive only one.

The inverter 17-1 and the like can be small enough to drive only the total number of memory cells.

[Embodiment] FIG. 2 is a detailed diagram of a buffer inverter as an embodiment of the present invention. In Figure 2, 18-
1 is a p-channel FET and 18-2 is an n-channel FET, which constitutes an inverter 17-1.

The word line buffer's highest stage (4) is also configured with a similar in-hook structure. When the sub-word line 7-1 is set to "H" level to select a memory cell constituted by an n-channel FET, as explained with reference to FIG.
8-1 is turned on (driving J current 12), at that time, the n-channel FET 14-
2 needs to be turned on (drive current 11). Therefore, the decoded data for the main word line 3 is inverted from the conventional decoded result for the word line 3. However, the operation of driving the main word line 3 is sufficiently accelerated due to the operation of the n-channel FET.

Figure 3 shows a mask bus grammable RO using the circuit shown in Figure 2.
FIG. 4 is a diagram showing a mask pattern for M. The left side of the figure is Inhak 17-1. The right side is the memory cell part 16-
1 is shown. Furthermore, since it has a two-layer structure, the portions that are wired to the second layer are shown by dotted lines. This configuration allows easy integration into LSI.

[Effects of the Invention] Thus, according to the present invention, the memory cells connected to the main word line are grouped by small inverters, so for example, when m memory cells are grouped together, the load on the main word line is 2. /m, which made it possible to drive the inverter in the winter stage with n-channels and to sufficiently increase the speed of operation. For example, in a CMOS gate array mask ROM, when the number of bits is 32 and the number of column selections is 8, the access time can be reduced by 2 ns.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, and Fig. 3 is a diagram showing the configuration of the embodiment of the present invention.
FIG. 4 is a diagram showing a cell of a conventional RAM type storage device, and FIG.
FIG. 6 is a diagram showing a cell of a conventional ROM type memory 1a device, FIG. 6 is a diagram showing an address decoding circuit, and FIG. 7 is a diagram for explaining a conventional word line selection operation. 1.2 Transistor (FET) Main word line bit line - sub word line 6 memory cell 7 inverter

Claims (1)

[Claims] The gate electrodes of a plurality of transistors (2-1) are commonly connected to the main word line (3), and the transistors (2-1)...
The source electrodes of 1) are connected to separate bit lines (4), and the bit lines (4) are commonly connected to the source electrodes of other transistors, and the word line (3) and bit line (4) are connected to each other. In a semiconductor memory device in which a predetermined transistor cell is selected to read and write information, a plurality of memory cells each composed of a transistor connected to the main word line (3) are divided into a plurality of groups (16-1) ( Sub-word lines (7-1) (7-2), which are divided into 16-2) and commonly connected for each group.
. . are connected to a main word line (3) via inverters (17-1), (17-2), .