JPH0249041B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a DC bias circuit for a semiconductor element in a semiconductor element matching circuit using a microstrip line used in an ultra-high frequency band.

In a matching circuit for a semiconductor element in an ultra-high frequency band, it is desirable to bias the semiconductor element by connecting a DC bias circuit that has as little influence on the high frequency circuit as possible.

To this end, methods have been used to date, such as configuring the DC bias circuit as a special low-pass filter circuit. However, despite various efforts, there has been a fundamental difficulty in providing a current supply line with a large current capacity and high characteristic impedance. For example, similar to constructing a microstrip line, it is easy to construct a DC bias line on an insulating substrate, but the characteristic impedance of a thin conductor line created by this method is It is lowered due to its dielectric constant, and it is physically difficult to increase it above about 100Ω. on the other hand,
When the thin conductor line is separated from the insulator substrate,
Although it is easy to increase the characteristic impedance to about several kilohms, it is difficult to dissipate the Joule heat generated from the thin conductor wire, making it difficult to obtain a large current capacity.

The present inventor conducted research and experiments to solve the above problem, and from experimental measurement data as shown in Figure 1 of the fusing current value of a thin conductor line due to Joule heat generated in the thin conductor line, the heat dissipation phenomenon of Joule heat was found. revealed.

The present invention has been made by focusing on the above-mentioned heat radiation phenomenon in order to eliminate the above-mentioned drawbacks inherent in the conventional technology.Therefore, an object of the present invention is to apply the above-mentioned heat radiation phenomenon to a method of configuring a thin conductor line. In particular, the object of the present invention is to provide a new DC bias circuit that is configured with a bias line that has a large current capacity and high characteristic impedance, setting effective heat dissipation conditions without impairing the high characteristic impedance condition. .

The DC bias circuit of the present invention is a DC bias circuit of a semiconductor matching circuit composed of microstrip lines, and is a thin conductor line for realizing a high characteristic impedance (or high reactance) line of 100Ω or more. On the other hand, in order to improve the heat conduction characteristics while maintaining the high characteristic impedance of this thin conductor line, the microstrip line is formed at at least one intermediate point other than both ends of this thin conductor line. The present invention is characterized in that a relay pattern is provided on an insulating substrate, and the thin conductor lines are relayed at intervals of 6 mm or less.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows data obtained from the relationship between the fusing current value of the gold wire and the bonding span length of the gold wire when both ends of the gold wire of φ20 μm are bonded to the pins of the T0-8 package. This data shows that if the gold wire is long enough, the gold wire will easily melt at low currents because no heat conduction effect can be expected from both ends. On the other hand, when the gold wire becomes shorter, heat radiation due to heat conduction to both ends becomes more pronounced, so that it does not easily melt even with a large current. From this data, for example, if a DC bias line with a length of 6 mm is made of a gold wire with a diameter of 20 μm, the allowable current of this gold wire is
It is 0.5A. However, if one pin is bonded in the center and the line is constructed as a relay point of 3 mm each, the allowable current increases to 0.68A. Furthermore, if two relay points are provided in the center and the lines are cascaded, each 2 mm in length, the allowable current will increase to 0.95 A.

FIG. 2 is a schematic diagram showing an embodiment of a DC bias circuit according to the present invention based on this principle.
In the figure, reference number 1 is a semiconductor element, 2 is a relatively low impedance line connecting the semiconductor element 1 and a microstrip line 3, 3 is a microstrip line constituting a high frequency conductor circuit, and 4 is a microstrip line. An insulator substrate for configuring a strip circuit,
5 and 6 are relay patterns for thin conductor lines 7 provided on the insulating substrate 4 to constitute the bias line of the present invention, and 7 has relay points necessary for the present invention on the relay patterns 5 and 6. 8 is a capacitor forming a low-pass filter together with the thin conductor line 7, and 9 is a relatively low impedance line connected to an external DC bias circuit. Reference numeral 10 indicates a grounded metal plate. On this metal plate 10, a semiconductor element 1, an insulator substrate 4, and a capacitor 8 are formed. On the insulator substrate 4, a microstrip line 3 and a relay pattern 5 are formed. ,6
is formed.

Here, the parameters of the present invention connected to an actual high-frequency circuit, that is, the thickness of the thin conductor line and the maximum length of the thin conductor line connected between each relay pattern may be determined as follows. . First, the specification of the high frequency circuit to which the present invention is to be connected determines the characteristic impedance that the thin conductor line should have, and thereby the diameter of the thin conductor line. Also, the maximum value of the current flowing through the thin conductor line is determined from the specifications of the high frequency circuit, but by referring to the experimental results shown in Figure 1, the maximum value of the length of the thin conductor line between the relay points can be determined. A value can be determined. By configuring the thin conductor line 7, the relay patterns 5, 6
In this case, it becomes possible to dissipate heat by thermal conduction as described in the previous experiment, and as a result, the thin conductor line 7 has a large current capacity. In addition, the dimensions of this relay pattern (the length of one side if the pattern outline is approximately square, the diameter if it is circular) are several times the thickness (or diameter) of the thin conductor line, and the mechanical The strength is sufficient, and the dimensions of this relay pattern can be made sufficiently smaller than the wavelength corresponding to the operating frequency of the high frequency circuit to be connected to the present invention. Therefore, the high-performance DC bias circuit having a large current capacity as intended by the present invention can be realized without substantially impairing the high characteristic impedance characteristic of the thin conductor line 7.

Furthermore, since the thin conductor line 7 has a relay point at the intermediate point, improvement in mechanical strength can be expected. This is an effect associated with the present invention.

Although one preferred embodiment of the present invention has been described above, it is merely an illustrative example, and the present invention is not limited only by the embodiment described here, and it is possible to deviate from its scope. Various modifications are possible. For example, in this embodiment, there are two relay points, but it goes without saying that the number of relay points may be one or three or more as necessary.

[Brief explanation of drawings]

Figure 1 shows the measured values of the gold wire length and fusing current when a 20 μm gold wire is bonded between the pins of the TO-8 package, with the gold wire length on the horizontal axis and the fusing current on the vertical axis. Each is shown on a logarithmic scale. FIG. 2 is a schematic configuration diagram showing an embodiment of the present invention. 1... Semiconductor element, 2... Line connecting the semiconductor element and microstrip line, 3... Microstrip line, 4... Insulator substrate, 5, 6...
Relay pattern for thin conductor line 7, 7... thin conductor line having a relay point according to the present invention, 8... capacitor, 9... tangential line to external DC circuit, 10...
metal plate.

Claims (1)

[Claims] 1 In the DC bias circuit of a semiconductor matching circuit composed of microstrip lines, the height of this thin conductor line is In order to improve heat conduction characteristics while maintaining characteristic impedance, at least one relay pattern is provided on the insulator substrate on which the microstrip line is formed, and the thin conductor line is connected to this relay pattern. relayed via
A DC bias circuit characterized in that the dimensions of this relay pattern are approximately several times the thickness of the thin conductor line.