JPH0119269B2 - - Google Patents
Info
- Publication number
- JPH0119269B2 JPH0119269B2 JP57080878A JP8087882A JPH0119269B2 JP H0119269 B2 JPH0119269 B2 JP H0119269B2 JP 57080878 A JP57080878 A JP 57080878A JP 8087882 A JP8087882 A JP 8087882A JP H0119269 B2 JPH0119269 B2 JP H0119269B2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- plate
- support
- subassembly
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000004020 conductor Substances 0.000 claims description 12
- 230000003014 reinforcing effect Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000012777 electrically insulating material Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 4
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- YCKOAAUKSGOOJH-UHFFFAOYSA-N copper silver Chemical compound [Cu].[Ag].[Ag] YCKOAAUKSGOOJH-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は少なくとも1個の半導体回路素子と保
護エンベロープを有する半導体装置の製造方法で
あり、電気的に絶縁特性であり伝熱特性の板に金
属化した表面を設け、その1つの面上に半導体回
路素子を搭載し、この板自体は電気的並びに熱的
に伝導性を有する支持体上に配置し、この板を電
気的に絶縁性の材料のフレームで包囲し、このフ
レームに接続導線を設けこれを支持体上に配置
し、その上にカバーを設け、その全体のアツセン
ブリ(組立て)としてこの板と支持体とさらに保
護エンベロープを構成するフレームおよびカバー
より成る半導体装置の組立て方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for manufacturing a semiconductor device having at least one semiconductor circuit element and a protective envelope, comprising: providing a plate with electrically insulating and heat conducting properties with a metallized surface; a semiconductor circuit element is mounted on one side thereof, the board itself is placed on an electrically and thermally conductive support, and the board is surrounded by a frame of electrically insulating material; A semiconductor device comprising a connecting conductor on this frame, placed on a support, a cover on top of it, and the entire assembly consisting of this plate, the support, and the frame and cover that constitute a protective envelope. This relates to an assembly method.
本発明方法はとくに極めて高い周波数範囲、例
えばGHz範囲の領域の周波数で動作すべき半導体
装置に好適なものである。ただし本発明の対象は
これに限定されるものではない。 The method according to the invention is particularly suitable for semiconductor devices which are to be operated in a very high frequency range, for example in the GHz range. However, the object of the present invention is not limited to this.
高い周波数領域で動作する半導体装置の分野に
おいては、各種要素のうち半導体回路素子を金属
化した表面に接続する接続線およびエンベロープ
に設ける接続導線または導体に接続する接続線の
長さにとくに注意を払うを要することは既知であ
る。既知のようにこれらの接続線の長さによつて
その線のインダクタンス値が定まる。一般に云つ
てトランジスタおよびMOS(金属酸化物半導体)
コンデンサを含む高周波半導体装置においては多
数の接続点が存する。これらの接続点において接
続線がこれに終端し、またこれら接続点より接続
線が発出する。 In the field of semiconductor devices that operate in high frequency ranges, special attention should be paid to the length of the connection wires that connect the semiconductor circuit elements to the metallized surface of the various elements, and the connection wires provided in the envelope or the connection wires that connect to the conductors. It is known that it costs money. As is known, the length of these connecting lines determines the inductance value of that line. Generally speaking, transistors and MOS (metal oxide semiconductors)
There are many connection points in a high frequency semiconductor device including a capacitor. Connection lines terminate at these connection points, and connection lines emanate from these connection points.
本発明の対象とする製造方法において、従来は
一般に酸化ベリリウムで作られる板と、一般にア
ルミナで作られるフレームと、一般に銅で作る支
持体を以て構成されるサブアツセンブリを1つの
第1段階で製造していた。この場合周囲のフレー
ムに比較して比較的に小さな寸法の板(プレー
ト)は、支持体上に直接はんだ付した。このフレ
ームは金属リングを用いて支持体に固定した。こ
の金属リングはフレームと支持体間に位置し、上
記2つの部分にはんだ付けにより固着した。この
リングを使用することによつてフレームと支持体
間の接触表面が減少し、これによつて機械的スト
レスが減少する。この方法は場合によつてはフレ
ームの寸法がかなりの大きさとなるため、はんだ
付けの瞬間においてフレームの破損が生ずる。1
個または1個以上の半導体素子はかく形成したサ
ブアツセンブリの板上にはんだ付材料を配置して
取付け、所要の接続線を固着する。最後にカバー
を配置しこれをはんだ付けにより固着する。 In the manufacturing method which is the object of the present invention, a subassembly, conventionally consisting of a plate generally made of beryllium oxide, a frame generally made of alumina, and a support generally made of copper, is produced in one first step. Was. In this case a plate of relatively small dimensions compared to the surrounding frame was soldered directly onto the support. This frame was fixed to the support using metal rings. This metal ring was located between the frame and the support and was fixed to the two parts by soldering. The use of this ring reduces the contact surface between the frame and the support, thereby reducing mechanical stress. In some cases, this method increases the dimensions of the frame so much that the frame breaks at the moment of soldering. 1
The one or more semiconductor devices are mounted on the plate of the thus formed subassembly by disposing soldering material and securing the required connection lines. Finally, place the cover and secure it by soldering.
このような従来の組立て方法にはいくつかの欠
点があつた。 These conventional assembly methods had several drawbacks.
第1に、経験によると板をこれを取囲むフレー
ムに対し正しく中心を定めることが不可能であつ
たことである。板とフレームと支持体より成るサ
ブアツセンブリの組立て中において、この板およ
びフレームは相互間で位置を移動し、最終的に完
成する各サブアツセンブリ毎にかなり大きく違つ
た位置を占めることとなる。しかしながら形成す
べき接続線の規則正しさはこの板とフレームとの
相対的位置により定まる。 First, experience has shown that it has been impossible to center the board correctly with respect to the surrounding frame. During the assembly of the subassemblies consisting of plates, frames, and supports, the plates and frames shift relative to each other and end up occupying considerably different positions in each completed subassembly. . However, the regularity of the connecting lines to be formed is determined by the relative position of this plate and frame.
第2に、板およびフレームの支持体に対する連
結部が1個以上の半導体素子をはんだ付けする次
の工程において到達する温度に耐えるものでなけ
ればならないことはよく理解されるところであろ
う。 Second, it will be appreciated that the connections of the plate and frame to the support must be able to withstand the temperatures reached in the subsequent soldering process of one or more semiconductor components.
この温度は約380℃程度である(これは金の層
を被着した板とクリスタル(結晶)をはんだ付け
する場合であり、クリスタル表面には金−珪素の
共融層が形成される)。従つてこの場合板および
フレームははんだ付介在物によつて固定する。そ
の溶融温度は380℃よりもかなり高い(一般に790
℃で溶融する銅−銀合金で作る)。容易に理解で
きるようにこのような温度ではフレームおよび板
に破損および割目が生じること並びにこれら2つ
の部分が互いに正しくない位置に配置されること
の両方より不良品が生ずることを避けるのはむず
かしかつた。 This temperature is approximately 380° C. (this is the case when a plate coated with a gold layer is soldered to a crystal, and a gold-silicon eutectic layer is formed on the surface of the crystal). In this case, the plate and frame are therefore fixed by means of soldered inserts. Its melting temperature is significantly higher than 380℃ (generally 790
made of a copper-silver alloy that melts at ℃). As can be easily seen, at such temperatures it is difficult to avoid rejects, both due to breakage and splitting of the frame and plate and due to incorrect positioning of these two parts relative to each other. It was.
最後に、板の表面上の正しい位置に回路素子を
固定する点で困難があつた。これはとくに回路素
子をフレーム壁に近く配置するを要するときに然
りであり、これはこの壁部は板より高く突出して
いたからである。 Finally, difficulties were encountered in securing the circuit elements in the correct location on the surface of the board. This is particularly the case when it is necessary to locate the circuit elements close to the frame wall, since this wall protrudes higher than the board.
本発明による方法は上述の従来方法の各欠点を
克服しようとするを目的とする。 The method according to the invention aims to overcome each of the drawbacks of the conventional methods mentioned above.
本方法は、第1工程として回路素子、板および
フレームを具えてなるサブアツセンブリを形成
し、この形成に際し、半導体回路素子を板の金属
化した表面の1つ上に固定し、これを接続線によ
り少なくとも前記接続導線に接続し、次いで第2
工程としてこのサブアツセンブリを一方において
支持体4に連結し、他方においてカバーに連結す
ることを特徴とする。 The method includes, as a first step, forming a subassembly comprising a circuit element, a plate, and a frame, securing a semiconductor circuit element on one of the metallized surfaces of the plate, and connecting the subassembly. by a wire to at least said connecting conductor, and then a second
The process is characterized in that this subassembly is connected on the one hand to the support 4 and on the other hand to the cover.
本発明方法を使用することにより、まず第1の
利点としては板とフレームとを支持体に対し組立
てる場合の温度を減少させることが可能である点
である。これは一個以上の回路素子を組立工程内
の板に予め固定するからである。本発明の方法に
よるときは従来既知の方法とは異なり溶融温度が
380℃よりも低いはんだ付材料を使用することが
できる。とくにこれに対し金(80%)と錫(20
%)の共融体で作つた溶融点が280℃の材料を使
用すると好都合である。この場合従来既知の方法
における790℃に比較して組立てにおける温度は
かなり低くなるので、セラミツク素子破損、割目
の形成、あるいは亀裂の生成による不良品が生ず
る危険性は遥かに小さい。またこの組立方法は低
い温度であるため遥かに容易に、また遥かに迅速
に行なうことができる。またフレームは支持体上
に直接支持されるのでこれら素子の間に熱膨張係
数の相違を打消すための金属リングを介在させる
必要がなくなる。 By using the method of the invention, a first advantage is that it is possible to reduce the temperature during the assembly of the plate and the frame to the support. This is because one or more circuit elements are prefixed to the plate during the assembly process. When using the method of the present invention, unlike conventionally known methods, the melting temperature is
Soldering materials lower than 380℃ can be used. In particular, gold (80%) and tin (20%)
It is advantageous to use a material with a melting point of 280° C. made from a eutectic of In this case, the assembly temperature is considerably lower than the 790 DEG C. in the previously known process, so that the risk of defective products due to damage to the ceramic elements, the formation of splits or the formation of cracks is much smaller. This method of assembly is also much easier and much faster due to the lower temperatures. Furthermore, since the frame is directly supported on the support, there is no need to interpose a metal ring between these elements to cancel out differences in thermal expansion coefficients.
本発明方法の第2の重要な利点は、板(プレー
ト)をフレームに対し極めて正しく位置決めし、
かつこれを維持することが可能となることであ
る。 A second important advantage of the method according to the invention is that the plate is positioned very precisely relative to the frame;
And it will be possible to maintain this.
このような正確な位置決めは接続線の配設工程
中に得られる。板よりフレームに延びる接続線は
板をフレームに対し安定に位置決めする極めて密
接な配線支持網を構成する。これによつて幾つか
のサブアツセンブリ間の接続線の長さは極めて規
則正しいものとなり、これにより電気特性の再現
性が改良される。 Such precise positioning is obtained during the connecting line installation process. The connecting wires extending from the plate to the frame constitute a very tight wiring support network that stably positions the plate relative to the frame. This allows the lengths of the connecting lines between the several subassemblies to be very regular, which improves the reproducibility of the electrical properties.
本発明方法による他の利点は、半導体回路素子
を板上にはんだ付けする工程が容易となることで
ある。これらの回路素子がこれら板の縁部近くに
位置しても同じことである。このはんだ付工程は
実際上当然のことながら板とフレーム間の接続を
設けるのに先立つて行われるものであり、このは
んだ付工程中においてはまだ配置されていないフ
レームが工具の移動を妨げることはない。さらに
不良品が出るとしても回路素子を板に対しはんだ
付けする工程で出るものであり、従来既知の技術
による組立方法の如く板−フレーム−支持体の3
者の組立工程で出るものではない。 Another advantage of the method of the invention is that it simplifies the process of soldering semiconductor circuit elements onto a board. The same is true if these circuit elements are located near the edges of the plates. This soldering process is actually performed prior to making the connection between the board and the frame, and during this soldering process, the frame that has not yet been placed does not interfere with the movement of the tool. do not have. Furthermore, even if defective products are produced, they are generated during the process of soldering the circuit elements to the board, and as in the assembly method using conventionally known technology, the three parts of the board - frame - support body are soldered.
It is not something that comes out during the assembly process.
本発明方法においては半導体装置の電気的動作
に必要な接続線のみで板とフレーム間の機械的位
置保持に充分である。従来の高周波装置において
板の重量は約0.1g程度であり、これに対し接続
線は極めて多数であることが多い。これらの接続
線は25ないし50μmの直径であり、サブアツセ
ンブリ部品の正しい位置保持に充分である。 In the method of the invention, only the connecting wires required for the electrical operation of the semiconductor device are sufficient to maintain the mechanical position between the plate and the frame. In conventional high-frequency devices, the weight of the plate is approximately 0.1 g, whereas the number of connection wires is often extremely large. These connecting lines have a diameter of 25 to 50 μm, which is sufficient to hold the subassembly parts in the correct position.
本発明方法の応用において、板の金属化表面と
フレーム間の機械的強度は、その1部を前記接続
線により保持し、またこれらの間を接続する補強
線により1部を受持たせることができる。これら
の補強線は純粋に機械的な作用のみを行うもので
ある。 In the application of the method of the invention, the mechanical strength between the metallized surface of the plate and the frame can be maintained partly by the connecting wires and partly by the reinforcing wires connecting them. can. These reinforcing wires have a purely mechanical function.
以下図面により本発明を説明する。 The present invention will be explained below with reference to the drawings.
添付の各図面においてその構成自体がよく知ら
れている各素子の細部については、図示を簡単に
するために省略してある。例えばトランジスタ或
いはMOSコンデンサの如き半導体回路素子の構
造をもつた半導体素子は単に略図で示してある。
さらに各構成素子でその寸法が極めて小さいもの
は理解を容易にするため寸法を拡大して示してあ
る。 In the accompanying drawings, details of elements whose construction is well known have been omitted for clarity. Semiconductor elements in the form of semiconductor circuit elements, such as transistors or MOS capacitors, are shown only schematically.
Further, each component whose size is extremely small is shown enlarged to facilitate understanding.
図面に示す組立方法においては、トランジスタ
1とMOS型コンデンサ2のような半導体回路素
子を例としてその組立てを示してある。これらの
回路素子は酸化ベリリウムの板3の金属化した表
面即ち上側表面3A上に配置する。トランジスタ
1はそのクリスタルの背面を表面30にはんだ付
けする。コンデンサ2は他の表面31上にはんだ
付けする。この表面31と他の表面32を板3の
側において延長し、同じく金属化してある板3の
底面3Bに接続する。この板3はその底面3Bに
よつて銅の支持体4に固定する。 In the assembly method shown in the drawings, the assembly is shown using semiconductor circuit elements such as a transistor 1 and a MOS type capacitor 2 as an example. These circuit elements are arranged on the metallized or upper surface 3A of the beryllium oxide plate 3. Transistor 1 is soldered on the back side of its crystal to surface 30. Capacitor 2 is soldered onto the other surface 31. This surface 31 and another surface 32 extend on the side of the plate 3 and are connected to the bottom surface 3B of the plate 3, which is also metallized. This plate 3 is fixed to a copper support 4 by its bottom surface 3B.
この板3をアルミナのフレーム5で覆い、これ
ら2つの素子の間の間隙(クリアランス)は約
0.5mm程度である。フレーム5は狭い幅の上側リ
ング5Bと下側リング5Aを有し、それらの間に
金属化した部分を設ける。これら両リングはフレ
ームの製造の際に互いに接続し、一体の部分を形
成させる。この金属化はリング5Aの全接続表面
上に設ける。この金属化部分はリング5Aの内側
表面にも延長し、接触表面を形成し、これは例え
ば表面50および51で形成する部分とする。こ
れらは接続領域6内のリング5Aの外側表面にも
同様に設け、これはリング5Bに配置される。接
続導線7および8は接続領域6にはんだ付けされ
る。フレーム5を支持体4に固定する。 This plate 3 is covered with an alumina frame 5, and the gap (clearance) between these two elements is approximately
It is about 0.5mm. The frame 5 has a narrow upper ring 5B and a lower ring 5A with a metallized section between them. Both rings are connected to each other during manufacture of the frame so that they form an integral part. This metallization is provided on all connecting surfaces of ring 5A. This metallization also extends to the inner surface of ring 5A and forms a contact surface, such as that formed by surfaces 50 and 51, for example. These are likewise provided on the outer surface of ring 5A in connection area 6, which is arranged on ring 5B. The connecting conductors 7 and 8 are soldered to the connecting area 6. The frame 5 is fixed to the support 4.
フレーム5にはカバー9を設け、その上側のレ
ベルは板3の面および1および2の如くの回路素
子に接続導線を設けた部分のレベルより上側に突
出する。 The frame 5 is provided with a cover 9 whose upper level projects above the surface of the plate 3 and the level of the portions where the circuit elements such as 1 and 2 are provided with connecting conductors.
接続線20は所望の電気接続を形成する。図示
の例においてはトランジスタ1のエミツタ領域1
1を一方において表面32に接続し、またこの表
面を通じ支持体4に接続し、さらに他方において
はコンデンサ2の電極に接続する。またこの表面
を通じ支持体4に接続し、さらに他方においては
コンデンサ2の電極に接続する。トランジスタ1
のベース領域12はコンデンサ2の他方の電極に
接続し、この電極を通じ他の接続を通じて金属化
表面51をベース出力導線8に接続する。トラン
ジスタ1が配置してある金属化表面30とコレク
タ出力導線7に接続してある表面50間のコレク
タ接続を接続導線で同じく完結する。 Connecting wire 20 forms the desired electrical connection. In the illustrated example, emitter region 1 of transistor 1
1 is connected on the one hand to the surface 32 and through this surface to the support 4 and on the other hand to the electrodes of the capacitor 2. It is also connected through this surface to the support 4 and, on the other hand, to the electrodes of the capacitor 2. transistor 1
The base region 12 of is connected to the other electrode of the capacitor 2, through which the metallized surface 51 is connected to the base output conductor 8 through another connection. The collector connection between the metallized surface 30 on which the transistor 1 is arranged and the surface 50 connected to the collector output conductor 7 is likewise completed with a connecting conductor.
本発明による方法をよりよく理解するため板3
またはコンデンサ2をフレーム5に接続する接続
線20Aを一方のものとし、また他方の20で示
した接続線は板3より決して外側には突出しない
ものとして符号により区別できるようにした。 Board 3 for a better understanding of the method according to the invention
Alternatively, the connection wire 20A connecting the capacitor 2 to the frame 5 is one, and the other connection wire 20 does not protrude outward from the plate 3, so that they can be distinguished by reference numerals.
特に第3図を参照し本発明により最も有利な条
件で上述のアツセンブリを製造する方法を説明す
る。上述したように本発明による方法は第1工程
としてサブアツセンブリ60を製造するが、この
工程においては1,2の如き回路素子、板3、フ
レーム5を組立てる。これにおいて半導体回路素
子1,2の如きものを板3の金属化した表面3
0,31上に取付け、接続線20Aによつて少な
くとも接続導体7,8に接続し、また第2工程と
してこのサブアツセンブリ60を一方において支
持体4に連結し、他方においてカバー9に連結す
る。 With particular reference to FIG. 3, the method of manufacturing the above-described assembly under the most advantageous conditions according to the invention will now be described. As described above, the method according to the present invention manufactures the subassembly 60 as a first step, and in this step, circuit elements such as 1 and 2, the plate 3, and the frame 5 are assembled. In this, semiconductor circuit elements 1, 2, etc. are placed on the metallized surface 3 of the plate 3.
0, 31 and connected to at least the connecting conductors 7, 8 by connecting wires 20A, and in a second step this subassembly 60 is connected on the one hand to the support 4 and on the other hand to the cover 9. .
このサブアツセンブリが形成されるとまず第1
に1および2の如き半導体回路素子を板3の金属
化表面30および31にはんだ付けする。この場
合他の全ての金属化と同様にこの金属化した表面
は金の層を有している。1および2で示し珪素か
ら成つている素子は、はんだ付けすべき面には金
の層を設け、これにより金−珪素合金を形成する
ようにする。はんだ付工程は約380℃の温度にお
いて行う。これに続いて板3とフレーム5を平ら
な作業テーブル上におく。フレーム5は例えば固
定位置に保持し、また板3はセクシヨン系(小駆
動系)により平らな作業テーブル上に保持し、こ
のセクシヨンはフレームに加えられる限度内の精
度を保持し乍ら後にこれを横に移動させる。これ
により2つの部分即ち3および5で表わされる部
分はその軸位置を定められる。 When this subassembly is formed, the first
Then semiconductor circuit elements such as 1 and 2 are soldered to the metallized surfaces 30 and 31 of plate 3. In this case, like all other metallizations, this metallized surface has a layer of gold. The silicon elements designated 1 and 2 are provided with a gold layer on the side to be soldered, so as to form a gold-silicon alloy. The soldering process is performed at a temperature of approximately 380°C. Following this, the plate 3 and frame 5 are placed on a flat work table. The frame 5 is held, for example, in a fixed position, and the plate 3 is held on a flat working table by means of a section system (small drive system), which section maintains the accuracy within the limits applied to the frame and later on it. move it to the side. This allows the two parts, designated 3 and 5, to define their axial positions.
これに続き例えば熱圧縮により金の接続線20
を接続して設ける。多くの場合接続線20Aの構
造は前述の作業位置より最終の組立工程に移動す
る間このサブアツセンブリ60を保持するに充分
な強度を有している。この組立工程は金80%と錫
20%の合金により行う。この合金のリング40を
フレーム5とカバー9との間に配置し、これらは
充分な金属化を行つておく。この合金の板41を
板3と金属化フレーム5を一方とし、他方には支
持体4のはんだ付領域の金被膜を設けた部分との
間に配置する。このアツセンブリは正しい位置に
おいて約280℃の温度とすることにより行う。こ
の温度においては板3に割目が生ずる危険性およ
びこの板およびフレーム5が損損する危険性は、
この全体のエンベロープを従来既知の技術で行わ
れていたように遥かに高い温度で行う場合に比べ
遥かに少なくなる。 This is followed by a gold connecting wire 20, for example by heat compression.
Connect and provide. In many cases, the structure of the connecting line 20A is strong enough to hold the subassembly 60 during movement from the aforementioned working position to the final assembly process. This assembly process consists of 80% gold and tin.
Performed by 20% alloy. A ring 40 of this alloy is placed between the frame 5 and the cover 9, which have sufficient metallization. A plate 41 of this alloy is placed between the plate 3 and the metallized frame 5 on the one hand and the gold-coated part of the soldering area of the support 4 on the other hand. This assembly is carried out at a temperature of approximately 280° C. in the correct position. At this temperature, the risk of cracks forming in the plate 3 and the risk of damage to this plate and the frame 5 are:
This total envelope is much less than if done at much higher temperatures, as was done in previously known techniques.
上述の本発明方法においてはサブアツセンブリ
60の機械的連結特性は接続線20Aのみによつ
て得られるものでなく、補強線を設けることによ
つても行うことができる。このような場合の応用
例を第2図に示す補強線21は、板3の金属化し
た表面をフレーム5の他方のフレームの表面に対
し機械的に連結する。即ち例えば第2図に見られ
るように、フレームの表面52および53を線2
1により接続し、これによつて表面52は板3の
絶縁表面33および上述の表面31に接続され、
また表面53は絶縁表面34と表面31に連結さ
れる。この場合線21は電気的な機能は行わず、
機械的な作用を行うのみである。 In the method of the present invention described above, the mechanical connection characteristics of the subassembly 60 can be achieved not only by the connecting wire 20A, but also by providing a reinforcing wire. A reinforcing wire 21, an example of application in such a case is shown in FIG. 2, mechanically connects the metallized surface of the plate 3 to the other frame surface of the frame 5. That is, for example, as can be seen in FIG.
1, whereby the surface 52 is connected to the insulating surface 33 of the plate 3 and to the above-mentioned surface 31;
Surface 53 is also coupled to insulating surface 34 and surface 31. In this case, line 21 performs no electrical function;
It only performs mechanical action.
第1図は超高周波用半導体装置の第2図の−
線に切つて見た断面図、第2図は第1図示装置
の平面図で、エンベロープのカバーを除いた状態
を示す、第3図は各回路素子と板(プレート)お
よびフレームを含むサブアツセンブリの製造状態
を示すため半導体装置の各部分の分解図を示すも
のであり、この製造工程は本発明の製造最終工程
に至る前の状況を示す図である。
1……トランジスタ(回路素子)、2……コン
デンサ(回路素子)、3……酸化ベリリウム板、
5……フレーム、7,8……回路の接続導線、2
0A,20……接続線、4……支持体、9……カ
バー。
Figure 1 shows the ultra-high frequency semiconductor device shown in Figure 2.
Fig. 2 is a plan view of the device shown in Fig. 1, with the envelope cover removed; Fig. 3 is a sub-assembly including each circuit element, plate, and frame. In order to show the manufacturing state of the assembly, an exploded view of each part of the semiconductor device is shown, and this manufacturing process is a diagram showing the situation before reaching the final manufacturing process of the present invention. 1... Transistor (circuit element), 2... Capacitor (circuit element), 3... Beryllium oxide plate,
5...Frame, 7, 8...Circuit connection conductor, 2
0A, 20...Connection line, 4...Support, 9...Cover.
Claims (1)
ベロープを有する半導体装置であり、電気的に絶
縁特性でありまた伝熱特性を有する板に金属化し
た表面を設け、その板の1つの面上に該半導体回
路素子を搭載し、この板自体は電気的並びに熱的
に伝導性を有する支持体上に配置し、この板を電
気的に絶縁性の材料のフレームで包囲し、このフ
レームに回路の接続導線を設け、このフレームを
支持体上に配置し、その上にカバーを設けてな
り、すなわちその全体のアツセンブリはこの板と
支持体とさらに保護エンベロープを構成するフレ
ームおよびカバーを有して成る半導体装置の組立
方法において、 第1工程として回路素子1,2、板3およびフ
レーム5を具えてなるサブアツセンブリ60を形
成するに際し、 半導体回路素子1,2を板3の金属化した表面
30,31の1つの上に固定し、これを接続線2
0Aにより少なくとも前記接続導線7,8に接続
し、 次いで第2工程としてこのサブアツセンブリ6
0を一方において支持体4に連結し、他方におい
てカバー9に連結する ことを特徴とする半導体装置の組立方法。 2 サブアツセンブリ60を形成するため板3と
フレーム5の間に補強線21を設け、これにより
板の金属化表面31,33,34,52,53と
フレームとを互いに連結することを特徴とする特
許請求の範囲第1項記載の方法。[Scope of Claims] 1. A semiconductor device having at least one semiconductor circuit element and a protective envelope, wherein a plate having electrically insulating and heat conducting properties is provided with a metallized surface, and one of the plates is provided with a metallized surface. The semiconductor circuit element is mounted on one side, the board itself is placed on an electrically and thermally conductive support, and the board is surrounded by a frame of electrically insulating material. The frame is provided with the connecting conductors of the circuit, this frame is placed on a support and a cover is provided thereon, i.e. the whole assembly consists of this plate, the support and also the frame and cover which constitute a protective envelope. In the method for assembling a semiconductor device comprising: forming a subassembly 60 comprising the circuit elements 1, 2, the plate 3 and the frame 5 as a first step, the semiconductor circuit elements 1, 2 are attached to the metal of the plate 3; fixed on one of the exposed surfaces 30, 31 and connected it to the connecting wire 2.
0A to at least the connecting conductors 7 and 8, and then as a second step, this subassembly 6
1. A method for assembling a semiconductor device, characterized in that a semiconductor device 0 is connected to a support 4 on one side and to a cover 9 on the other side. 2. A reinforcing wire 21 is provided between the plate 3 and the frame 5 to form a subassembly 60, thereby connecting the metallized surfaces 31, 33, 34, 52, 53 of the plate and the frame to each other. The method according to claim 1.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8109817A FR2506075A1 (en) | 1981-05-18 | 1981-05-18 | METHOD FOR ASSEMBLING A SEMICONDUCTOR DEVICE AND ITS PROTECTIVE HOUSING |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57196549A JPS57196549A (en) | 1982-12-02 |
JPH0119269B2 true JPH0119269B2 (en) | 1989-04-11 |
Family
ID=9258561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57080878A Granted JPS57196549A (en) | 1981-05-18 | 1982-05-15 | Method of assembling semiconductor device |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS57196549A (en) |
KR (1) | KR900002119B1 (en) |
DE (1) | DE3217345A1 (en) |
FR (1) | FR2506075A1 (en) |
GB (1) | GB2098801B (en) |
IT (1) | IT1152406B (en) |
NL (1) | NL186206C (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617647A (en) * | 1984-06-21 | 1986-01-14 | Toshiba Corp | Circuit substrate |
JPS61218151A (en) * | 1985-03-23 | 1986-09-27 | Hitachi Ltd | Semiconductor device |
JP2712461B2 (en) * | 1988-12-27 | 1998-02-10 | 日本電気株式会社 | Semiconductor device container |
DE3931634A1 (en) * | 1989-09-22 | 1991-04-04 | Telefunken Electronic Gmbh | SEMICONDUCTOR COMPONENT |
DE4201931C1 (en) * | 1992-01-24 | 1993-05-27 | Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh + Co.Kg, 4788 Warstein, De |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3340602A (en) * | 1965-02-01 | 1967-09-12 | Philco Ford Corp | Process for sealing |
FR1468122A (en) * | 1965-02-17 | 1967-02-03 | Motorola Inc | Semiconductor package |
US3515952A (en) * | 1965-02-17 | 1970-06-02 | Motorola Inc | Mounting structure for high power transistors |
DE1564815A1 (en) * | 1966-08-27 | 1970-02-26 | Standard Elek K Lorenz Ag | Process for the installation of semiconductor arrangements in miniaturized circuits |
US3641398A (en) * | 1970-09-23 | 1972-02-08 | Rca Corp | High-frequency semiconductor device |
JPS5116258B2 (en) * | 1971-10-30 | 1976-05-22 | ||
US3784884A (en) * | 1972-11-03 | 1974-01-08 | Motorola Inc | Low parasitic microwave package |
JPS5272170A (en) * | 1975-12-12 | 1977-06-16 | Nec Corp | Package for semiconductor elements |
JPS5623759A (en) * | 1979-08-01 | 1981-03-06 | Hitachi Ltd | Resin-sealed semiconductor device and manufacture thereof |
-
1981
- 1981-05-18 FR FR8109817A patent/FR2506075A1/en active Granted
-
1982
- 1982-05-08 DE DE19823217345 patent/DE3217345A1/en active Granted
- 1982-05-14 GB GB8214182A patent/GB2098801B/en not_active Expired
- 1982-05-14 NL NLAANVRAGE8202010,A patent/NL186206C/en not_active IP Right Cessation
- 1982-05-14 IT IT21289/82A patent/IT1152406B/en active
- 1982-05-15 JP JP57080878A patent/JPS57196549A/en active Granted
- 1982-05-15 KR KR8202125A patent/KR900002119B1/en active
Also Published As
Publication number | Publication date |
---|---|
NL8202010A (en) | 1982-12-16 |
FR2506075A1 (en) | 1982-11-19 |
GB2098801B (en) | 1985-01-03 |
IT1152406B (en) | 1986-12-31 |
IT8221289A0 (en) | 1982-05-14 |
GB2098801A (en) | 1982-11-24 |
DE3217345C2 (en) | 1987-07-02 |
KR900002119B1 (en) | 1990-04-02 |
JPS57196549A (en) | 1982-12-02 |
KR840000076A (en) | 1984-01-30 |
FR2506075B1 (en) | 1984-10-19 |
DE3217345A1 (en) | 1982-12-02 |
NL186206B (en) | 1990-05-01 |
NL186206C (en) | 1990-10-01 |
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