KR840000076A - Assembly method of semiconductor device and its protective skin - Google Patents

Assembly method of semiconductor device and its protective skin Download PDF

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Publication number
KR840000076A
KR840000076A KR1019820002125A KR820002125A KR840000076A KR 840000076 A KR840000076 A KR 840000076A KR 1019820002125 A KR1019820002125 A KR 1019820002125A KR 820002125 A KR820002125 A KR 820002125A KR 840000076 A KR840000076 A KR 840000076A
Authority
KR
South Korea
Prior art keywords
plate
support
semiconductor device
semiconductor circuit
assembly method
Prior art date
Application number
KR1019820002125A
Other languages
Korean (ko)
Other versions
KR900002119B1 (en
Inventor
피에르 로쉬 프랑스
Original Assignee
디.제이.삭커스
엔.브이.필립스 글로아이람펜 파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 디.제이.삭커스, 엔.브이.필립스 글로아이람펜 파브리켄 filed Critical 디.제이.삭커스
Publication of KR840000076A publication Critical patent/KR840000076A/en
Application granted granted Critical
Publication of KR900002119B1 publication Critical patent/KR900002119B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

내용 없음No content

Description

반도체장치 및 그 보호외피의 조립방법Assembly method of semiconductor device and its protective skin

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 조립체의 분해도로서, 회로소자, 플레이트 및 프레임으로 구성된 미조립체의 조립단계를 나타낸 것이며 본 발명에 의한 방법중 최종조립을 시작하는 단계이다.Figure 3 is an exploded view of the assembly, showing the assembling step of the non-assembly consisting of the circuit element, plate and frame and the step of starting the final assembly of the method according to the invention.

Claims (2)

적어도 1개의 반도체 회로소자와 1개의 보호외피를 조립하는 방법, 즉, 전기절연 및 열전도재질인 플레이트의 표면을 금속으로 피복하고 그위에 반도체회로소자를 부착하며 전기 및 열전도 지지물상에 플레이트를 배치하는 동시에 전기 절연재질인 프레임으로 플레이트를 에워싸고 프레임에는 연결도체를 마련하여 지지물상에 배치하고 덮개를 씌우며 플레이트, 지지물, 프레인 및 보호외피인 덮개로 조립체를 만드는 방법에 있어서, 제1단계에서, 플레이트(3)의 금속면(30,31)중의 하나에 부착되며 연결선(20)에 의하여 적어도 연결도체들(7,8)에 연결되는 반도체 회로소자(1,2), 플레이트(3) 및 프레임(5)을 포함하는 미조립체를 만들고, 제2단계에서 미조립체(60)를 지지물(4)과 덮개(9)에 연결하는 것을 특징으로 하는 반도체 장치 및 그 보호외피의 조립방법.A method of assembling at least one semiconductor circuit element and one protective sheath, i.e., covering the surface of the plate, which is electrically insulating and thermally conductive, with a metal, attaching the semiconductor circuit element thereon, and placing the plate on the electrical and thermally conductive support At the same time, in the first step, a method of enclosing a plate with a frame made of electrical insulation and providing a connecting conductor on the frame, placing it on a support, covering the plate, and making an assembly from a cover of a plate, a support, a plane and a protective jacket, in the first step, Semiconductor circuit elements 1, 2, plate 3 and frame attached to one of the metal surfaces 30, 31 of the plate 3 and connected to at least the connecting conductors 7, 8 by means of a connecting line 20. A method for assembling a semiconductor device and its protective envelope, comprising: forming an unassembled body comprising (5) and connecting the unassembled body (60) to the support (4) and the cover (9) in a second step. 제1항에 청구된 바와 같은 방법에 있어서, 보강선(21)을 사용하여 플레이트(3)의 금속면들을 형성하는 것을 특징으로 하는 반도체 장치 및 그 보호외피의 조립방법.The method as claimed in claim 1, wherein the reinforcing lines (21) are used to form the metal surfaces of the plates (3). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8202125A 1981-05-18 1982-05-15 Method of assembling a semiconductor device and its protective envelope KR900002119B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US8109817 1981-05-18
FR8109817A FR2506075A1 (en) 1981-05-18 1981-05-18 METHOD FOR ASSEMBLING A SEMICONDUCTOR DEVICE AND ITS PROTECTIVE HOUSING

Publications (2)

Publication Number Publication Date
KR840000076A true KR840000076A (en) 1984-01-30
KR900002119B1 KR900002119B1 (en) 1990-04-02

Family

ID=9258561

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8202125A KR900002119B1 (en) 1981-05-18 1982-05-15 Method of assembling a semiconductor device and its protective envelope

Country Status (7)

Country Link
JP (1) JPS57196549A (en)
KR (1) KR900002119B1 (en)
DE (1) DE3217345A1 (en)
FR (1) FR2506075A1 (en)
GB (1) GB2098801B (en)
IT (1) IT1152406B (en)
NL (1) NL186206C (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617647A (en) * 1984-06-21 1986-01-14 Toshiba Corp Circuit substrate
JPS61218151A (en) * 1985-03-23 1986-09-27 Hitachi Ltd Semiconductor device
JP2712461B2 (en) * 1988-12-27 1998-02-10 日本電気株式会社 Semiconductor device container
DE3931634A1 (en) * 1989-09-22 1991-04-04 Telefunken Electronic Gmbh SEMICONDUCTOR COMPONENT
DE4201931C1 (en) * 1992-01-24 1993-05-27 Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh + Co.Kg, 4788 Warstein, De

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340602A (en) * 1965-02-01 1967-09-12 Philco Ford Corp Process for sealing
US3515952A (en) * 1965-02-17 1970-06-02 Motorola Inc Mounting structure for high power transistors
FR1468122A (en) * 1965-02-17 1967-02-03 Motorola Inc Semiconductor package
DE1564815A1 (en) * 1966-08-27 1970-02-26 Standard Elek K Lorenz Ag Process for the installation of semiconductor arrangements in miniaturized circuits
US3641398A (en) * 1970-09-23 1972-02-08 Rca Corp High-frequency semiconductor device
JPS5116258B2 (en) * 1971-10-30 1976-05-22
US3784884A (en) * 1972-11-03 1974-01-08 Motorola Inc Low parasitic microwave package
JPS5272170A (en) * 1975-12-12 1977-06-16 Nec Corp Package for semiconductor elements
JPS5623759A (en) * 1979-08-01 1981-03-06 Hitachi Ltd Resin-sealed semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
NL8202010A (en) 1982-12-16
NL186206C (en) 1990-10-01
IT8221289A0 (en) 1982-05-14
GB2098801A (en) 1982-11-24
KR900002119B1 (en) 1990-04-02
FR2506075A1 (en) 1982-11-19
IT1152406B (en) 1986-12-31
JPH0119269B2 (en) 1989-04-11
DE3217345C2 (en) 1987-07-02
GB2098801B (en) 1985-01-03
NL186206B (en) 1990-05-01
DE3217345A1 (en) 1982-12-02
JPS57196549A (en) 1982-12-02
FR2506075B1 (en) 1984-10-19

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