JPH0249027Y2 - - Google Patents

Description

[Detailed explanation of the invention] (1) Technical field of the invention This invention relates to an EFM frame synchronization detection circuit for detecting a frame synchronization signal from an EFM (Eight to Fourteen Modulation) signal reproduced from a compact disk, etc. By detecting a specific pattern in the synchronization signal and also detecting the signal pattern immediately before and after it,
This is intended to prevent a signal that is not a frame synchronization signal from being mistakenly detected as a frame synchronization signal.

(2) Prior art For example, in a compact disk, 588
Information is recorded frame by frame, with channel bits as one frame. Each frame is
A frame synchronization signal is provided at the beginning, followed by subcode data, sample data, error correction data, etc. During playback, a frame synchronization signal is detected to determine the position of each data in the frame.

By the way, the EFM signal recorded on the disk is
The pattern is determined to avoid consecutive "1's" and to have between two "1's" and no more than 10 "0's". Now, if we consider the combination of one "1" followed by consecutive "0" as one signal pattern, and express the length of that signal pattern as the product of the number of channel bits and the time width T of one channel bit. (For example, one “1”
3T is a pattern in which 2 “0”s follow 1, and 4 is a pattern in which 1 “1” is followed by 3 “0s”.
T), the EFM signal has a minimum length of 3T, and 11
It is configured as a combination of signal patterns whose maximum length is T. The frame synchronization signal consists of 24 channel bits as shown in Figure 1.
11T:1 repeating the 11T signal pattern twice
It is defined to include a pattern called 1T that is not used elsewhere.

Therefore, in the past, this 11T:11T
The frame synchronization signal was detected by detecting the pattern. FIG. 2 shows a conventional EFM frame synchronization detection circuit configured in this manner. Here, the notation method of the logic circuit is simplified. One line 2 is drawn on the input side of NOR circuit 1, and the signals of the lines whose intersections with it are circled are input to NOR circuit 1. (The same notation will be used below). The circuit in Figure 2 consists of a 23-stage shift register 3,
3-1 to 3-23, the first stage 3-1 is played from a compact disk, and the NRZ
- Input the EFM signal converted to I signal and set the specified clocks φ3, φ4 (588
4.32MH clock)
The signals of each stage 3-1 to 3-23 are transferred to the first stage 3-
1, the 12th stage 3-12, and the 23rd stage 3-23 are inverted by inverters 4, 5, and 6, respectively, and the other stages are input to the NOR circuit 1 as they are. According to such a configuration, when a signal with a pattern of 11T:11T is input, the signals of the first stage 3-1, the 12th stage 3-12, and the 23rd stage 3-23 become "1", and the other signals become "1". The stage becomes "0", all the inputs of the NOR circuit 1 become "0", and the output becomes "1", so that a frame synchronization signal can be detected.

However, the EFM signal may be lost due to scratches on the disk, or different data may arrive.
At that time, if a pattern of 11T:11T happened to occur, the circuit shown in FIG. 2 had the disadvantage of erroneously detecting it as a frame synchronization signal.

(3) Purpose of the invention The purpose of this invention is to improve the drawbacks of the prior art described above. Even if an 11T:11T pattern occurs outside of the frame synchronization signal due to scratches on the disk, frame synchronization is still possible. This is intended to prevent erroneous detection of signals.

(4) Structure of the invention This invention uses the characteristics of EFM signals to
11T obtained from the EFM signal: By detecting the signal pattern immediately before and after the 11T signal pattern, it is possible to determine whether it is in a regular frame synchronization signal or by chance due to a data error.
T:11T is determined. That is, as mentioned above, the EFM signal is defined as a continuum of signal patterns from 3T to 11T, and there is no pattern of two consecutive 11Ts except in the frame synchronization signal, and
A pattern with three or more consecutive 1Ts is never used, and if it is a regular frame synchronization signal, no 11T signal pattern will occur before or after it (if it occurs, it will be a 1T that should not have been used).
This results in a pattern of three consecutive 1Ts. )
Therefore, 11 due to the regular frame synchronization signal.
In the case of a T:11T signal, the signal patterns immediately before and after it are always greater than or equal to 3T and less than or equal to 10T.
Therefore, the signal patterns immediately before and after the detected 11T:11T signal pattern are detected, and if both are between 3T and 10T, it is determined that it is due to a frame synchronization signal. Any data other than 3T to 10T is determined to be incorrect data.

(5) Example of the invention An example of the invention is shown in Fig. 3. The circuit shown in FIG. 3 includes a 43-stage shift register 9.
The EFM signal reproduced from the disk and further converted into an NRZ-I signal is inputted from the first stage 9A-1 and sequentially shifted using 4.32 MHz clocks φ3 and φ4. The shift register 9 has the following functions:
It is divided into three sections 9A, 9B, and 9C.

Section 9B is a part where a signal pattern of 11T:11T is detected, and the first stage 9B that constitutes this section
The registers in each stage from -1 to 23rd stage 9B-23 are the registers in the first stage 3 in the conventional circuit shown in FIG.
They correspond to the registers from -1 to 23rd stage 3-23, respectively. Therefore, the first stage 9B- of the circuit of FIG. 3 corresponds to the first stage 3-1, the twelfth stage 3-12, and the twenty-third stage 3-23 of the circuit of FIG.
Inverters 10, 11, and 12 are connected to the outputs of 1, 12th stage 9B-12, and 23rd stage 9B-23, respectively. These inverters 10, 11, 12
output and other stages 9B-2 to 9B-1
Each output of 1, 9B-13 to 9B-22 is input to a NOR circuit 13 for detecting a frame synchronization signal.

Section 9C is a portion for determining whether the signal pattern immediately before the signal pattern of 11T:11T is greater than or equal to 3T and less than or equal to 10T. The first of this section
The outputs of stage 9C-1 and second stage 9C-2 are input to NOR circuit 13, respectively. These signals are used to determine whether it is 3T or more. That is, when "1" is set in the first stage 9C-1, it is determined to be 1T (a state in which there is no "0" between it and the "1" in the previous stage 9B-23), and the second stage
If “1” stands on stage 9C-2, 2T (9B-
In both cases, the voltage is below 2T, so the frame synchronization signal detection NOR circuit 13 is turned off (when the output is "0"). (means to be in a state)
The EFM frame synchronization detection signal is not output.
If both the first stage 9C-1 and the second stage 9C-2 are "0", it is determined that the voltage is 3T or more, so the frame synchronization detection NOR circuit 13 is enabled to turn on.

Section 9C, 3rd stage 9C-3 to 10th stage 9C-1
The outputs of 0 are respectively input to the NOR circuit 14. This NOR circuit 14 detects whether the voltage is 10T or less. That is, the third stage 9C
If all of the 10 stages 9C-10 from -3 to 9C-10 are "0", it is determined that the value is 11T or more (all from the 1st stage 9C-1 to the 10th stage 9C-10 are "0"), so the output of the NOR circuit 14 is set to "1" to turn off the EFM frame synchronization detection NOR circuit 13. 3rd to 3rd stage
When “1” stands on any of the 10 rows, 1
Since it is 0T or less (when "1" is set in the third stage 9C-3, it is 3T and "1" is set in the fourth stage 9C-4).
When is standing, 4T,..., 10th stage 9C-1
When "1" is set to 0 (10T), the output of the NOR circuit 14 becomes "0", and the synchronization detection NOR circuit 13 becomes in a state where it can be turned on. In addition, in detecting whether the temperature is 10T or less, the first stage 9C-1 and the second stage
Those who do not see stage 9C-2 are the first stage 9C-1 and the second stage.
This is because when any of the stages 9C-2 is "1", the condition of 3T or more is not satisfied, and there is no need to check whether it is 10T or less.

Section 9A is a portion for determining whether the signal pattern immediately after the signal pattern of 11T:11T is greater than or equal to 3T and less than or equal to 10T. The outputs of the ninth stage 9A-9 and the tenth stage 9A-10 of this section 9A are input to the NOR circuit 13, respectively. These signals are 11 due to the same effect as the outputs of the second stage 9C-2 and the first stage 9C-1 in the section 9C.
T: Used to detect whether the signal pattern immediately after 11T is 3T or more. In other words, if both the 9th stage 9A-9 and the 10th stage 9A-10 are "0", it is determined that it is 3T or more.
The NOR circuit 13 for detecting EFM frame synchronization is set in a state where it can be turned on, and when either one is set to "1", it is determined that it is 2T or less, and the NOR circuit 13 for EFM frame synchronization detection is turned off.

1st stage 9A-1 to 8th stage 9A-8 of section 9A
The outputs of are respectively input to the NOR circuit 15.
This NOR circuit 15 is the NOR circuit 1 of the section 9C.
11T: It is detected whether the signal pattern immediately after 11T is equal to or less than 10T by the same operation as in No. 4. That is, when all of the first stage 9A-1 to the eighth stage 9A-8 are "0", 11
Determining that it is T or more, the NOR circuit 15 outputs "1" and turns off the EFM frame synchronization detection NOR circuit 13. In addition, the first stage 9A-1 to the eighth stage 9A-
When any of
The frame synchronization detection NOR circuit 13 is now in a state where it can be turned on.

According to the above configuration, when a regular frame synchronization signal in which 11T:11T is inputted to the section 9B of the shift register 9, the sections 9A and 9 of the preceding and following sections
The signal patterns of C are both 3T to 10T, and the outputs of NOR circuits 13 and 14 are both “0”.
Therefore, the EFM frame synchronization detection NOR circuit 13 is turned on and an EFM frame synchronization detection signal (signal "1") is output.

In addition, due to erroneous detection due to scratches on the disk, etc.
When a signal pattern of 1T:11T occurs, the signal patterns before and after it are not necessarily less than 2T or more than 11T, but the influence of scratches etc. may extend to the areas before and after the 11T:11T pattern, resulting in a signal pattern of less than 2T or more than 11T. There is a high possibility that a signal pattern of 11T or higher will occur, or
T:11T pattern, one 11T is regular
The other 11 is due to the EFM frame synchronization signal.
If T is incorrect data, its 11T:11
Since the other 11T pattern based on the regular EFM frame synchronization signal occurs immediately before or after T, in such a case, either the output of the NOR circuit 14 or 15 becomes "1". Therefore, the NOR circuit 13 is turned off, and the EFM frame synchronization detection signal is not output, making it possible to prevent erroneous detection of the EFM frame synchronization signal.

(6) Effects of the invention As explained above, according to this invention,
In addition to detecting the 11T:11T signal pattern in the EFM frame synchronization signal, the signal patterns before and after it are also detected, so that erroneous detection of the EFM frame synchronization signal can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the data format of the EFM signal (NRZ-I display) in a compact disc, Fig. 2 is a circuit diagram showing a conventional EFM frame synchronization detection circuit, and Fig. 3 is an example of an embodiment of this invention. FIG. 1, 13...NOR circuit for EFM frame synchronization signal detection, 3, 9...Shift register.

Claims (1)

[Scope of utility model registration request] a first circuit that detects a 11T:11T signal pattern that is a 11T signal pattern twice in succession from an EFM signal;
T: a second circuit that detects that the signal pattern immediately before the signal pattern of 11T is one of 3T to 10T;
a third circuit that detects that the signal pattern immediately after the signal pattern of T:11T is one of 3T to 10T, and when each of the predetermined signal patterns is detected by the first to third circuits; ,EFM
and a circuit that outputs a frame synchronization detection signal.
EFM frame synchronization detection circuit.