JPS60120561U - EFM frame synchronization detection circuit - Google Patents
EFM frame synchronization detection circuitInfo
- Publication number
- JPS60120561U JPS60120561U JP566184U JP566184U JPS60120561U JP S60120561 U JPS60120561 U JP S60120561U JP 566184 U JP566184 U JP 566184U JP 566184 U JP566184 U JP 566184U JP S60120561 U JPS60120561 U JP S60120561U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frame synchronization
- efm
- synchronization detection
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はコンパクトディスクにおけるEFM信号のデー
タフォーマット(NRZ−1表示)を示す図、第2図は
従来におけるEFMフレーム同期検出回路を示す回路図
、第3図はこの考案の一実施例を示す回路図である。
1.13・・・EFMフレーム同期信号検出用ノア回路
、3.9−・・シフトレジスタ。
會
EFM 7番−A同朋旅幻縛
第3図
ノ
ーFigure 1 is a diagram showing the data format (NRZ-1 display) of the EFM signal on a compact disc, Figure 2 is a circuit diagram showing a conventional EFM frame synchronization detection circuit, and Figure 3 is an example of an embodiment of this invention. It is a circuit diagram. 1.13...NOR circuit for EFM frame synchronization signal detection, 3.9-...Shift register. Kai EFM No. 7-A Doho Travel Genbaku Figure 3 No
Claims (1)
IT: I ITの信号パターンを検出する第1の回
路と、前記EFM信号における前記11T:11Tの信
号パターンの直前の信号パターンが3T〜IOTのいず
れかであることを検出する第2の回路と、前記EFM信
号における前記11T:11Tの信号パターンの直後の
信号パターンが3T〜IOTのいずれかであることを検
出する第3の回路と、前記第1〜第3の回路により前記
各所定の信号パターンが検出されたとき、EFMフレー
ム同期検出信号を出力する回路とを具えたEFMフレー
ム同期検出回路。I that the signal pattern of 11T is repeated twice from the EFM signal
IT: A first circuit that detects a signal pattern of IIT, and a second circuit that detects that a signal pattern immediately before the signal pattern of 11T:11T in the EFM signal is one of 3T to IOT. , a third circuit that detects that the signal pattern immediately after the 11T:11T signal pattern in the EFM signal is one of 3T to IOT, and the first to third circuits detect each of the predetermined signals. An EFM frame synchronization detection circuit comprising: a circuit for outputting an EFM frame synchronization detection signal when a pattern is detected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP566184U JPS60120561U (en) | 1984-01-19 | 1984-01-19 | EFM frame synchronization detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP566184U JPS60120561U (en) | 1984-01-19 | 1984-01-19 | EFM frame synchronization detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60120561U true JPS60120561U (en) | 1985-08-14 |
JPH0249027Y2 JPH0249027Y2 (en) | 1990-12-21 |
Family
ID=30482370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP566184U Granted JPS60120561U (en) | 1984-01-19 | 1984-01-19 | EFM frame synchronization detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60120561U (en) |
-
1984
- 1984-01-19 JP JP566184U patent/JPS60120561U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0249027Y2 (en) | 1990-12-21 |
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