JPH0247863B2 - - Google Patents
Info
- Publication number
- JPH0247863B2 JPH0247863B2 JP56157430A JP15743081A JPH0247863B2 JP H0247863 B2 JPH0247863 B2 JP H0247863B2 JP 56157430 A JP56157430 A JP 56157430A JP 15743081 A JP15743081 A JP 15743081A JP H0247863 B2 JPH0247863 B2 JP H0247863B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- polycrystalline silicon
- film region
- aluminum
- fuse device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 58
- 229910052782 aluminium Inorganic materials 0.000 claims description 46
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 239000010408 film Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 230000004927 fusion Effects 0.000 claims description 2
- 238000007664 blowing Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 230000015654 memory Effects 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Description
【発明の詳細な説明】
本発明は、フイールドプログラマブル集積回路
等に用いられる低電流、低電圧で溶断可能なヒユ
ーズ装置と、そのヒユーズ装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fuse device used in field programmable integrated circuits and the like that can be blown with low current and low voltage, and a method for manufacturing the fuse device.
ヒユーズ装置は、フイールドプログラマブル集
積回路における固定情報の蓄積媒体として有用で
ある。例えば、ヒユーズ形読出専用メモリのメモ
リセル、又は冗長回路構成を採つた集積回路の冗
長回路の切替装置に広く用いられている。これら
のヒユーズ装置は、半導体基板上にトランジスタ
と共に混載され、ヒユーズ装置の溶断に必要な電
流はトランジスタを介して供給されている。従つ
て、この種のヒユーズ装置は、低電流でかつ低電
圧で溶断できることが望まれる。 Fuse devices are useful as fixed information storage media in field programmable integrated circuits. For example, it is widely used in switching devices for memory cells of fuse-type read-only memories or redundant circuits of integrated circuits having a redundant circuit configuration. These fuse devices are mounted together with transistors on a semiconductor substrate, and the current necessary for blowing out the fuse devices is supplied through the transistors. Therefore, it is desired that this type of fuse device can be blown with low current and low voltage.
しかし、従来のこの種のヒユーズ装置では、
Ni−Cr薄膜あるいは多結晶シリコン薄膜のよう
な融点の高い材料で構成していたため、溶断には
比較的大電流と高電圧を必要としていた。例え
ば、市販されているNi−Cr薄膜や多結晶シリコ
ン薄膜を用いた従来のヒユーズ装置では、20〜
30mA、12〜25Vを必要とする欠点があつた。ま
た、ヒユーズ装置に電流を供給するために大形の
トランジスタや高圧回路を必要とする欠点があつ
た。 However, with this type of conventional fuse device,
Because they were made of materials with high melting points, such as Ni-Cr thin films or polycrystalline silicon thin films, they required relatively large currents and voltages to fuse. For example, in conventional fuse devices using commercially available Ni-Cr thin films or polycrystalline silicon thin films,
It had the disadvantage of requiring 30mA and 12 to 25V. Another drawback was that a large transistor and high voltage circuit were required to supply current to the fuse device.
本発明は、多結晶シリコン薄膜領域と、シリコ
ンとアルミニウムの混和した薄膜領域とよりな
り、前記２つの領域の境界が溶断部に設けられた
ことを特徴とし、その目的は、低電流低電圧で溶
断可能にしてしかも構成の簡単なヒユーズ装置お
よびそのヒユーズ装置の製造方法を提供すること
にある。 The present invention is characterized in that it consists of a polycrystalline silicon thin film region and a mixed silicon and aluminum thin film region, and the boundary between the two regions is provided at a fusing part, and its purpose is to provide low current and low voltage. It is an object of the present invention to provide a fuse device which can be fused and has a simple configuration, and a method for manufacturing the fuse device.
本願発明者らは、多結晶シリコン薄膜領域とシ
リコンとアルミニウムの混和した薄膜領域との境
界を経由して電流を流すと、境界近傍が低電流で
溶断することを発見した。この発見に基づき、多
結晶シリコン薄膜領域とシリコンとアルミニウム
の混和した薄膜領域との境界を溶断部に設けたこ
とを特徴とする本発明のヒユーズ装置を提案する
ものである。 The inventors of the present application have discovered that when a current is passed through the boundary between a polycrystalline silicon thin film region and a thin film region in which silicon and aluminum are mixed, the vicinity of the boundary is fused at a low current. Based on this discovery, we propose the fuse device of the present invention, which is characterized in that the boundary between the polycrystalline silicon thin film region and the silicon-aluminum mixed thin film region is provided in the fusing part.
第１図は本発明のヒユーズ装置の基本構成であ
る。１と２は電極、３と４は溶断部であり、１と
３は多結晶シリコン薄膜領域、２と４はシリコン
とアルミニウムの混和した薄膜領域である。５は
前記２領域の境界、６と７はリード線である。 FIG. 1 shows the basic configuration of the fuse device of the present invention. 1 and 2 are electrodes, 3 and 4 are fusing parts, 1 and 3 are polycrystalline silicon thin film regions, and 2 and 4 are thin film regions in which silicon and aluminum are mixed. 5 is the boundary between the two regions, and 6 and 7 are lead lines.
第２図ａ〜ｅは本発明のヒユーズ装置の実施例
で、第１図の基本構成の変形である。 2a to 2e show an embodiment of the fuse device of the present invention, which is a modification of the basic configuration of FIG. 1.
第２図ａは溶断部が３領域で形成されたヒユー
ズ装置である。１と１′は電極、３，３′および４
は溶断部、６と７はリード線である。１，１′，
３および３′は多結晶シリコン領域、４はシリコ
ンとアルミニウムの混和した薄膜領域、５と５′
は各２領域の境界である。 FIG. 2a shows a fuse device in which the fusing section is formed in three regions. 1 and 1' are electrodes, 3, 3' and 4
is a fusing part, and 6 and 7 are lead wires. 1,1′,
3 and 3' are polycrystalline silicon regions, 4 is a mixed thin film region of silicon and aluminum, and 5 and 5'
is the boundary between each two regions.
第２図ｂは溶断部が３領域で形成された別のヒ
ユーズ装置である。２と２′は電極、３，４およ
び４′は溶断部、６と７はリード線である。２，
２′，４および４′はシリコンとアルミニウムの混
和した薄膜領域、３は多結晶シリコン薄膜領域で
形成された溶断部、５と５′は各領域の境界であ
る。 FIG. 2b shows another fuse device in which the fusing section is formed in three regions. 2 and 2' are electrodes, 3, 4 and 4' are fusing parts, and 6 and 7 are lead wires. 2,
2', 4 and 4' are thin film regions in which silicon and aluminum are mixed, 3 is a fused portion formed of a polycrystalline silicon thin film region, and 5 and 5' are boundaries between the respective regions.
第２図ｃは、第１図の基本構成のシリコンとア
ルミニウムの混和した薄膜領域の電極としてアル
ミニウム薄膜領域８を有するヒユーズ装置であ
る。 FIG. 2c shows a fuse device having an aluminum thin film region 8 as an electrode of the silicon and aluminum mixed thin film region having the basic structure shown in FIG.
第２図ｄは第２図ｃの変形でシリコンとアルミ
ニウムの混和した薄膜領域の一端を覆うアルミニ
ウム薄膜領域８を電極としたヒユーズ装置であ
る。 FIG. 2d shows a fuse device in which an aluminum thin film region 8 covering one end of a thin film region in which silicon and aluminum are mixed is used as an electrode, which is a modification of FIG. 2c.
第２図ｅは第２図ａのシリコンとアルミニウム
の混和した薄膜領域の中央部を覆うアルミニウム
薄膜領域８を設けたヒユーズ装置である。 FIG. 2e shows a fuse device provided with an aluminum thin film region 8 covering the center of the silicon and aluminum mixed thin film region of FIG. 2a.
第２図ａ，ｂ，ｅは２個の境界をもつヒユーズ
装置であつて、対称構造という特徴がある。 Figures 2a, b, and e are fuse devices with two boundaries, which are characterized by a symmetrical structure.
第２図ｃ，ｄ，ｅは、後述のように、本発明の
ヒユーズ装置の製造法と関連して、実用価値の高
い形態である。すなわち、用いられるアルミニウ
ム薄膜領域から、アルミニウムを多結晶シリコン
薄膜領域に浸透させることにより、シリコンとア
ルミニウムの混和した薄膜領域を容易に形成でき
る。 2c, d, and e are embodiments of high practical value in connection with the method of manufacturing the fuse device of the present invention, as will be described later. That is, by permeating aluminum from the aluminum thin film region used into the polycrystalline silicon thin film region, a thin film region in which silicon and aluminum are mixed can be easily formed.
以上の実施例で示したように、本発明のヒユー
ズ装置の基本は、溶断部に多結晶シリコン薄膜領
域とシリコンとアルミニウムの混和した薄膜領域
の境界を設けたことである。境界の個数、電極の
構成、材料、各部の形状等は任意に設定できる。 As shown in the above embodiments, the basic principle of the fuse device of the present invention is that the boundary between the polycrystalline silicon thin film region and the mixed silicon and aluminum thin film region is provided in the fusing portion. The number of boundaries, electrode configuration, material, shape of each part, etc. can be set arbitrarily.
次に、本発明のヒユーズ装置の作用について述
べる。第１図において、電極１と２間に電圧を印
加し、溶断部３および４に電流を流すことによつ
て境界５近傍を第３図に示す如く溶断できる。本
発明の装置においては、溶断時の電流と電圧が従
来のヒユーズ装置に比較して大幅に小さい利点が
ある。 Next, the operation of the fuse device of the present invention will be described. In FIG. 1, by applying a voltage between electrodes 1 and 2 and passing current through fusing parts 3 and 4, the vicinity of boundary 5 can be fused as shown in FIG. 3. The device of the present invention has the advantage that the current and voltage at the time of blowing are significantly lower than in conventional fuse devices.
第４図は第２図ｄに示した実施例についての実
験結果で、電極間の印加電圧に対する溶断部を流
れる電流の特性である。印加電圧の増加と共に電
流は増加するが、電流のピーク値において本ヒユ
ーズ装置は溶断する。溶断時の電流のピーク値を
溶断電流、電流のピーク値における印加電圧を溶
断電圧と呼ぶ。 FIG. 4 shows the experimental results for the embodiment shown in FIG. 2d, which shows the characteristics of the current flowing through the fusing portion with respect to the voltage applied between the electrodes. The current increases as the applied voltage increases, but the fuse device blows at the peak value of the current. The peak value of current at the time of fusing is called fusing current, and the applied voltage at the peak value of current is called fusing voltage.
実験に使用したヒユーズ装置の各部の寸法を第
２図ｄ中に示したように溶断部の膜厚ｄ、幅ｗ、
多結晶シリコン薄膜領域の長さｌで示す。溶断部
の多結晶シリコン薄膜領域の長さｌは本発明のヒ
ユーズ装置の溶断特性にとつて重要である。すな
わち、溶断電圧はシリコンとアルミニウムの混和
した薄膜領域に比べ非常に抵抗の高い多結晶シリ
コン薄膜領域に集中してかかり、該多結晶シリコ
ン薄膜領域で溶断に必要な電力のほとんどが消費
されるからである。いいかえれば、シリコンとア
ルミニウムの混和した薄膜領域の長さは、溶断特
性に大きな影響を与えないため、任意に設定でき
る。 The dimensions of each part of the fuse device used in the experiment are shown in Figure 2 d, the film thickness d, width w,
The length of the polycrystalline silicon thin film region is indicated by l. The length l of the polycrystalline silicon thin film region of the blowout portion is important for the blowout characteristics of the fuse device of the present invention. In other words, the fusing voltage is concentrated on the polycrystalline silicon thin film region, which has much higher resistance than the thin film region where silicon and aluminum are mixed, and most of the power required for fusing is consumed in the polycrystalline silicon thin film region. It is. In other words, the length of the thin film region in which silicon and aluminum are mixed can be set arbitrarily because it does not have a large effect on the fusing characteristics.
第４図の特性測定に用いた本発明のヒユーズ装
置の第２図ｄに示した溶断部の寸法は、膜厚ｄが
100nm、幅ｗが3μmであり、多結晶シリコン薄膜
領域の長さｌについては、特性９が2μm、特性１
０が7μm、特性１１が17μm、特性１２が6μmで
ある。多結晶シリコン薄膜領域の比抵抗は特性
９，１０，１１が約５×10-3Ω・cm、特性１２が
約７×10-3Ω・cmである。 The dimensions of the fusing part shown in FIG. 2 d of the fuse device of the present invention used for the characteristic measurement of FIG. 4 are as follows:
100 nm, the width w is 3 μm, and the length l of the polycrystalline silicon thin film region is 2 μm for characteristic 9 and 2 μm for characteristic 1.
0 is 7 μm, characteristic 11 is 17 μm, and characteristic 12 is 6 μm. The specific resistance of the polycrystalline silicon thin film region is approximately 5×10 -3 Ω·cm for characteristics 9, 10, and 11, and approximately 7×10 −3 Ω·cm for characteristic 12.
なお、特性１３は多結晶シリコン薄膜で形成さ
れた従来のヒユーズ装置の実験結果で、本発明の
ヒユーズ装置との比較のために記載してある。従
来の多結晶シリコン薄膜領域の溶断部の膜厚ｄは
100nm、幅ｗは3μm、比抵抗は約５×10-3Ω・cm
であり、特性９〜１１の本発明のヒユーズ装置の
多結晶シリコン薄膜領域と全く同じである。但
し、溶断部の多結晶シリコン薄膜領域の長さｌは
10μmである。 Note that characteristic 13 is an experimental result of a conventional fuse device formed of a polycrystalline silicon thin film, and is described for comparison with the fuse device of the present invention. The film thickness d of the fused portion of the conventional polycrystalline silicon thin film region is
100nm, width w is 3μm, specific resistance is approximately 5×10 -3 Ω・cm
This is exactly the same as the polycrystalline silicon thin film region of the fuse device of the present invention having characteristics 9 to 11. However, the length l of the polycrystalline silicon thin film region of the fused part is
It is 10μm.
実験結果から明らかなように、従来のヒユーズ
装置の溶断電流が約11mAであるのに対し、本発
明のヒユーズ装置では1/2以下の約5mAと低電流
である。また、従来のヒユーズ装置では、溶断部
の多結晶シリコン薄膜領域の長さｌによつて溶断
電流が変る欠点があつたが、本発明のヒユーズ装
置の溶断電流は特性９，１０，１１から明らかな
ようにほぼ一定である。従つて、溶断部の多結晶
シリコン薄膜領域の長さｌを短縮することによつ
て、溶断電流を一定に保つたまま溶断電圧を低減
できる。例えば、溶断部の多結晶シリコン薄膜領
域の長さｌが2μmの本発明のヒユーズ装置では、
特性９から分かるように、溶断電圧を約3.5Vと
従来のヒユーズ装置の1/3以下に低減できる。従
つて、溶断に必要な電力は従来のヒユーズ装置の
１／６以下に低減できる。このように、本発明のヒ
ユーズ装置では、溶断電流と溶断電圧を大幅に低
減でき、溶断に必要な電力を大幅に低減できる利
点がある。 As is clear from the experimental results, while the conventional fuse device has a blowing current of about 11 mA, the fuse device of the present invention has a low current of about 5 mA, which is less than half that. In addition, the conventional fuse device had a drawback that the blowing current varied depending on the length l of the polycrystalline silicon thin film region of the blowing part, but the blowing current of the fuse device of the present invention is clear from characteristics 9, 10, and 11. It is almost constant. Therefore, by shortening the length l of the polycrystalline silicon thin film region of the fusing part, the fusing voltage can be reduced while keeping the fusing current constant. For example, in the fuse device of the present invention in which the length l of the polycrystalline silicon thin film region of the fusion part is 2 μm,
As can be seen from characteristic 9, the fusing voltage can be reduced to approximately 3.5V, less than 1/3 of that of conventional fuse devices. Therefore, the power required for blowing can be reduced to 1/6 or less of that of conventional fuse devices. As described above, the fuse device of the present invention has the advantage that the fusing current and the fusing voltage can be significantly reduced, and the power required for fusing can be significantly reduced.
また、従来のヒユーズ装置の溶断電流は溶断部
の材料の比抵抗により変化する欠点があつた。し
かし、本発明のヒユーズ装置の溶断電流は、特性
１２から分かるように多結晶シリコン薄膜領域の
比抵抗がかなり変動しても一定に保たれる。すな
わち、本発明のヒユーズ装置では多結晶シリコン
薄膜領域の比抵抗のばらつきを大幅に許容でき、
ヒユーズ装置の設計および製造上のマージンを広
くとれる利点がある。 Further, the fusing current of the conventional fuse device has a drawback that it varies depending on the specific resistance of the material of the fusing part. However, the blowing current of the fuse device of the present invention remains constant even if the resistivity of the polycrystalline silicon thin film region varies considerably, as seen from characteristic 12. In other words, the fuse device of the present invention can largely tolerate variations in resistivity in the polycrystalline silicon thin film region.
This has the advantage of allowing a wide margin in the design and manufacturing of the fuse device.
次に、第５図を用いて本発明のヒユーズ装置の
製造方法の一例を工程順に説明する。第５図は第
２図ｄに示したヒユーズ装置の一点鎖線に沿つた
断面構造を工程順に示した図であり、図ａ〜ｆは
以下の工程(a)〜(f)に対応している。 Next, an example of a method for manufacturing a fuse device according to the present invention will be explained in order of steps with reference to FIG. Fig. 5 is a diagram showing the cross-sectional structure of the fuse device shown in Fig. 2 d along the dashed line in the order of steps, and Figs. a to f correspond to the following steps (a) to (f). .
工程 (a)
絶縁基板１４の表面に、例えば、化学気相成長
法で多結晶シリコン薄膜１５を堆積する。多結晶
シリコン薄膜15の堆積中あるいは堆積後、りん、
ひ素等の特定の不純物をドープし、熱処理を行
い、多結晶シリコン薄膜１５の抵抗を所定の値に
設定する。Step (a) A polycrystalline silicon thin film 15 is deposited on the surface of the insulating substrate 14 by, for example, chemical vapor deposition. During or after the deposition of the polycrystalline silicon thin film 15, phosphorus,
A specific impurity such as arsenic is doped, heat treatment is performed, and the resistance of the polycrystalline silicon thin film 15 is set to a predetermined value.
工程 (b)
多結晶シリコン薄膜１５をフオトリソグラフイ
技術により加工成形し、電極１および溶断部３を
つくる。Step (b) The polycrystalline silicon thin film 15 is processed and formed by photolithography to form the electrode 1 and the fusing portion 3.
工程 (c)
アルミニウム薄膜１６を例えば真空蒸着法によ
つて堆積する。Step (c) The aluminum thin film 16 is deposited, for example, by vacuum evaporation.
工程 (d)
フオトリソグラフイ技術により、アルミニウム
薄膜１６が電極１および溶断部３の多結晶シリコ
ン薄膜領域の一部に接触するように加工成形し、
電極８をつくる。Step (d) Processing and forming the aluminum thin film 16 so as to contact the electrode 1 and a part of the polycrystalline silicon thin film region of the fusing part 3 using photolithography technology;
Make electrode 8.
工程 (e)
熱処理を行い、電極８と溶断部３の接触部１７
よりアルミニウムを溶断部３の多結晶シリコン・
薄膜領域中に浸透させ、シリコンとアルミニウム
の混和した薄膜領域の溶断部４を形成する。第５
図(e)中に示した溶断部４の長さｘを熱処理の温度
と時間によつて制御し、多結晶シリコン薄膜領域
とシリコンとアルミニウムの混和した薄膜領域と
の境界５を所定の位置に設定する。Step (e) Heat treatment is performed to form the contact portion 17 between the electrode 8 and the fusing portion 3.
The polycrystalline silicon of the fusing part 3 is made of aluminum.
It penetrates into the thin film region to form a fusing portion 4 in the thin film region in which silicon and aluminum are mixed. Fifth
The length x of the fusing part 4 shown in Fig. (e) is controlled by the temperature and time of the heat treatment, and the boundary 5 between the polycrystalline silicon thin film region and the silicon and aluminum mixed thin film region is set at a predetermined position. Set.
工程 (f)
酸化シリコン等の絶縁薄膜１８を堆積し、フオ
トリソグラフイ技術によりスルホール１９を形成
し、電極１および電極８からそれぞれリード線６
および７を引き出し、ヒユーズ装置を完成する。Step (f) Deposit an insulating thin film 18 such as silicon oxide, form through holes 19 using photolithography, and connect lead wires 6 from electrodes 1 and 8, respectively.
and 7 to complete the fuse device.
なお、以上説明した工程以外にも、本発明のヒ
ユーズ装置を実現する多くの製造方法がある。例
えば、工程(a)中の不純物のドープと工程(b)の加工
成形を逆順にすること、工程(b)と工程(c)の間に絶
縁薄膜を形成する工程と、多結晶シリコン薄膜と
アルミニウム薄膜とを接触させるためのスルホー
ル形成工程を含めること等多くの変形をとること
ができる。 In addition to the steps described above, there are many manufacturing methods for realizing the fuse device of the present invention. For example, doping of impurities in step (a) and processing and forming in step (b) may be performed in the reverse order, forming an insulating thin film between step (b) and step (c), and forming a polycrystalline silicon thin film. Many variations can be made, such as including a through-hole formation step for contacting the aluminum thin film.
以上、第２図(d)の本発明のヒユーズ装置の製造
法について述べたが、第２図(a)，(b)，(c)，(d)のヒ
ユーズ装置のシリコンとアルミニウムの混和した
薄膜領域および境界も第２図(d)と同様の製造方法
によつて形成できる。すなわち、所定の電極およ
び溶断部を多結晶シリコン薄膜領域で形成した
後、この多結晶シリコン薄膜領域の所定の位置に
接触したアルミニウム薄膜領域を形成する。例え
ば、第２図(a)，(b)の場合には溶断部の中央の多結
晶シリコン薄膜領域に、同図(b)の場合には溶断部
の中央部を除く多結晶シリコン薄膜領域に、同図
(c)の場合には溶断部の一部の多結晶シリコン薄膜
領域にアルミニウム薄膜領域を形成する。つづい
て、熱処理によつて該アルミニウム薄膜領域より
アルミニウムを多結晶シリコン薄膜領域中に浸透
させ、シリコンとアルミニウムの混和した薄膜領
域を形成し、溶断部に境界を位置させる。なお、
第２図(a)，(b)の場合には、アルミニウム薄膜領域
のアルミニウムをすべて多結晶シリコン中に浸透
させるか又は一部浸透させた後、残部のアルミニ
ウム薄膜領域をエツチング等によつて除去して、
ヒユーズ装置を形成できる。 The method for manufacturing the fuse device of the present invention shown in FIG. 2(d) has been described above. The thin film region and boundary can also be formed by a manufacturing method similar to that shown in FIG. 2(d). That is, after forming a predetermined electrode and a fusing portion using a polycrystalline silicon thin film region, an aluminum thin film region is formed in contact with a predetermined position of the polycrystalline silicon thin film region. For example, in the case of Figures 2(a) and (b), the polycrystalline silicon thin film area in the center of the fused part, and in the case of Figure 2(b), the polycrystalline silicon thin film area excluding the central part of the fused part. , same figure
In the case of (c), an aluminum thin film region is formed in a part of the polycrystalline silicon thin film region of the fused portion. Subsequently, by heat treatment, aluminum permeates from the aluminum thin film region into the polycrystalline silicon thin film region to form a thin film region in which silicon and aluminum are mixed, and the boundary is located at the fused portion. In addition,
In the case of Figures 2 (a) and (b), after the aluminum in the aluminum thin film region has completely or partially penetrated into the polycrystalline silicon, the remaining aluminum thin film region is removed by etching, etc. do,
A fuse device can be formed.
要するに、本発明の製造方法の主旨は、所望の
断面積と比抵抗をもつ多結晶シリコン薄膜の形成
工程と、この多結晶シリコン薄膜に接触してアル
ミニウム薄膜を形成する工程と、熱処理によつて
シリコンとアルミニウムの混和した薄膜領域を形
成し混和した薄膜領域と残部の多結晶シリコン薄
膜領域との境界を溶断部に設ける工程とを含むこ
とにある。 In short, the gist of the manufacturing method of the present invention is to form a polycrystalline silicon thin film having a desired cross-sectional area and specific resistance, to form an aluminum thin film in contact with this polycrystalline silicon thin film, and to heat treatment. The present invention includes the steps of forming a thin film region in which silicon and aluminum are mixed, and providing a boundary between the mixed thin film region and the remaining polycrystalline silicon thin film region at a fusing portion.
次に本発明のヒユーズ装置の効果について述べ
る。 Next, the effects of the fuse device of the present invention will be described.
本発明の第１の効果は、従来のヒユーズ装置に
比べ低電流で溶断可能なことである。このため、
ヒユーズ装置に溶断電流を供給するトランジスタ
を小形化できる利点がある。例えば、本発明をヒ
ユーズ形読出専用メモリに適用した場合、ヒユー
ズ装置とそのヒユーズ装置の制御用トランジスタ
で構成されたメモリセルを小形化できる。従つ
て、チツプ面積の減少による製造歩留りの向上、
あるいはチツプ当りのメモリ容量の増大によるビ
ツトコストの低下が図れ、ヒユーズ形読出専用メ
モリの小形化・経済化が図れる。 The first effect of the present invention is that it can be blown with a lower current than conventional fuse devices. For this reason,
This has the advantage that the transistor that supplies the blowing current to the fuse device can be made smaller. For example, when the present invention is applied to a fuse-type read-only memory, a memory cell composed of a fuse device and a transistor for controlling the fuse device can be miniaturized. Therefore, improvement in manufacturing yield due to reduction of chip area,
Alternatively, the bit cost can be reduced by increasing the memory capacity per chip, and the fuse type read-only memory can be made smaller and more economical.
本発明の第２の効果は、従来のヒユーズ装置に
比べ溶断電圧を大幅に下げられることである。す
なわち、従来のヒユーズ装置では溶断電圧を決め
る溶断部の長さｌはフオトリソグラフイ技術の最
小加工寸法で制限されていた。しかし、本発明に
よるヒユーズ装置では、製造方法で述べたように
アルミニウムを多結晶シリコン薄膜領域に浸透さ
せて形成するシリコンとアルミニウムの混和した
薄膜領域の長さｘ（第５図ｅ参照）すなわち境界
５の位置は熱処理の温度と時間によつて制御でき
るため、溶断電圧を決める溶断部の長さｌは熱処
理条件によつて加工寸法以下に設定できる。この
ため、本発明のヒユーズ装置の溶断電圧は数Ｖ程
度まで下げられる。これにより、従来のヒユーズ
装置で必要としていた高圧回路は不要となる。従
つて、高圧回路の設計は省略でき、しかも高耐圧
トランジスタ形成の製造プロセスを省略できる利
点がある。 A second effect of the present invention is that the fusing voltage can be significantly lowered compared to conventional fuse devices. That is, in conventional fuse devices, the length l of the fusing portion, which determines the fusing voltage, is limited by the minimum processing size of photolithography technology. However, in the fuse device according to the present invention, as described in the manufacturing method, the length x (see FIG. 5e) of the thin film region in which silicon and aluminum are mixed, which is formed by infiltrating aluminum into the polycrystalline silicon thin film region, is the boundary. Since the position of 5 can be controlled by the temperature and time of the heat treatment, the length l of the fusing part, which determines the fusing voltage, can be set to be less than the processing dimension depending on the heat treatment conditions. Therefore, the blowout voltage of the fuse device of the present invention can be lowered to about several volts. This eliminates the need for the high-voltage circuit required in conventional fuse devices. Therefore, there is an advantage that the design of the high voltage circuit can be omitted and the manufacturing process for forming the high voltage transistor can be omitted.
本発明の第３の効果は、溶断電流が多結晶シリ
コン薄膜の比抵抗に依存せず、一定なことであ
る。従来のヒユーズ装置では溶断電流が比抵抗の
ばらつきの影響を受けるため、比抵抗のばらつき
が大きいと所望の電流で溶断できなくなる場合が
あつた。しかし、本発明のヒユーズ装置では多結
晶シリコン薄膜の比抵抗のばらつきは大幅に許容
されるため、回路設計および製造プロセスにおけ
る多結晶シリコン薄膜の比抵抗制御が容易になる
利点がある。 A third effect of the present invention is that the fusing current does not depend on the specific resistance of the polycrystalline silicon thin film and is constant. In conventional fuse devices, the blowing current is affected by variations in resistivity, so if the variations in resistivity are large, it may not be possible to blow the fuse with a desired current. However, in the fuse device of the present invention, variations in the resistivity of the polycrystalline silicon thin film are allowed to a large extent, so there is an advantage that the resistivity of the polycrystalline silicon thin film can be easily controlled in the circuit design and manufacturing process.
本発明の第４の効果は、従来のヒユーズ装置に
比べ低電力で溶断でき、しかも溶断箇所を局所的
にできることである。従来のヒユーズ装置では溶
断に必要な電力は大きく、溶断部全体がはげしく
溶断し、周辺部への影響が大きいため、溶断部を
絶縁被膜内に埋め込んで溶断することは不可能で
あつた。しかし、本発明のヒユーズ装置は低電力
で局所的に溶断できるため、溶断部を絶縁物被膜
内に埋め込んだ状態で溶断できる。従つて、ヒユ
ーズ装置を保護膜で覆うことができ、ヒユーズ装
置および周辺回路の信頼性を高められる利点があ
る。 A fourth effect of the present invention is that the fuse can be blown with lower power than conventional fuse devices, and the blowout can be done locally. In conventional fuse devices, the power required to blow the fuse is large, the entire blowout section is blown out rapidly, and the surrounding areas are greatly affected, so it has been impossible to embed the blowout section within the insulating coating and blow it out. However, since the fuse device of the present invention can be fused locally with low power, it can be fused with the fused portion embedded within the insulating film. Therefore, the fuse device can be covered with a protective film, which has the advantage of increasing the reliability of the fuse device and peripheral circuits.
このように、本発明のヒユーズ装置は従来のヒ
ユーズ装置に比べ、溶断条件が優れ、ヒユーズ装
置を用いた集積回路の小形化、経済化及び高信頼
化に優れた効果を有している。 As described above, the fuse device of the present invention has better fusing conditions than conventional fuse devices, and has excellent effects in making integrated circuits using the fuse device smaller, more economical, and more reliable.
第１図は本発明のヒユーズ装置の基本構成を示
す斜視図、第２図ａ，ｂ，ｃ，ｄ，ｅは本発明の
実施例を示す斜視図、第３図は本発明のヒユーズ
装置の溶断状態を示す斜視図、第４図は第２図ｃ
の実施例の電流−電圧特性の実測例を示す特性
図、第５図ａ，ｂ，ｃ，ｄ，ｅ，ｆは第２図ｄの
実施例の製造工程を示す縦断面図である。
１，１′……多結晶シリコン薄膜領域で形成さ
れた電極、２，２′……シリコンとアルミニウム
の混和した薄膜領域で形成された電極、３，３′
……多結晶シリコン薄膜領域で形成された溶断
部、４，４′……シリコンとアルミニウムの混和
した薄膜領域で形成された溶断部、５，５′……
シリコンとアルミニウムの混和した薄膜領域と多
結晶シリコン薄膜領域の境界、６，７……リード
線、８……アルミニウム薄膜領域、９，１０，１
１，１２……本発明のヒユーズ装置の電流対電圧
特性例、１３……従来のヒユーズ装置の電流対電
圧特性例、１４……絶縁基板、１５……多結晶シ
リコン薄膜、１６……アルミニウム薄膜、１７…
…多結晶シリコン薄膜とアルミニウム薄膜の接触
部、１８……絶縁膜、１９……スルーホール。
FIG. 1 is a perspective view showing the basic structure of the fuse device of the present invention, FIGS. 2 a, b, c, d, and e are perspective views showing embodiments of the present invention, and FIG. A perspective view showing the fused state, Figure 4 is Figure 2c
FIGS. 5a, b, c, d, e, and f are longitudinal sectional views showing the manufacturing process of the embodiment of FIG. 2d. 1, 1'... Electrode formed of a polycrystalline silicon thin film region, 2, 2'... Electrode formed of a thin film region of a mixture of silicon and aluminum, 3, 3'
... Fused part formed of a polycrystalline silicon thin film region, 4, 4'... Fused part formed of a thin film region of a mixture of silicon and aluminum, 5, 5'...
Boundary between silicon and aluminum mixed thin film region and polycrystalline silicon thin film region, 6, 7... Lead wire, 8... Aluminum thin film region, 9, 10, 1
1, 12...Example of current versus voltage characteristics of the fuse device of the present invention, 13...Example of current versus voltage characteristics of a conventional fuse device, 14...Insulating substrate, 15...Polycrystalline silicon thin film, 16...Aluminum thin film , 17...
...Contact portion between polycrystalline silicon thin film and aluminum thin film, 18...Insulating film, 19...Through hole.
Claims (1)
ミニウムとの混和した膜領域とを備え、前記２つ
の領域の境界が溶断部に設けられたことを特徴と
するヒユーズ装置。 ２ 多結晶シリコン薄膜を形成する工程と、該多
結晶シリコン薄膜の一部に接触してアルミニウム
薄膜を形成する工程と、前記アルミニウム薄膜か
らアルミニウムを前記多結晶シリコン薄膜内に浸
透させシリコンとアルミニウムとの混和した薄膜
領域を形成し該混和した薄膜領域と残部の多結晶
シリコン薄膜領域との境界を溶断部に設ける工程
とを含むことを特徴とするヒユーズ装置の製造方
法。Claims: 1. A fuse device comprising a polycrystalline silicon thin film region and a mixed silicon and aluminum film region, the boundary between the two regions being provided at a fusing part. 2. A step of forming a polycrystalline silicon thin film, a step of forming an aluminum thin film in contact with a part of the polycrystalline silicon thin film, and a step of infiltrating aluminum from the aluminum thin film into the polycrystalline silicon thin film to combine silicon and aluminum. 1. A method for manufacturing a fuse device comprising the steps of: forming a thin film region in which the mixed thin film region and the remaining polycrystalline silicon thin film region are mixed, and providing a boundary between the mixed thin film region and the remaining polycrystalline silicon thin film region at a fusion section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56157430A JPS5859528A (en) | 1981-10-05 | 1981-10-05 | Fuse unit and method of producing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56157430A JPS5859528A (en) | 1981-10-05 | 1981-10-05 | Fuse unit and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5859528A JPS5859528A (en) | 1983-04-08 |
| JPH0247863B2 true JPH0247863B2 (en) | 1990-10-23 |
Family
ID=15649462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56157430A Granted JPS5859528A (en) | 1981-10-05 | 1981-10-05 | Fuse unit and method of producing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5859528A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5269537A (en) * | 1975-12-08 | 1977-06-09 | Fujitsu Ltd | Semiconductor memory |
| JPS5272541A (en) * | 1975-12-15 | 1977-06-17 | Fujitsu Ltd | Semi-conductor memory |
| JPS57143857A (en) * | 1981-03-03 | 1982-09-06 | Seiko Instr & Electronics Ltd | Two terminal polysilicon programmable read-only memory |
-
1981
- 1981-10-05 JP JP56157430A patent/JPS5859528A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5269537A (en) * | 1975-12-08 | 1977-06-09 | Fujitsu Ltd | Semiconductor memory |
| JPS5272541A (en) * | 1975-12-15 | 1977-06-17 | Fujitsu Ltd | Semi-conductor memory |
| JPS57143857A (en) * | 1981-03-03 | 1982-09-06 | Seiko Instr & Electronics Ltd | Two terminal polysilicon programmable read-only memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5859528A (en) | 1983-04-08 |
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