JPH0246749A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH0246749A JPH0246749A JP19770988A JP19770988A JPH0246749A JP H0246749 A JPH0246749 A JP H0246749A JP 19770988 A JP19770988 A JP 19770988A JP 19770988 A JP19770988 A JP 19770988A JP H0246749 A JPH0246749 A JP H0246749A
- Authority
- JP
- Japan
- Prior art keywords
- package
- metal lid
- spot welding
- solder frame
- positions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 238000003466 welding Methods 0.000 claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 230000004927 fusion Effects 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000007789 sealing Methods 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 5
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005493 welding type Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置用パッケージに係り、特に金属蓋とソルダー
枠とを一体化した構造に関し、封止ボイドの発生を防止
可能な半導体用パ・ノケージの提供を目的とし、
半導体素子を搭載したパンケージと、表面周縁部にソル
ダー枠がスポット溶接にて接合された金属蓋を有し、前
記ソルダー枠を介して前記パッケージと前記金属蓋とを
融着することによって前記半導体素子を気密封止する半
導体装置用パッケージにおいて、前記パッケージと前記
金属蓋との融着面を除く複数の位置に前記スポット溶接
の領域を設けて構成する。[Detailed Description of the Invention] [Summary] The object of the present invention is to provide a package for semiconductor devices that can prevent the occurrence of sealing voids, particularly in the case of a structure in which a metal lid and a solder frame are integrated. and a pan cage in which a semiconductor element is mounted, and a metal lid having a solder frame joined to the peripheral edge of the surface by spot welding, and the package and the metal lid are fused together via the solder frame. In a package for a semiconductor device that hermetically seals a semiconductor element, the spot welding areas are provided at a plurality of positions excluding a fused surface between the package and the metal lid.
本発明は半導体装置用パッケージに係り、特に金属蓋と
ソルダー枠とを一体化した構造に関する。The present invention relates to a package for a semiconductor device, and particularly to a structure in which a metal lid and a solder frame are integrated.
第３図は従来のパッケージに金属蓋を融着する直前の断
面図であって、第３図（ａ）は金属蓋、ソルダー枠、パ
ッケージの３点構成図、第３図（ｂ）はソルダー枠付金
属蓋、パッケージの２点構成図を示す。両図において、
１は金属蓋、２はソルダー枠。Figure 3 is a cross-sectional view just before a metal lid is fused to a conventional package. Figure 3 (a) is a three-piece configuration diagram of the metal lid, solder frame, and package, and Figure 3 (b) is a diagram of the solder. A two-piece configuration diagram of the metal lid with frame and the package is shown. In both figures,
1 is a metal lid, 2 is a solder frame.
３はパッケージ、４は封止すべき半導体素子をそれぞれ
示す。ソルダー枠２は金と錫の共晶合金、あるいは鉛、
錫の合金等からなり、金属蓋１の融着面にはあらかじめ
金メツキ等が施されており、ソルダー枠２を挟んで金属
Ｍ１の上から押圧加熱することにより融着封止を行うも
のである。融着封止の作業性を向上させるため、第３図
（ｂ）に示すようにソルダー枠２と金属蓋１とをあらか
じめスポット溶接にて一体化した方法が用いられている
。3 indicates a package, and 4 indicates a semiconductor element to be sealed. The solder frame 2 is made of a eutectic alloy of gold and tin, or lead,
It is made of a tin alloy, etc., and the fusion surface of the metal lid 1 is pre-plated with gold plating, etc., and fusion sealing is performed by pressing and heating from above the metal M1 with the solder frame 2 in between. be. In order to improve the workability of fusion sealing, a method is used in which the solder frame 2 and the metal lid 1 are previously integrated by spot welding, as shown in FIG. 3(b).
第４図は従来のソルダー枠のスポット溶接位置を示す図
であって、第４図ｉａ）は四隅スポット溶接位置の平面
図と断面図、第４図（ｂ）は菱形スポット溶接位置の平
面図を示している。両図において、５は複数のスポット
溶接位置を示す。スポット溶接の位置および数はこの例
以外にも幾多の種類が存在している。Fig. 4 is a diagram showing the spot welding positions of a conventional solder frame, in which Fig. 4 ia) is a plan view and a sectional view of the four corner spot welding positions, and Fig. 4(b) is a plan view of the rhombus spot welding position. It shows. In both figures, 5 indicates a plurality of spot welding positions. There are many other types of spot welding positions and numbers other than this example.
従来のソルダー枠２と金属蓋１とのスポット溶接による
一体化手段によれば、そのスポット溶接位置４の周辺部
分には封止ボイドが発生し易く、パッケージ３に封止を
行う場合に融着強度の劣化を招く欠点がある。According to the conventional method of integrating the solder frame 2 and the metal lid 1 by spot welding, sealing voids are likely to occur in the area around the spot welding position 4, and when sealing the package 3, fusion bonding may occur. It has the disadvantage of causing deterioration in strength.
本発明は上記従来の欠点に鑑みてなされたもので、封止
ボイドの発生を防止可能な半導体用パンケージの提供を
目的とする。The present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a semiconductor package that can prevent the occurrence of sealing voids.
第１図は、本発明の構成を示す平面図および要部断面図
である。半導体素子４を搭載したパッケージ３と、表面
周縁部にソルダー枠２がスポット溶接にて接合された金
属蓋ｌを有し、前記ソルダー枠２を介して前記パッケー
ジ３と前記金属蓋１とを融着することによって前記半導
体素子４を気密封止する半導体装置用パッケージにおい
て、前記パッケージ３と前記金属Ｍ１との融着面を除く
複数の位置６に前記スポット溶接の領域７を設けて構成
する。FIG. 1 is a plan view and a sectional view of essential parts showing the configuration of the present invention. It has a package 3 on which a semiconductor element 4 is mounted, and a metal lid l having a solder frame 2 joined to the peripheral edge of the surface by spot welding, and the package 3 and the metal lid 1 are fused through the solder frame 2. In a package for a semiconductor device that hermetically seals the semiconductor element 4 by attaching the package 3 to the metal M1, the spot welding areas 7 are provided at a plurality of positions 6 excluding the fused surface between the package 3 and the metal M1.
パッケージ３と前記金属蓋１との融着面を除く複数の位
置６に前記スポット溶接の領域７を設けることにより、
パッケージ３にソルダー枠２を介して金属蓋ｌを融着す
る際にスポット溶接領域７にて発生する封止ボイドの影
響を受けなくなり、パフケージ３と前記金属蓋１との融
着面に封止ボイドの発生を防止することができる。By providing the spot welding areas 7 at a plurality of positions 6 excluding the fusion surface between the package 3 and the metal lid 1,
When the metal lid l is fused to the package 3 via the solder frame 2, it is no longer affected by sealing voids that occur in the spot welding area 7, and the sealing is performed on the fused surface of the puff cage 3 and the metal lid 1. Generation of voids can be prevented.
る形に金属蓋１とソルダー枠２を形成し、その領域７の
範囲内（例えばスポット溶接位置６に示すような複数の
位置）にてスポット溶接を行うことにより、金属蓋１と
ソルダー枠２とを一体化しておけば、パッケージ３と融
着封止を行う際に封止ボイドの発生を防止することがで
きる。By forming the metal lid 1 and the solder frame 2 in the shape of the metal lid 1 and the solder frame 2, and performing spot welding within the area 7 (for example, at multiple positions as shown in the spot welding positions 6), the metal lid 1 and the solder frame 2 are If these are integrated, it is possible to prevent sealing voids from occurring when sealing with the package 3 by fusion bonding.
なお、領域７の位置および数はこの例に限定されるもの
でないことは言うまでもない。It goes without saying that the position and number of regions 7 are not limited to this example.
以下本発明の実施例を図面によって詳述する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
なお、構成、動作の説明を理解し易くするために全図を
通じて同一部分には同一符号を付してその重複説明を省
略する。Note that, in order to make the explanation of the configuration and operation easier to understand, the same parts are given the same reference numerals throughout all the figures, and repeated explanation thereof will be omitted.
第１図は本発明の構成を示す平面図および要部断面図、
第２図は本発明の構成を示す他の実施例の平面図である
。両図においてスポット溶接の領域７はパッケージ３と
前記金属蓋１との融着面を除く複数の位置６に突出させ
て設けている。すなわち、あらかじめ第１図あるいは第
２図に図示す〔発明の効果〕
以上の説明から明らかなように本発明によれば、スポッ
ト溶接型のソルダー枠一体化金属蓋における封止ボイド
の発生を防止することができる効果がある。FIG. 1 is a plan view and a sectional view of essential parts showing the configuration of the present invention,
FIG. 2 is a plan view of another embodiment showing the structure of the present invention. In both figures, spot welding areas 7 are provided to protrude at a plurality of positions 6 excluding the fused surface between the package 3 and the metal lid 1. That is, as shown in FIG. 1 or 2 in advance [Effects of the Invention] As is clear from the above explanation, according to the present invention, the occurrence of sealing voids in a spot welding type solder frame integrated metal lid can be prevented. There is an effect that can be done.
第１図は本発明の構成を示す平面図および要部断面図、
第２図は本発明の構成を示す他の実施例の平面図、
第３図はは従来のパッケージに金属蓋を融着する直前の
断面図、
第４図は従来のソルダー枠のスポ・ノド溶接位置を示す
図である。
第１図↓こおいて、１は金属蓋、２はソルダー枠、３は
パッケージ、６はスポット溶接位置、７は領域をそれぞ
れ示す。
Ｎ＼Fig. 1 is a plan view and a sectional view of main parts showing the structure of the present invention, Fig. 2 is a plan view of another embodiment showing the structure of the present invention, and Fig. 3 is a metal lid fused to a conventional package. FIG. 4 is a cross-sectional view just before welding, and is a diagram showing the spot and throat welding positions of the conventional solder frame. In Figure 1, 1 is the metal lid, 2 is the solder frame, 3 is the package, 6 is the spot welding position, and 7 is the area. N\
Claims (1)
周縁部にソルダー枠（２）がスポット溶接にて接合され
た金属蓋（１）を有し、前記ソルダー枠（２）を介して
前記パッケージ（３）と前記金属蓋（１）とを融着する
ことによって前記半導体素子（４）を気密封止する半導
体装置用パッケージにおいて、 前記パッケージ（３）と前記金属蓋（１）との融着面を
除く複数の位置（６）に前記スポット溶接の領域（７）
を設けたことを特徴とする半導体装置用パッケージ。[Scope of Claims] It has a package (3) in which a semiconductor element (4) is mounted, and a metal lid (1) having a solder frame (2) joined to the peripheral edge of the surface by spot welding. 2), in which the semiconductor element (4) is hermetically sealed by fusing the package (3) and the metal lid (1) via the package (3) and the metal lid; The spot welding area (7) at multiple positions (6) excluding the fusion surface with (1)
A package for a semiconductor device characterized by being provided with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19770988A JP2653405B2 (en) | 1988-08-08 | 1988-08-08 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19770988A JP2653405B2 (en) | 1988-08-08 | 1988-08-08 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0246749A true JPH0246749A (en) | 1990-02-16 |
| JP2653405B2 JP2653405B2 (en) | 1997-09-17 |
Family
ID=16379055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19770988A Expired - Lifetime JP2653405B2 (en) | 1988-08-08 | 1988-08-08 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2653405B2 (en) |
-
1988
- 1988-08-08 JP JP19770988A patent/JP2653405B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2653405B2 (en) | 1997-09-17 |
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