JPH0245974A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease a resistance value of a word line and to achieve a rapid operation of a storage device by forming, on the word line, a second-layer wiring which has almost the same flat pattern as the word line and by short- circuiting the word line at a regular interval by the second-layer wiring. CONSTITUTION:A first wiring layer 2 made of polysilicon, polycide or silicide is used as a word line. On the word line 2, a wiring layer 4 of a second wiring layer made of polysilicon, polycide or silicide and decreasing a resistance value of a word line is formed. The word line 2 is short-circuited at a regular interval by the second-layer interconnection 4. The second wiring layer 4 has almost the same flat pattern as the word line 2. By bringing the second-layer wiring 4 into contact with the word line 2 at every 16 bits, a resistance value of the word line 2 can be approximately halved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the resistance value of a word line is reduced.

[Prior Art] A conventional semiconductor memory device will be described with reference to FIG. 2, taking a static RAM as an example. In FIG. 2, a source/drain diffusion layer is formed in the substrate of a semiconductor substrate 1, and a polycide layer (1) which is a first layer interconnection is formed on the semiconductor substrate 1 via a gate oxide film or a field oxide film.
2, 3) are formed. Here, 2 is a word line that also serves as the gate of the transfer transistor, and 3 is a wiring layer that also serves as the gate electrode of the driver transistor. On top of this, a ground wiring layer 6, which is a second layer wiring, is formed of polycide via a first interlayer insulation film 5, and furthermore, on the second interlayer insulation film 7 and in its through hole. A high resistance polysilicon layer 8 serving as a load resistance of the driver transistor is formed, and a nitride film 9 is formed thereon. Then, the third interlayer insulating film 1
An A1 wiring 11 serving as a digit line is formed above 0 and in the through hole thereof.

[Problems to be Solved by the Invention In recent years, high speed performance of semiconductor memory devices has been increasingly sought after. However, on the other hand, higher integration and miniaturization have been promoted, and as a result, the width of the word line has become narrower and the number of elements connected to the word line has increased. Therefore, the resistance of the word line increases and the capacitance of this line increases, impairing high-speed operation. In order to lower the resistance of this line, polycide or silicide has been used instead of polysilicon, but even with this, a sufficiently low resistance value has not been obtained. Furthermore, if a reduction in resistance is attempted by increasing the thickness of the wiring, not only will there be problems in terms of film formation technology, but step coverage will deteriorate.

The present invention has been made to address this problem, and its purpose is to reduce the resistance value of the word line without adding any new process, thereby improving the operation of the semiconductor memory device. The goal is to achieve high speed.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a first layer wiring made of polysilicon, polycide, or silicide, and a second layer wiring made of polysilicon, polycide, or silicide. The first layer wiring is used as a word line, and a second layer wiring having substantially the same planar shape is formed on the word line, and the word line is short-circuited by the second layer wiring at regular intervals.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a static memory cell, in which a word line 2 made of polycide as a first wiring layer and a gate of a driver transistor are formed on a semiconductor substrate 1 via a gate insulating layer or a field oxide film. A wiring layer 3 that also serves as an electrode is formed. On the first layer wiring, a word line low resistance wiring layer 4 made of silicide and a ground wiring layer 6 are formed as second layer wiring with a first interlayer insulating film 5 interposed therebetween. Both the word line 2 and the word line low resistance wiring layer 4 extend perpendicularly to the plane of the paper, and
Both are electrically connected every 16 bits.

The semiconductor memory device of this example is manufactured as follows.

That is, an oxide film is formed on a P-type semiconductor silicon substrate in which a P-well is formed in an N-type semiconductor substrate, and word lines 2 and wiring layers 3 are formed thereon using tungsten polycide. After growing a 1,000-layer vapor-phase oxide film as a first interlayer insulating film 5 on the first polycide layer, a second tungsten polycide layer is formed on the entire surface. The second tungsten polycide layer is patterned as a ground wiring layer 6 and a word line low resistance wiring layer 4. The word line low resistance wiring layer 4 has almost the same planar pattern as the word line 2 which is the first layer wiring, and by making contact with the word line 2 every 16 bits, the word line The resistance value can be approximately halved. Thereafter, a second interlayer insulating film 7 is grown to a thickness of about 1 μm, a through hole is formed to the cell node, and a high resistance polysilicon layer 8 is formed as a load resistance of the driver transistor. Furthermore, after selectively forming a nitride film 9 thereon and forming a third interlayer insulating film 1o on the entire surface,
A through hole for a digit line is formed, and finally an AI wiring 11 is formed as a digit line. In this example,
The word line low-resistance wiring layer 4 and the word line 2 made of first layer polycide were connected every 16 bits, but of course, electrical connection is made for every 16 bits or less, for example every 8 bits or every bit. may be connected to. Also,
A polysilicon layer or a silicide layer may be used instead of the first or second polycide layer.

[Effects of the Invention] As explained above, the present invention has the following advantages:
Since the word lines, which are the first layer wiring, are short-circuited at appropriate intervals, the present invention can reduce the resistance of the word lines (i.e., increase the speed of semiconductor memory devices) without increasing the number of steps. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 1... Semiconductor substrate, 2... Word line, 3...
Ground wiring, 4... Word line low resistance wiring layer.

Claims (1)

[Claims] a semiconductor substrate in which a plurality of diffusion layers are formed; a first layer wiring made of polysilicon, polycide, or silicide formed on the semiconductor substrate with an insulating film interposed therebetween;
A semiconductor memory device comprising an interlayer insulating film formed on the first layer wiring and a second layer wiring made of polysilicon, polycide, or silicide formed on the interlayer insulating film. A plurality of word lines are formed by the first layer wiring, a word line low resistance wiring layer consisting of the second layer wiring is formed on the plurality of word lines via the interlayer insulating film, and A semiconductor memory device characterized in that each of the plurality of word lines is connected to the word line low resistance wiring layer formed thereon at a plurality of locations.