JP2796724B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and for example, to a dynamic RAM (Random Access Memory).

B. 2. Description of the Related Art A structure of a so-called folded bit line type memory cell generally used in a dynamic RAM, for example, will be described with reference to FIG. 16, and its problems will be described with reference to a plan view of FIG.

As shown in FIG. 16, predetermined N ⁺ -type source regions 8 and N ⁺ -type drain regions 12 are formed on the surface of the P-type silicon substrate 1, with a gate oxide film 5 interposed therebetween. Gate electrodes (word lines) 7b and 7c are provided, respectively, and two N-channel MOS transistors (transfer gates) are respectively formed using the drain region 12 in common. A field plate (polysilicon layer) 4 is provided on the P-type silicon substrate 1 with an oxide film 3 interposed therebetween.
The field plate 4 is provided in each of the source regions 8 described above.
And a capacitor composed of the oxide film 3 are connected to each other.
Note that word lines 7a and 7d are provided on each field plate 4 via an oxide film 6.

Further, an interlayer insulating layer 9 is further deposited on the surface, and a contact hole 10 is provided in the drain region 12,
For example, an Al wiring (bit line) 11 is formed. In addition,
In the figure, 2 is a field oxide film, and 13 is an element region. In FIG. 17, 7e, 7f, 7g, and 7h are word lines, respectively.
l is the distance between the contact hole 10 and the end of the element region 13, m is the distance between the contact hole 10 and the respective gate electrode (word line) (for example, the distance between the contact hole 10 and the gate electrode 7c). ).

The manufacturing process of the above-described device can be briefly described by using a well-known LOCOS (Local Oxidation of Silicon).
After the element region 13 is separated by a method or the like, the respective gate electrodes are formed, the source region 8 and the drain region 12 are formed by ion implantation or the like, and the interlayer insulating layer 9 is further formed thereon. A method of forming a contact hole 10 in 12 and depositing an Al wiring layer 11 or the like has been performed.

 Hereinafter, problems of the above-described device will be described.

(1). That is, an electrical short (for example, the gate electrode 7 shown in FIG. 16) due to misalignment of the mask or the like.
And short-circuit with the Al wiring layer 11). For this reason, as shown in FIG. 17, it is absolutely necessary to provide a sufficient space (l and m) around the contact hole 10 in consideration of a shift in mask alignment or the like when forming the contact hole 10 in advance. Become. Therefore, in addition to the area of the region where the contact hole 10 is to be formed, an extra area due to the above-described interval is required.
There are also very severe restrictions on the layout of wiring patterns and the like. As a result, miniaturization of the device becomes very difficult, which is disadvantageous for high integration.

(2). Also, when trying to increase the degree of integration of the device,
Inevitably, the area occupied by the contact hole 10 must be reduced. But contact holes
When the area of 10 is reduced, in the device described above, step coverage in the contact hole 10 of Al or the like forming the bit line 11 (Step Coverage: step coverage)
And so on, which leads to a decrease in the reliability of the device (for example, the resistance of the bit line 11 becomes large, and in severe cases, the device may be disconnected).

(3). Further, the extra interval l described in (1)
And m result in an increase in the area of the element region 13 itself, unnecessarily increasing the power consumption required for the operation of the element, and increasing unnecessary parasitic capacitance and the like (for example, between layers) in the device. Will be invited.

In addition, the above-described problems can be similarly considered for an element such as a single MOS transistor.

Japanese Patent Application Laid-Open No. 62-287667 discloses a technique in which an insulating film (interlayer insulating layer) on a gate electrode is removed and a contact of a wiring layer is formed in a self-aligned manner. There is a risk that the insulation separation above will be insufficient,
In order to prevent this, an additional step of covering the upper surface with a nitride film is required, and it is necessary to form a contact hole with the upper wiring through the nitride film.

C. An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device which can be highly integrated, has low power consumption, and has small parasitic capacitance.

D. Configuration of the Invention That is, the present invention provides a method of manufacturing the semiconductor device, comprising: forming an insulating film on one main surface of a semiconductor substrate;
A step of forming a first conductive layer (for example, gate electrodes 7, 7a, 7b, 7c, 7d described later) on the insulating film, and a step of forming the first conductive layer (for example, gate electrodes 7, 7a, 7b, 7c, described later); 7d) forming an interlayer insulating layer thereon, patterning the first conductive layer (for example, gate electrodes 7, 7a, 7b, 7c, 7d described later) and the interlayer insulating layer into the same pattern, One conductive layer (for example, gate electrodes 7, 7a, 7b, 7c, 7
d) selectively forming an insulating coating film over the side surface of d) and the side surface of the interlayer insulating layer; and forming the insulating coating film below a contact hole present on the one main surface without the insulating coating film. The present invention also provides a method for manufacturing a semiconductor device, comprising: a step of forming a diffusion layer using a cover film as a mask; and a step of applying a second conductive layer (for example, polysilicon layers 11 and 15 described later) to the contact holes. is there.

E. Examples Hereinafter, examples of the present invention will be described.

1 to 4 show an example in which the present invention is applied to, for example, a single MOS transistor.

In the device according to this embodiment, as shown in FIG. 1, an N ⁺ -type source region 8 and a drain region 12 are formed by diffusion on one principal surface side of a P-type silicon substrate 1, and between the source region 8 and the drain region 12. Is provided with a gate electrode 7 via a gate oxide film 5 to form an N-channel MOS transistor. Then, on the gate electrode 7, the gate electrode 7
(The total thickness of the gate electrode 7 and the interlayer insulating layer 9 is, for example, 1.5 μm).
It is about. Further, a nitride film 14 is selectively formed by sidewall technology over the side surface of the gate electrode 7 and the side surface of the interlayer insulating layer 9.

A contact hole 10 is provided on each of the source region 8 and the drain region 12, and a polysilicon layer 15 is deposited in the contact hole 10. Further, a wiring is provided on the polysilicon layer. Layer (eg Al)
16 are formed. FIG. 2 is a plan view of FIG.

As described above, the device according to the present embodiment includes:
A gate electrode 7 having a predetermined pattern formed on one main surface of a P-type silicon substrate 1 via a gate oxide film 5, an interlayer insulating layer 9 formed on the gate electrode 7, and side surfaces of the gate electrode 7 And a nitride film 14 which is selectively formed over the side surface of the interlayer insulating layer 9 (this nitride film has a very high insulating property even if it is thin). There is no need to worry about an electrical short between the polysilicon layer 15 connected to the source region 8 and the drain region 12 formed below the contact hole. Moreover, the contact hole 10 is formed in the gate electrode 7.
(The details of the manufacturing process will be described later.) Therefore, the insulating layer 9 on the side surface of the gate electrode 7 due to a mask alignment shift or the like at the time of forming the contact hole 10 as in the related art.
(See FIG. 16) (the insulating layer 9 may be thin, or if it is severe, may not be deposited at all)
A short circuit occurs between the gate electrode 7 and the polysilicon layer 15. No need to worry).

Therefore, as shown in FIG.
Since it is not necessary to consider an extra area due to, for example, the device can be miniaturized, which is very advantageous for high integration.
Furthermore, according to the device of the present example, the area occupied by the contact hole 10 itself is not reduced unnecessarily,
Step coverage or the like in the contact hole 10 (in this example, step coverage of the polysilicon layer 15)
And the degree of integration can be easily improved while ensuring sufficient performance.

Further, as described above, since no extra area is required around the contact hole 10, the area of the element region 13 can be reduced to a desired size. Therefore, the power consumption required for the operation of the element (N-channel MOS transistor in this example) can be reduced, and unnecessary parasitic capacitance in the element can be reduced (interlayer insulating layer 9).
Is sufficiently thick, so that the parasitic capacitance becomes smaller. ). The gate electrode 7 can also be sufficiently separated from the upper part by the thick insulating layer 9 thereon.

Next, the method of manufacturing the device of FIG. 1 will be described with reference to FIGS.
The figure will be described. FIG. 3 is a plan view corresponding to each of FIG.

First, as shown in FIGS. 3A and 4A, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by a known LO method.
Selective growth by COS (Local Oxidation of Silicon) method (grows 8000mm thick at 900 ° C)
Thus, an element region 13 is formed. Thereafter, a gate oxide film 5 having a thickness of 200 ° is formed by thermal oxidation at a temperature of 900 ° C.

Then, as shown in FIG. 3B and FIG.
After a polysilicon layer 7 is deposited on the front surface by a CVD (Chemical Vapor Deposition) method to a thickness of 5000 .ANG., Phosphorus is doped and annealing is performed to reduce the resistance of the polysilicon layer 7. Then, after a mask (for example, a photoresist) process, the polysilicon layer 7 is patterned into a predetermined pattern by dry etching as shown in FIGS. 3C and 4C.

Next, for example, after forming a source region and a drain region in other peripheral circuits, as shown in FIGS. 3D and 4D, an interlayer insulating layer (for example, a BPS
G (Borophosphosilicate Glass) 9) 0.5 ~
After depositing to a thickness of 1.5 μm, for example 1 μm,
The interlayer insulating layer 9 is planarized by a predetermined heat treatment at 50 to 950 ° C. Then, after a predetermined region is covered with a mask (for example, a photoresist), as shown in FIGS. 3E and 4E, the interlayer insulating layer 9 and the gate electrode (poly) are respectively etched by a predetermined etching (by sequentially changing the etchant). The silicon layer 7 and the gate oxide film 5 are formed in a predetermined same pattern. Thereby, the contact hole 10 is also formed at the same time.

Next, as shown in FIGS. 3F and 4F, a nitride film 14 is deposited on the entire surface including the contact holes 10 by a CVD method. Thereafter, as shown in FIG. 3G and FIG.
As shown in FIG. 5G, the nitride film 14 is left as a sidewall only on the side surface of each layer in the contact hole 10.

Next, as shown in FIG. 3H and FIG. 4H, an N-type doped (for example, phosphorus-rich) polysilicon layer 15 is deposited on the entire surface including the contact hole 10 by a CVD method, and thereafter, Annealing at a temperature of 800 to 900 ° C. lowers the resistance of the polysilicon layer 15 and simultaneously diffuses N-type impurities such as phosphorus into the P-type silicon substrate 1 to form the source region 8 and the drain region 12. I do.

Next, as shown in FIGS. 3I and 4I, the polysilicon layer 15 is left only in the contact hole 10 by etch back. Thereafter, by performing a predetermined wiring process or the like, for example, Al is deposited to complete the device of FIG.

As is clear from the manufacturing process described above,
FIG. 3F, FIG.
As shown in FIG. 4F, FIG. 3G, and FIG.
After the formation of the contact hole 10 at the same time as the formation of the nitride film 14, the nitride film 14 is selectively formed (a thin and very insulating material is formed over the side surface of the gate electrode 7 and the side surface of the interlayer insulating layer 9). Since the nitride film 14 is formed), there is no need to worry about electrical short-circuiting due to misalignment of the mask and the like, and the area of the contact portion can be made as small as possible. Therefore, with the advantages described above, high integration is possible without requiring any new technology.
Moreover, a highly reliable device can be easily manufactured.

5 to 9 show another embodiment of the present invention, in which the present invention is applied to a memory cell of the above-mentioned folded bit line type dynamic RAM.

As shown in FIG. 5, the basic structure is the same as the example shown in FIG. 1 described above with reference to the example shown in FIG. That is, P
On the silicon substrate 1, gate electrodes (word lines) 7b and 7c are respectively provided between the two source regions 8 through the respective gate oxide films 5 using the drain region 12 in common. A channel MOS transistor (transfer gate) is configured. A capacitor comprising a field plate 4 and an oxide film 3 is connected to each source region 8, and word lines 7a and 7d are formed on the field plate 4 via a gate oxide film 5, respectively. I have. The above-described word lines (gate electrodes) 7a, 7b, 7c, 7d and other insulating structures are the same as those in FIG. 1, and the respective source regions 8 and drain regions 12 Contact hole 10 above
Polysilicon layers 15 are respectively formed therein similarly to the above-described example.

That is, as described above, this example also has the nitride film 14 selectively formed over the side surface of the gate electrode (for example, the gate electrode 7b) and the side surface of the interlayer insulating layer 9, so that There are similar advantages as in the example. That is, a layout pattern having a high integration density as shown in FIG. 6 is not required without an extra area due to the intervals l and m in consideration of an electrical short due to a mask alignment shift or the like as shown in FIG. realizable. Further, as in the above-described example, the degree of integration can be easily increased while ensuring sufficient step coverage of the polysilicon 15 and the like in the contact hole 10. In addition, since the area of the element region 13 itself can be reduced, power consumption and unnecessary parasitic capacitance can be reduced, and device reliability can be improved.

Next, a method of manufacturing the device of FIG. 6 will be described with reference to FIGS. 7 to 9. FIG. 7 is a plan view, FIG. 8 is a sectional view taken along line VIII-VIII of FIG. 7, and FIG. 9 is a sectional view of FIG.
It is a IX-IX line sectional view. 7 and 9 are omitted because they can be similarly represented in FIGS. 7I and 9I.

First, as shown in FIGS. 7A, 8A and 9A, after going through the same steps as in FIG. 4A described above, FIGS. 7B, 8B and 9B
As shown in the figure, polysilicon 4 is deposited on the entire surface by a CVD method, and further, FIGS. 7C, 8C, 9C, and 7D,
As shown in FIGS. 8D and 9D, the polysilicon layer 4 and the oxide film 3 are sequentially subjected to a predetermined patterning so that the polysilicon layer (field plate) 4 is left only in a predetermined region.

Next, as shown in FIGS. 7E, 8E and 9E, an oxide film (gate oxide film) 5 is formed on the entire surface by thermal oxidation, and further, as shown in FIGS. 7F, 8F and 9F. As shown,
After a polysilicon layer 7 is formed on the entire surface by a predetermined CVD method, a predetermined region is covered with a mask (for example, a photoresist) 40.

Next, as shown in FIGS. 7G, 8G, and 9G, the polysilicon layer 7 and the oxide film 5 in a predetermined region are respectively patterned by performing predetermined etching (however,
Here, as shown in FIG. 7G, each word line 7
a, 7b, 7c and 7d are connected in an H-shape. ).

Next, as shown in FIGS. 7H, 8H and 9H, after an interlayer insulating layer 9 is deposited on the entire surface by a predetermined CVD method,
A predetermined area is covered with a mask (for example, a photoresist) 41.

Next, as shown in FIGS. 7I, 8I, and 9I, predetermined etching is sequentially performed to form the interlayer insulating layer 9, the polysilicon layer 7, and the oxide film 5 in a predetermined region in the same pattern. That is, the gate electrode (word line) 7a,
7b, 7c and 7d are respectively formed (the word lines 7a and 7d are respectively formed on the field plate 4).
At this time, contact holes 10 are simultaneously formed between the respective word lines.

Next, as shown in FIG. 8J, an oxide film 6 is formed on the entire surface including the contact hole 10 by thermal oxidation. Thereafter, as shown in FIG. 8K, the oxide film 6 is selectively removed by performing predetermined etching to expose the P-type silicon substrate 1 in each contact hole 10.
Since the oxide film 6 on the surface of the polysilicon 4 or 7 is thicker than that of the contact hole 10, it remains after the above etching.

Then, as shown in FIG. 8L, through the same steps as in FIG. 4F, as shown in FIG.
A nitride film 14 is selectively formed on each of the side surfaces of a, 7b, 7c, and 7d and on each of the side surfaces of each of the interlayer insulating layers 9 formed in the same pattern on their gate electrodes.

Next, as shown in FIG. 8N, the source region 8 and the drain region
Then, polysilicon layers 15 are respectively formed in the respective contact holes through the same steps as those of FIG. 4I described above.

As is clear from the manufacturing process described above, in the device according to the present example and the method of manufacturing the same, after forming the respective contact holes 10 as shown in FIGS. Since the nitride film 14 is selectively formed, it has the advantages described above, and does not require any new technology as in the example of FIG. 1 and can easily be highly integrated. And a device having very high reliability can be easily manufactured.

FIGS. 10 to 14 show another embodiment of the present invention, in which the present invention is applied to the same memory cell as the conventional example of FIG. However, the capacitor and the word line 7a,
7d is omitted from the drawing.

As shown in FIG. 10, the basic structure is the same as that of the example of FIG. 16, but the remarkably different points are over the respective side surfaces of the gate electrodes 7b and 7c and the respective side surfaces of the interlayer insulating layer 9. That is, the nitride film 14 is selectively formed. FIG. 11 is a plan view of FIG.

Next, a method of manufacturing the device shown in FIG. 10 will be described with reference to FIGS. 12 to 14. FIG. 12 is a plan view, and FIG.
13 is a sectional view taken along line XIII-XIII in FIG. 12, and FIG. 14 is a sectional view of FIG.
FIG. 4 is a sectional view taken along line XIV-XIV.

First, as shown in FIGS. 12A, 13A and 14A,
After the same steps as those in FIG. 4A described above, the gate oxide film 5 is further removed by etching through the same steps as those in FIGS. 4B and 4C to obtain the same as FIGS. 12B, 13B, and 14B. As shown, the polysilicon layer 7 and the gate oxide film 5 are left only in predetermined regions.

Next, as shown in FIGS. 12C, 13C, and 14C, ions 50 of an N-type impurity (for example, As) are selectively implanted into a predetermined region by an ion implantation method, and the source region 8 is respectively formed by annealing thereafter. Form, then 12D
As shown in FIGS. 13 and 14D, an interlayer insulating layer 9 is formed on the entire surface by CVD, and a predetermined region is covered with a mask (for example, a photoresist) 60.

Next, FIGS. 13E to 13H show FIGS.
The device shown in FIG. 10 is completed by performing each wiring process and the like through the same steps as in FIG. 4H.

As described above, according to the device and the method of manufacturing the same according to the present embodiment, the nitride film extends over the respective side surfaces of the gate electrodes 7b and 7c and the respective side surfaces of the interlayer insulating layer 9 as in the above-described example. Since 14 is selectively formed, there is an advantage similar to the above-described example. That is, as shown in FIG. 11, as compared with the conventional FIG. 17, a layout pattern having a high integration density can be easily realized, and a device having extremely high reliability can be easily manufactured.

FIG. 15 shows still another example of the present invention, which is a modification of the example shown in FIG.

That is, although the basic structure is the same as that of the example of FIG. 10, the description is omitted, but the other difference is that the oxide film is formed in the groove 31 formed in the P-type silicon substrate 1 as shown in FIG. Polysilicon 32 doped with N-type (for example, containing phosphorus or the like at a high concentration) is filled through 3, and capacitors formed of the oxide film 3 and the polysilicon layer 32 are connected to the source region 8, respectively. That is. In this example, the substrate 1
The charge is accumulated inside the trench 3 (polysilicon layer 32) with the side grounded.

Therefore, it is needless to say that there is the same point as in the above-mentioned example. However, in this case, since the capacitor is constituted by the groove 3, the capacity of the capacitor can be increased and the integration degree can be improved. It is very advantageous. Also, in this case, no new technology is required, and the device shown in FIG. 15 can be easily manufactured by using the conventional etching technology or the like.

Although the present invention has been described above, the above-described example can be further modified based on the technical idea of the present invention.

For example, in the above-described example, nitride is used for the insulating coating film 14 selectively formed over the side surface of the gate electrode (for example, 7b) and the side surface of the interlayer insulating layer 9, but other materials such as an oxide film may be used. An appropriate material may be employed (for example, any material having an insulating property may be used). In addition, the interlayer insulating layer 9 may be made of, for example, PSG or S in addition to BPSG.
iO ₂ or the like may be used.

The gate electrode (for example, 7b) and the polysilicon layer 15 described above can be made of any suitable material such as titanium, tungsten, molybdenum or other high-melting metal, or silicide which is a compound of metal and Si, in addition to Al. In this case, it is naturally advantageous for high-speed operation of the device.

In the above example, N ⁺ -type diffusion layer (e.g. the drain region 12) is formed of went forming step such as polysilicon layer 15, the polysilicon layer after the formation of the example N ⁺ -type diffusion layer 15
May be formed. Diffusion may be performed by an appropriate optical excitation treatment such as laser annealing or lamp annealing in addition to thermal diffusion.

It is needless to say that the conductivity type of each of the above-mentioned regions may be changed, and the present invention can be applied to an appropriate device such as a static RAM in addition to the dynamic RAM.

F. Advantageous Effects of the Invention As described above, the present invention has an insulating coating film selectively formed over the side surface of the first conductive layer and the side surface of the interlayer insulating layer. Since there is no contact hole, there is no need to worry about an electrical short circuit due to a mask alignment shift or the like, and no extra area is required in consideration of a mask alignment shift or the like when forming a contact hole. The area such as a region can be reduced, and the degree of integration can be improved.
Also. Since the above-mentioned extra area is not required, it is not necessary to reduce the area occupied by the contact holes more than necessary for high integration. Therefore, high integration can be achieved while ensuring sufficient step coverage of the semiconductor material in the contact holes and the like. Further, since the area of the element region and the like can be reduced as described above, it is possible to provide a highly reliable semiconductor device manufacturing method capable of reducing unnecessary power consumption and parasitic capacitance.

[Brief description of the drawings]

1 to 15 show an embodiment of the present invention. FIG. 1 is a sectional view of a MOS transistor (I in FIG. 2 to be described later).
2 is a plan view of FIG. 1, FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG.
3G, 3H, and 3I are plan views (FIGS. 4A to 4C to be described later) sequentially showing the main steps of the method of manufacturing the device of FIG.
4I), FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG.
4G, 4H and 4I are cross-sectional views (cross-sectional views taken along line IV-IV corresponding to FIGS. 3A to 3I) sequentially showing the main steps of the method of manufacturing the device of FIG. 5 is a cross-sectional view of a device according to another example (a cross-sectional view taken along line VV in FIG. 6 described later), FIG. 6 is a plan view of FIG. 5, FIG. 7A, FIG. 7B, FIG. Fig. 7D, Fig. 7E, Fig. 7F,
FIGS. 7G, 7H and 7I are plan views (FIGS. 8A to 8C to be described later) showing the method of manufacturing the device of FIG.
8I and plan views corresponding to FIGS. 9A to 9I, respectively, except for drawings corresponding to FIGS. 8J to 8N. ), 8A, 8B, 8C, 8D, 8E, 8F,
8G, 8H, 8I, 8J, 8K, 8L, 8M
8N are cross-sectional views (VIII corresponding to each of FIG. 7) sequentially showing the main steps of the method of manufacturing the device of FIG.
9A, 9B, 9C, 9D, 9E, 9F,
9G, 9H, and 9I are cross-sectional views (IX-IX line cross-sectional views corresponding to FIG. 7, respectively) sequentially showing main steps of a method of manufacturing the device of FIG. Similarly, FIG. 9J and subsequent figures are not shown.), FIG. 10 is a cross-sectional view of a device according to another example (a cross-sectional view taken along the line XX of FIG. 11 described later), and FIG. FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D, and FIG.
Plan views sequentially showing main steps of a method of manufacturing the device shown in the figure (plan views corresponding to FIGS. 13A to 13E and FIGS. 14A to 14E to be described later, but illustrations after FIG. 12F are omitted. 13A, 13B, 13C, 13D, 13E, and 13F.
13G and 13H are cross-sectional views (cross-sectional views taken along the line XIII-XIII corresponding to each of FIG. 12) sequentially showing main steps of a method of manufacturing the device of FIG. 10, FIGS. 14A and 14B Figures, 14C, 14D, 14E, 14F
FIGS. 14G and 14H are cross-sectional views (cross-sectional views taken along the line XIV-XIV corresponding to each of FIG. 12) sequentially showing main steps of a method of manufacturing the device of FIG. 10, and FIG. It is sectional drawing of the device which shows the example of FIG. 16 and 17 show a conventional device, respectively. FIG. 16 is a cross-sectional view of the device (a cross-sectional view taken along line XVI-XVI in FIG. 17), and FIG. 17 is a cross-sectional view of the device of FIG. It is a top view. In the reference numerals shown in the drawings, 1... P-type silicon substrate 2... Field oxide film 3 6 oxide film 4 field plate 5 gate oxide film 7 7 a 7 b 7 c 7 d 7 e , 7f, 7g, 7h ... gate electrode (word line: first conductive layer) 8 ... source region (diffusion layer) 9 ... interlayer insulating layer 10 ... contact hole 11, 15 ... polysilicon layer (second Conductive layer) 12 Drain region (diffusion layer) 13 Element region 14 A nitride film (insulating coating film).

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 H01L 29/78

Claims (1)

(57) [Claims] A step of forming an insulating film on one main surface of the semiconductor substrate; a step of forming a first conductive layer on the insulating film; and a step of forming an interlayer insulating layer on the first conductive layer. Patterning the first conductive layer and the interlayer insulating layer into the same pattern; and selectively forming an insulating coating film over a side surface of the first conductive layer and a side surface of the interlayer insulating layer. Forming a diffusion layer under the contact hole existing on the one main surface without the insulating coating film using the insulating coating film as a mask; and applying a second conductive layer to the contact hole. A method for manufacturing a semiconductor device, comprising: